diff --git a/arch/arm/mach-omap2/vc.c b/arch/arm/mach-omap2/vc.c index 72c9cb64a42bd7c4ed486f99a722f03d5551bd14..1791f79112bf92ee42f686af23c6738bb28f7832 100644 --- a/arch/arm/mach-omap2/vc.c +++ b/arch/arm/mach-omap2/vc.c @@ -19,6 +19,52 @@ #include "prm-regbits-44xx.h" #include "prm44xx.h" +/* + * Channel configuration bits, common for OMAP3 & 4 + * OMAP3 register: PRM_VC_CH_CONF + * OMAP4 register: PRM_VC_CFG_CHANNEL + */ +#define CFG_CHANNEL_SA BIT(0) +#define CFG_CHANNEL_RAV BIT(1) +#define CFG_CHANNEL_RAC BIT(2) +#define CFG_CHANNEL_RACEN BIT(3) +#define CFG_CHANNEL_CMD BIT(4) +#define CFG_CHANNEL_MASK 0x3f + +/** + * omap_vc_config_channel - configure VC channel to PMIC mappings + * @voltdm: pointer to voltagdomain defining the desired VC channel + * + * Configures the VC channel to PMIC mappings for the following + * PMIC settings + * - i2c slave address (SA) + * - voltage configuration address (RAV) + * - command configuration address (RAC) and enable bit (RACEN) + * - command values for ON, ONLP, RET and OFF (CMD) + * + * This function currently only allows flexible configuration of the + * non-default channel. Starting with OMAP4, there are more than 2 + * channels, with one defined as the default (on OMAP4, it's MPU.) + * Only the non-default channel can be configured. + */ +static int omap_vc_config_channel(struct voltagedomain *voltdm) +{ + struct omap_vc_channel *vc = voltdm->vc; + + /* + * For default channel, the only configurable bit is RACEN. + * All others must stay at zero (see function comment above.) + */ + if (vc->flags & OMAP_VC_CHANNEL_DEFAULT) + vc->cfg_channel &= CFG_CHANNEL_RACEN; + + voltdm->rmw(CFG_CHANNEL_MASK << vc->cfg_channel_sa_shift, + vc->cfg_channel << vc->cfg_channel_sa_shift, + vc->common->cfg_channel_reg); + + return 0; +} + /* Voltage scale and accessory APIs */ int omap_vc_pre_scale(struct voltagedomain *voltdm, unsigned long target_volt, @@ -166,8 +212,6 @@ static void __init omap3_vc_init_channel(struct voltagedomain *voltdm) * Generic VC parameters init * XXX This data should be abstracted out */ - voltdm->write(OMAP3430_CMD1_MASK | OMAP3430_RAV1_MASK, - OMAP3_PRM_VC_CH_CONF_OFFSET); voltdm->write(OMAP3430_MCODE_SHIFT | OMAP3430_HSEN_MASK, OMAP3_PRM_VC_I2C_CFG_OFFSET); @@ -186,15 +230,6 @@ static void __init omap4_vc_init_channel(struct voltagedomain *voltdm) if (is_initialized) return; - /* - * Generic VC parameters init - * XXX This data should be abstracted out - */ - vc_val = (OMAP4430_RAV_VDD_MPU_L_MASK | OMAP4430_CMD_VDD_MPU_L_MASK | - OMAP4430_RAV_VDD_IVA_L_MASK | OMAP4430_CMD_VDD_IVA_L_MASK | - OMAP4430_RAV_VDD_CORE_L_MASK | OMAP4430_CMD_VDD_CORE_L_MASK); - voltdm->write(vc_val, OMAP4_PRM_VC_CFG_CHANNEL_OFFSET); - /* XXX These are magic numbers and do not belong! */ vc_val = (0x60 << OMAP4430_SCLL_SHIFT | 0x26 << OMAP4430_SCLH_SHIFT); voltdm->write(vc_val, OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET); @@ -222,6 +257,8 @@ void __init omap_vc_init_channel(struct voltagedomain *voltdm) return; } + vc->cfg_channel = 0; + /* get PMIC/board specific settings */ vc->i2c_slave_addr = vdd->pmic_info->i2c_slave_addr; vc->volt_reg_addr = vdd->pmic_info->volt_reg_addr; @@ -232,6 +269,7 @@ void __init omap_vc_init_channel(struct voltagedomain *voltdm) voltdm->rmw(vc->smps_sa_mask, vc->i2c_slave_addr << __ffs(vc->smps_sa_mask), vc->common->smps_sa_reg); + vc->cfg_channel |= CFG_CHANNEL_SA; /* * Configure the PMIC register addresses. @@ -239,10 +277,14 @@ void __init omap_vc_init_channel(struct voltagedomain *voltdm) voltdm->rmw(vc->smps_volra_mask, vc->volt_reg_addr << __ffs(vc->smps_volra_mask), vc->common->smps_volra_reg); - if (vc->cmd_reg_addr) + vc->cfg_channel |= CFG_CHANNEL_RAV; + + if (vc->cmd_reg_addr) { voltdm->rmw(vc->smps_cmdra_mask, vc->cmd_reg_addr << __ffs(vc->smps_cmdra_mask), vc->common->smps_cmdra_reg); + vc->cfg_channel |= CFG_CHANNEL_RAC | CFG_CHANNEL_RACEN; + } /* Set up the on, inactive, retention and off voltage */ on_vsel = vdd->pmic_info->uv_to_vsel(vdd->pmic_info->on_volt); @@ -254,6 +296,10 @@ void __init omap_vc_init_channel(struct voltagedomain *voltdm) (ret_vsel << vc->common->cmd_ret_shift) | (off_vsel << vc->common->cmd_off_shift)); voltdm->write(val, vc->cmdval_reg); + vc->cfg_channel |= CFG_CHANNEL_CMD; + + /* Channel configuration */ + omap_vc_config_channel(voltdm); /* Configure the setup times */ voltdm->rmw(voltdm->vfsm->voltsetup_mask, diff --git a/arch/arm/mach-omap2/vc.h b/arch/arm/mach-omap2/vc.h index 6e8806b598237db0b559674eb9b87c2ac00b41b9..4e1913748d2a02461b9d686ac352dfcf7a64972d 100644 --- a/arch/arm/mach-omap2/vc.h +++ b/arch/arm/mach-omap2/vc.h @@ -54,8 +54,12 @@ struct omap_vc_common { u8 cmd_onlp_shift; u8 cmd_ret_shift; u8 cmd_off_shift; + u8 cfg_channel_reg; }; +/* omap_vc_channel.flags values */ +#define OMAP_VC_CHANNEL_DEFAULT BIT(0) + /** * struct omap_vc_channel - VC per-instance data * @i2c_slave_addr: I2C slave address of PMIC for this VC channel @@ -67,6 +71,7 @@ struct omap_vc_common { * @smps_volra_mask: VOLRA* bitmask in the PRM_VC_VOL_RA register * @smps_cmdra_mask: CMDRA* bitmask in the PRM_VC_CMD_RA register * @cmdval_reg: register for on/ret/off voltage level values for this channel + * @flags: VC channel-specific flags (optional) */ struct omap_vc_channel { /* channel state */ @@ -74,6 +79,7 @@ struct omap_vc_channel { u16 volt_reg_addr; u16 cmd_reg_addr; u16 setup_time; + u8 cfg_channel; /* register access data */ const struct omap_vc_common *common; @@ -81,6 +87,8 @@ struct omap_vc_channel { u32 smps_volra_mask; u32 smps_cmdra_mask; u8 cmdval_reg; + u8 cfg_channel_sa_shift; + u8 flags; }; extern struct omap_vc_channel omap3_vc_mpu; diff --git a/arch/arm/mach-omap2/vc3xxx_data.c b/arch/arm/mach-omap2/vc3xxx_data.c index df8bd5ead7e43ad1ac620559cf8bfc6df481ddc5..f4449eb59841bd7575c1a726f847755858b373a7 100644 --- a/arch/arm/mach-omap2/vc3xxx_data.c +++ b/arch/arm/mach-omap2/vc3xxx_data.c @@ -43,6 +43,7 @@ static struct omap_vc_common omap3_vc_common = { .cmd_onlp_shift = OMAP3430_VC_CMD_ONLP_SHIFT, .cmd_ret_shift = OMAP3430_VC_CMD_RET_SHIFT, .cmd_off_shift = OMAP3430_VC_CMD_OFF_SHIFT, + .cfg_channel_reg = OMAP3_PRM_VC_CH_CONF_OFFSET, }; struct omap_vc_channel omap3_vc_mpu = { @@ -51,6 +52,7 @@ struct omap_vc_channel omap3_vc_mpu = { .smps_sa_mask = OMAP3430_PRM_VC_SMPS_SA_SA0_MASK, .smps_volra_mask = OMAP3430_VOLRA0_MASK, .smps_cmdra_mask = OMAP3430_CMDRA0_MASK, + .cfg_channel_sa_shift = OMAP3430_PRM_VC_SMPS_SA_SA0_SHIFT, }; struct omap_vc_channel omap3_vc_core = { @@ -59,4 +61,5 @@ struct omap_vc_channel omap3_vc_core = { .smps_sa_mask = OMAP3430_PRM_VC_SMPS_SA_SA1_MASK, .smps_volra_mask = OMAP3430_VOLRA1_MASK, .smps_cmdra_mask = OMAP3430_CMDRA1_MASK, + .cfg_channel_sa_shift = OMAP3430_PRM_VC_SMPS_SA_SA1_SHIFT, }; diff --git a/arch/arm/mach-omap2/vc44xx_data.c b/arch/arm/mach-omap2/vc44xx_data.c index 5d104ff662b32c2fe75405e13cac5a6623209354..1610bdedee6b9356f0030ca69b15ba59bafc53d6 100644 --- a/arch/arm/mach-omap2/vc44xx_data.c +++ b/arch/arm/mach-omap2/vc44xx_data.c @@ -44,15 +44,18 @@ static const struct omap_vc_common omap4_vc_common = { .cmd_onlp_shift = OMAP4430_ONLP_SHIFT, .cmd_ret_shift = OMAP4430_RET_SHIFT, .cmd_off_shift = OMAP4430_OFF_SHIFT, + .cfg_channel_reg = OMAP4_PRM_VC_CFG_CHANNEL_OFFSET, }; /* VC instance data for each controllable voltage line */ struct omap_vc_channel omap4_vc_mpu = { + .flags = OMAP_VC_CHANNEL_DEFAULT, .common = &omap4_vc_common, .cmdval_reg = OMAP4_PRM_VC_VAL_CMD_VDD_MPU_L_OFFSET, .smps_sa_mask = OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_MASK, .smps_volra_mask = OMAP4430_VOLRA_VDD_MPU_L_MASK, .smps_cmdra_mask = OMAP4430_CMDRA_VDD_MPU_L_MASK, + .cfg_channel_sa_shift = OMAP4430_SA_VDD_MPU_L_SHIFT, }; struct omap_vc_channel omap4_vc_iva = { @@ -61,6 +64,7 @@ struct omap_vc_channel omap4_vc_iva = { .smps_sa_mask = OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_MASK, .smps_volra_mask = OMAP4430_VOLRA_VDD_IVA_L_MASK, .smps_cmdra_mask = OMAP4430_CMDRA_VDD_IVA_L_MASK, + .cfg_channel_sa_shift = OMAP4430_SA_VDD_IVA_L_SHIFT, }; struct omap_vc_channel omap4_vc_core = { @@ -69,5 +73,6 @@ struct omap_vc_channel omap4_vc_core = { .smps_sa_mask = OMAP4430_SA_VDD_CORE_L_0_6_MASK, .smps_volra_mask = OMAP4430_VOLRA_VDD_CORE_L_MASK, .smps_cmdra_mask = OMAP4430_CMDRA_VDD_CORE_L_MASK, + .cfg_channel_sa_shift = OMAP4430_SA_VDD_CORE_L_SHIFT, };