Intel: intel_rapl: support 64 bit register
mainline inclusion from mainline-v5.3-rc1 commit d978e755 category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/I47H3V CVE: NA -------------------------------- commit d978e755 upstream. RAPL MMIO interface uses 64 bit registers, thus force use 64 bit register for all the RAPL code. Reviewed-by: NPandruvada, Srinivas <srinivas.pandruvada@intel.com> Tested-by: NPandruvada, Srinivas <srinivas.pandruvada@intel.com> Signed-off-by: NZhang Rui <rui.zhang@intel.com> Signed-off-by: NRafael J. Wysocki <rafael.j.wysocki@intel.com> Signed-off-by: NYouquan Song <youquan.song@intel.com> Signed-off-by: NJackie Liu <liuyun01@kylinos.cn> Signed-off-by: NZheng Zengkai <zhengzengkai@huawei.com> Reviewed-by: NHanjun Guo <guohanjun@huawei.com> Reviewed-by: NXie XiuQi <xiexiuqi@huawei.com> Signed-off-by: NYang Yingliang <yangyingliang@huawei.com>
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