提交 23107802 编写于 作者: G Gabor Juhos 提交者: Ralf Baechle

MIPS: ath79: Use a helper function to get system clock rates

The ath79 platform uses similar code to get the
rate of various clocks during init. Separate the
similar code into a new helper function and use
that to avoid code duplication.
Signed-off-by: NGabor Juhos <juhosg@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5778/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
上级 837f036c
...@@ -400,6 +400,22 @@ void __init ath79_clocks_init(void) ...@@ -400,6 +400,22 @@ void __init ath79_clocks_init(void)
(ath79_ref_clk.rate / 1000) % 1000); (ath79_ref_clk.rate / 1000) % 1000);
} }
unsigned long __init
ath79_get_sys_clk_rate(const char *id)
{
struct clk *clk;
unsigned long rate;
clk = clk_get(NULL, id);
if (IS_ERR(clk))
panic("unable to get %s clock, err=%d", id, (int) PTR_ERR(clk));
rate = clk_get_rate(clk);
clk_put(clk);
return rate;
}
/* /*
* Linux clock API * Linux clock API
*/ */
......
...@@ -21,6 +21,8 @@ ...@@ -21,6 +21,8 @@
#define ATH79_MEM_SIZE_MAX (128 * 1024 * 1024) #define ATH79_MEM_SIZE_MAX (128 * 1024 * 1024)
void ath79_clocks_init(void); void ath79_clocks_init(void);
unsigned long ath79_get_sys_clk_rate(const char *id);
void ath79_ddr_wb_flush(unsigned int reg); void ath79_ddr_wb_flush(unsigned int reg);
void ath79_gpio_function_enable(u32 mask); void ath79_gpio_function_enable(u32 mask);
......
...@@ -81,21 +81,19 @@ static struct platform_device ar933x_uart_device = { ...@@ -81,21 +81,19 @@ static struct platform_device ar933x_uart_device = {
void __init ath79_register_uart(void) void __init ath79_register_uart(void)
{ {
struct clk *clk; unsigned long uart_clk_rate;
clk = clk_get(NULL, "uart"); uart_clk_rate = ath79_get_sys_clk_rate("uart");
if (IS_ERR(clk))
panic("unable to get UART clock, err=%ld", PTR_ERR(clk));
if (soc_is_ar71xx() || if (soc_is_ar71xx() ||
soc_is_ar724x() || soc_is_ar724x() ||
soc_is_ar913x() || soc_is_ar913x() ||
soc_is_ar934x() || soc_is_ar934x() ||
soc_is_qca955x()) { soc_is_qca955x()) {
ath79_uart_data[0].uartclk = clk_get_rate(clk); ath79_uart_data[0].uartclk = uart_clk_rate;
platform_device_register(&ath79_uart_device); platform_device_register(&ath79_uart_device);
} else if (soc_is_ar933x()) { } else if (soc_is_ar933x()) {
ar933x_uart_data.uartclk = clk_get_rate(clk); ar933x_uart_data.uartclk = uart_clk_rate;
platform_device_register(&ar933x_uart_device); platform_device_register(&ar933x_uart_device);
} else { } else {
BUG(); BUG();
......
...@@ -209,13 +209,11 @@ void __init plat_mem_setup(void) ...@@ -209,13 +209,11 @@ void __init plat_mem_setup(void)
void __init plat_time_init(void) void __init plat_time_init(void)
{ {
struct clk *clk; unsigned long cpu_clk_rate;
clk = clk_get(NULL, "cpu"); cpu_clk_rate = ath79_get_sys_clk_rate("cpu");
if (IS_ERR(clk))
panic("unable to get CPU clock, err=%ld", PTR_ERR(clk));
mips_hpt_frequency = clk_get_rate(clk) / 2; mips_hpt_frequency = cpu_clk_rate / 2;
} }
static int __init ath79_setup(void) static int __init ath79_setup(void)
......
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