arm64: Document ICC_CTLR_EL3.PMHE setting requirements

mainline inclusion
from mainline-5.5-rc1
commit 7e3a57fa
category: bugfix
bugzilla: 23209
CVE: NA
---------------------------

It goes without saying, but better saying it: the kernel expects
ICC_CTLR_EL3.PMHE to have the same value across all CPUs, and
for that setting not to change during the lifetime of the kernel.
Signed-off-by: NMarc Zyngier <maz@kernel.org>
Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
Signed-off-by: NWei Li <liwei391@huawei.com>
Reviewed-by: NHanjun Guo <guohanjun@huawei.com>
Signed-off-by: NYang Yingliang <yangyingliang@huawei.com>

Documentation/arm64/booting.txt

@@ -197,6 +197,9 @@ Before jumping into the kernel, the following conditions must be met:
   - If EL3 is present:
     ICC_SRE_EL3.Enable (bit 3) must be initialiased to 0b1.
     ICC_SRE_EL3.SRE (bit 0) must be initialised to 0b1.
+    ICC_CTLR_EL3.PMHE (bit 6) must be set to the same value across
+    all CPUs the kernel is executing on, and must stay constant
+    for the lifetime of the kernel.
   - If the kernel is entered at EL1:
     ICC.SRE_EL2.Enable (bit 3) must be initialised to 0b1
     ICC_SRE_EL2.SRE (bit 0) must be initialised to 0b1.