From 2287c1747859d0c29e52ba7b7cec649d98c7dab5 Mon Sep 17 00:00:00 2001 From: Marc Zyngier Date: Thu, 12 Dec 2019 09:56:53 +0800 Subject: [PATCH] arm64: Document ICC_CTLR_EL3.PMHE setting requirements mainline inclusion from mainline-5.5-rc1 commit 7e3a57fa6ca8 category: bugfix bugzilla: 23209 CVE: NA --------------------------- It goes without saying, but better saying it: the kernel expects ICC_CTLR_EL3.PMHE to have the same value across all CPUs, and for that setting not to change during the lifetime of the kernel. Signed-off-by: Marc Zyngier Signed-off-by: Catalin Marinas Signed-off-by: Wei Li Reviewed-by: Hanjun Guo Signed-off-by: Yang Yingliang --- Documentation/arm64/booting.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/arm64/booting.txt b/Documentation/arm64/booting.txt index e38793899c18..2890ece8625f 100644 --- a/Documentation/arm64/booting.txt +++ b/Documentation/arm64/booting.txt @@ -197,6 +197,9 @@ Before jumping into the kernel, the following conditions must be met: - If EL3 is present: ICC_SRE_EL3.Enable (bit 3) must be initialiased to 0b1. ICC_SRE_EL3.SRE (bit 0) must be initialised to 0b1. + ICC_CTLR_EL3.PMHE (bit 6) must be set to the same value across + all CPUs the kernel is executing on, and must stay constant + for the lifetime of the kernel. - If the kernel is entered at EL1: ICC.SRE_EL2.Enable (bit 3) must be initialised to 0b1 ICC_SRE_EL2.SRE (bit 0) must be initialised to 0b1. -- GitLab