From 226dcefe706ff8854bca1bb75ae7bfd2fe3296c5 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Thu, 20 Aug 2015 14:54:08 +1000 Subject: [PATCH] drm/nouveau/sw: cosmetic changes This is purely preparation for upcoming commits, there should be no code changes here. Signed-off-by: Ben Skeggs --- .../gpu/drm/nouveau/include/nvkm/engine/sw.h | 8 ++--- .../gpu/drm/nouveau/nvkm/engine/sw/gf100.c | 20 ++++++------- drivers/gpu/drm/nouveau/nvkm/engine/sw/nv04.c | 28 +++++++---------- drivers/gpu/drm/nouveau/nvkm/engine/sw/nv10.c | 28 +++++++---------- drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.c | 30 +++++++++---------- drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.h | 4 --- 6 files changed, 49 insertions(+), 69 deletions(-) diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/sw.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/sw.h index a529013c92ab..c46e5595573b 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/engine/sw.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/sw.h @@ -25,17 +25,17 @@ struct nvkm_sw_chan { #include struct nvkm_sw { - struct nvkm_engine base; + struct nvkm_engine engine; }; #define nvkm_sw_create(p,e,c,d) \ nvkm_engine_create((p), (e), (c), true, "SW", "software", (d)) #define nvkm_sw_destroy(d) \ - nvkm_engine_destroy(&(d)->base) + nvkm_engine_destroy(&(d)->engine) #define nvkm_sw_init(d) \ - nvkm_engine_init(&(d)->base) + nvkm_engine_init(&(d)->engine) #define nvkm_sw_fini(d,s) \ - nvkm_engine_fini(&(d)->base, (s)) + nvkm_engine_fini(&(d)->engine, (s)) #define _nvkm_sw_dtor _nvkm_engine_dtor #define _nvkm_sw_init _nvkm_engine_init diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sw/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/sw/gf100.c index 533d5d8ed363..b35b45931cbd 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/sw/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/sw/gf100.c @@ -50,20 +50,20 @@ gf100_sw_mthd_mp_control(struct nvkm_object *object, u32 mthd, void *args, u32 size) { struct nv50_sw_chan *chan = (void *)nv_engctx(object->parent); - struct nv50_sw_priv *priv = (void *)nv_object(chan)->engine; + struct nvkm_sw *sw = (void *)nv_object(chan)->engine; u32 data = *(u32 *)args; switch (mthd) { case 0x600: - nv_wr32(priv, 0x419e00, data); /* MP.PM_UNK000 */ + nv_wr32(sw, 0x419e00, data); /* MP.PM_UNK000 */ break; case 0x644: if (data & ~0x1ffffe) return -EINVAL; - nv_wr32(priv, 0x419e44, data); /* MP.TRAP_WARP_ERROR_EN */ + nv_wr32(sw, 0x419e44, data); /* MP.TRAP_WARP_ERROR_EN */ break; case 0x6ac: - nv_wr32(priv, 0x419eac, data); /* MP.PM_UNK0AC */ + nv_wr32(sw, 0x419eac, data); /* MP.PM_UNK0AC */ break; default: return -EINVAL; @@ -99,14 +99,14 @@ gf100_sw_vblsem_release(struct nvkm_notify *notify) { struct nv50_sw_chan *chan = container_of(notify, typeof(*chan), vblank.notify[notify->index]); - struct nv50_sw_priv *priv = (void *)nv_object(chan)->engine; - struct nvkm_bar *bar = nvkm_bar(priv); + struct nvkm_sw *sw = (void *)nv_object(chan)->engine; + struct nvkm_bar *bar = nvkm_bar(sw); - nv_wr32(priv, 0x001718, 0x80000000 | chan->vblank.channel); + nv_wr32(sw, 0x001718, 0x80000000 | chan->vblank.channel); bar->flush(bar); - nv_wr32(priv, 0x06000c, upper_32_bits(chan->vblank.offset)); - nv_wr32(priv, 0x060010, lower_32_bits(chan->vblank.offset)); - nv_wr32(priv, 0x060014, chan->vblank.value); + nv_wr32(sw, 0x06000c, upper_32_bits(chan->vblank.offset)); + nv_wr32(sw, 0x060010, lower_32_bits(chan->vblank.offset)); + nv_wr32(sw, 0x060014, chan->vblank.value); return NVKM_NOTIFY_DROP; } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv04.c index 897024421d36..f1bb1e6f35a1 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv04.c @@ -24,14 +24,6 @@ #include #include -struct nv04_sw_priv { - struct nvkm_sw base; -}; - -struct nv04_sw_chan { - struct nvkm_sw_chan base; -}; - /******************************************************************************* * software object classes ******************************************************************************/ @@ -48,9 +40,9 @@ nv04_sw_set_ref(struct nvkm_object *object, u32 mthd, void *data, u32 size) static int nv04_sw_flip(struct nvkm_object *object, u32 mthd, void *args, u32 size) { - struct nv04_sw_chan *chan = (void *)nv_engctx(object->parent); - if (chan->base.flip) - return chan->base.flip(chan->base.flip_data); + struct nvkm_sw_chan *chan = (void *)nv_engctx(object->parent); + if (chan->flip) + return chan->flip(chan->flip_data); return -EINVAL; } @@ -76,7 +68,7 @@ nv04_sw_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) { - struct nv04_sw_chan *chan; + struct nvkm_sw_chan *chan; int ret; ret = nvkm_sw_context_create(parent, engine, oclass, &chan); @@ -113,17 +105,17 @@ nv04_sw_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) { - struct nv04_sw_priv *priv; + struct nvkm_sw *sw; int ret; - ret = nvkm_sw_create(parent, engine, oclass, &priv); - *pobject = nv_object(priv); + ret = nvkm_sw_create(parent, engine, oclass, &sw); + *pobject = nv_object(sw); if (ret) return ret; - nv_engine(priv)->cclass = &nv04_sw_cclass; - nv_engine(priv)->sclass = nv04_sw_sclass; - nv_subdev(priv)->intr = nv04_sw_intr; + nv_engine(sw)->cclass = &nv04_sw_cclass; + nv_engine(sw)->sclass = nv04_sw_sclass; + nv_subdev(sw)->intr = nv04_sw_intr; return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv10.c b/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv10.c index c61153a3fb8b..1288142437b7 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv10.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv10.c @@ -23,14 +23,6 @@ */ #include -struct nv10_sw_priv { - struct nvkm_sw base; -}; - -struct nv10_sw_chan { - struct nvkm_sw_chan base; -}; - /******************************************************************************* * software object classes ******************************************************************************/ @@ -38,9 +30,9 @@ struct nv10_sw_chan { static int nv10_sw_flip(struct nvkm_object *object, u32 mthd, void *args, u32 size) { - struct nv10_sw_chan *chan = (void *)nv_engctx(object->parent); - if (chan->base.flip) - return chan->base.flip(chan->base.flip_data); + struct nvkm_sw_chan *chan = (void *)nv_engctx(object->parent); + if (chan->flip) + return chan->flip(chan->flip_data); return -EINVAL; } @@ -65,7 +57,7 @@ nv10_sw_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) { - struct nv10_sw_chan *chan; + struct nvkm_sw_chan *chan; int ret; ret = nvkm_sw_context_create(parent, engine, oclass, &chan); @@ -96,17 +88,17 @@ nv10_sw_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) { - struct nv10_sw_priv *priv; + struct nvkm_sw *sw; int ret; - ret = nvkm_sw_create(parent, engine, oclass, &priv); - *pobject = nv_object(priv); + ret = nvkm_sw_create(parent, engine, oclass, &sw); + *pobject = nv_object(sw); if (ret) return ret; - nv_engine(priv)->cclass = &nv10_sw_cclass; - nv_engine(priv)->sclass = nv10_sw_sclass; - nv_subdev(priv)->intr = nv04_sw_intr; + nv_engine(sw)->cclass = &nv10_sw_cclass; + nv_engine(sw)->sclass = nv10_sw_sclass; + nv_subdev(sw)->intr = nv04_sw_intr; return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.c index 0946280a54b0..af2c1afaae55 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.c @@ -121,19 +121,19 @@ nv50_sw_vblsem_release(struct nvkm_notify *notify) { struct nv50_sw_chan *chan = container_of(notify, typeof(*chan), vblank.notify[notify->index]); - struct nv50_sw_priv *priv = (void *)nv_object(chan)->engine; - struct nvkm_bar *bar = nvkm_bar(priv); + struct nvkm_sw *sw = (void *)nv_object(chan)->engine; + struct nvkm_bar *bar = nvkm_bar(sw); - nv_wr32(priv, 0x001704, chan->vblank.channel); - nv_wr32(priv, 0x001710, 0x80000000 | chan->vblank.ctxdma); + nv_wr32(sw, 0x001704, chan->vblank.channel); + nv_wr32(sw, 0x001710, 0x80000000 | chan->vblank.ctxdma); bar->flush(bar); - if (nv_device(priv)->chipset == 0x50) { - nv_wr32(priv, 0x001570, chan->vblank.offset); - nv_wr32(priv, 0x001574, chan->vblank.value); + if (nv_device(sw)->chipset == 0x50) { + nv_wr32(sw, 0x001570, chan->vblank.offset); + nv_wr32(sw, 0x001574, chan->vblank.value); } else { - nv_wr32(priv, 0x060010, chan->vblank.offset); - nv_wr32(priv, 0x060014, chan->vblank.value); + nv_wr32(sw, 0x060010, chan->vblank.offset); + nv_wr32(sw, 0x060014, chan->vblank.value); } return NVKM_NOTIFY_DROP; @@ -205,17 +205,17 @@ nv50_sw_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_object **pobject) { struct nv50_sw_oclass *pclass = (void *)oclass; - struct nv50_sw_priv *priv; + struct nvkm_sw *sw; int ret; - ret = nvkm_sw_create(parent, engine, oclass, &priv); - *pobject = nv_object(priv); + ret = nvkm_sw_create(parent, engine, oclass, &sw); + *pobject = nv_object(sw); if (ret) return ret; - nv_engine(priv)->cclass = pclass->cclass; - nv_engine(priv)->sclass = pclass->sclass; - nv_subdev(priv)->intr = nv04_sw_intr; + nv_engine(sw)->cclass = pclass->cclass; + nv_engine(sw)->sclass = pclass->sclass; + nv_subdev(sw)->intr = nv04_sw_intr; return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.h b/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.h index d8adc1108467..1c9101bff894 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.h @@ -9,10 +9,6 @@ struct nv50_sw_oclass { struct nvkm_oclass *sclass; }; -struct nv50_sw_priv { - struct nvkm_sw base; -}; - int nv50_sw_ctor(struct nvkm_object *, struct nvkm_object *, struct nvkm_oclass *, void *, u32, struct nvkm_object **); -- GitLab