diff --git a/arch/arm64/boot/dts/hisilicon/hip06.dtsi b/arch/arm64/boot/dts/hisilicon/hip06.dtsi
index f2fe076bb7deaeca416914581f566439c9cd7a21..29b5739955a3b4c8328fcac9c9b072afcb9fc997 100644
--- a/arch/arm64/boot/dts/hisilicon/hip06.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hip06.dtsi
@@ -298,6 +298,14 @@
 			#interrupt-cells = <2>;
 			num-pins = <10>;
 		};
+
+		mbigen_smmu_pcie_intc: intc_smmu_pcie {
+			msi-parent = <&its_dsa 0x40b0c>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			num-pins = <3>;
+		};
+
 	};
 
 	mbigen_dsa@c0080000 {
@@ -317,6 +325,13 @@
 			#interrupt-cells = <2>;
 			num-pins = <128>;
 		};
+
+		mbigen_smmu_dsa_intc: intc_smmu_dsa {
+			msi-parent = <&its_dsa 0x40b20>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			num-pins = <3>;
+		};
 	};
 
 	/**
@@ -344,6 +359,20 @@
 		status = "disabled";
 	};
 
+        smmu1: smmu_dsa {
+                compatible = "arm,smmu-v3";
+                reg = <0x0 0xc0040000 0x0 0x20000>;
+                interrupt-parent  = <&mbigen_smmu_dsa_intc>;
+		interrupts = <733 1>,
+				<734 1>,
+				<735 1>;
+                interrupt-names = "eventq", "gerror", "priq";
+                #iommu-cells = <1>;
+                dma-coherent;
+                smmu-cb-memtype = <0x0 0x1>;
+                hisilicon,broken-prefetch-cmd;
+        };
+
 	soc {
 		compatible = "simple-bus";
 		#address-cells = <2>;
@@ -448,6 +477,7 @@
 			reg-names = "ppe-base", "dsaf-base";
 			interrupt-parent = <&mbigen_dsaf0>;
 			subctrl-syscon = <&dsa_subctrl>;
+			iommus = <&smmu1 0x0>;
 			reset-field-offset = <0>;
 			interrupts =
 			<576 1>, <577 1>, <578 1>, <579 1>, <580 1>,