diff --git a/arch/arm64/include/asm/cache.h b/arch/arm64/include/asm/cache.h
index 1c1485f669ea65570c8099558f6af5cafb924da2..d1c46d75885fa9c6d4249329a7425f745cd7db65 100644
--- a/arch/arm64/include/asm/cache.h
+++ b/arch/arm64/include/asm/cache.h
@@ -108,6 +108,15 @@ int cache_line_size(void);
 static inline u32 __attribute_const__ read_cpuid_effective_cachetype(void)
 {
 	u32 ctr = read_cpuid_cachetype();
+#ifdef CONFIG_HISILICON_ERRATUM_1980005
+	static const struct midr_range idc_support_list[] = {
+		MIDR_ALL_VERSIONS(MIDR_HISI_TSV110),
+		MIDR_REV(MIDR_HISI_TSV200, 1, 0),
+		{ /* sentinel */ }
+	};
+	if (is_midr_in_range_list(read_cpuid_id(), idc_support_list))
+		ctr |= BIT(CTR_IDC_SHIFT);
+#endif
 
 	if (!(ctr & BIT(CTR_IDC_SHIFT))) {
 		u64 clidr = read_sysreg(clidr_el1);
diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
index 8dbe94b4ec81ef13ce7dcaa64eed4d722d3542f5..a6f2451b446906b617a67b1180bf07822c91d9fb 100644
--- a/arch/arm64/kernel/cpu_errata.c
+++ b/arch/arm64/kernel/cpu_errata.c
@@ -90,6 +90,7 @@ hisilicon_1980005_enable(const struct arm64_cpu_capabilities *__unused)
 {
 	cpus_set_cap(ARM64_HAS_CACHE_IDC);
 	arm64_ftr_reg_ctrel0.sys_val |= BIT(CTR_IDC_SHIFT);
+	arm64_ftr_reg_ctrel0.strict_mask &= ~BIT(CTR_IDC_SHIFT);
 	sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0);
 }
 #endif