From 0873f54eb7b57dc857239b0ad95e6a9cc4c714b7 Mon Sep 17 00:00:00 2001 From: Luo Jiaxing Date: Fri, 17 May 2019 15:22:19 +0800 Subject: [PATCH] scsi: hisi_sas: ignore the error code between phy down to phy up driver inclusion category: bugfix bugzilla: NA CVE: NA Several error code will generate between phy down to phy up. This issue was instroduced by SoC design, So SoC guys come to a conclusion that we should ignore these several error code. (number of error code is usually under three). Signed-off-by: Jiaxing Luo Signed-off-by: John Garry Feature or Bugfix:Bugfix Signed-off-by: luojiaxing Reviewed-by: chenxiang Reviewed-by: Yang Yingliang Signed-off-by: Yang Yingliang --- drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c index bd7ea13dc585..d4ea33ecad23 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c +++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c @@ -970,8 +970,14 @@ static void enable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no) static void disable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no) { u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG); + u32 irq_msk = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2_MSK); + static const u32 msk = BIT(CHL_INT2_RX_DISP_ERR_OFF) | + BIT(CHL_INT2_RX_CODE_ERR_OFF) | + BIT(CHL_INT2_RX_INVLD_DW_OFF); u32 state; + hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2_MSK, msk | irq_msk); + cfg &= ~PHY_CFG_ENA_MSK; hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); @@ -983,6 +989,20 @@ static void disable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no) cfg |= PHY_CFG_PHY_RST_MSK; hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); } + + /* + * Wait 1us till all misleading error code to have occured + */ + udelay(1); + + hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_INVLD_DW); + hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DISP_ERR); + hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_CODE_ERR); + + hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2, msk); + + irq_msk = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2_MSK); + hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2_MSK, (~msk) & irq_msk); } static void start_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no) -- GitLab