drm/msm/dpu: adjust display_v_end for eDP and DP

stable inclusion
from stable-v5.10.121
commit 328cfeac735c02e7b0a346eb885e3bfad2b973dd
category: bugfix
bugzilla: https://gitee.com/openeuler/kernel/issues/I5L6CQ

Reference: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=328cfeac735c02e7b0a346eb885e3bfad2b973dd

--------------------------------

[ Upstream commit e18aeea7 ]

The “DP timing” requires the active region to be defined in the
bottom-right corner of the frame dimensions which is different
with DSI. Therefore both display_h_end and display_v_end need
to be adjusted accordingly. However current implementation has
only display_h_end adjusted.
Signed-off-by: NKuogee Hsieh <quic_khsieh@quicinc.com>

Fixes: fc3a69ec ("drm/msm/dpu: intf timing path for displayport")
Reviewed-by: NDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: NStephen Boyd <swboyd@chromium.org>
Patchwork: https://patchwork.freedesktop.org/patch/476277/
Link: https://lore.kernel.org/r/1645824192-29670-2-git-send-email-quic_khsieh@quicinc.comSigned-off-by: NDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: NSasha Levin <sashal@kernel.org>
Signed-off-by: NZheng Zengkai <zhengzengkai@huawei.com>
Acked-by: NXie XiuQi <xiexiuqi@huawei.com>

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c

@@ -146,6 +146,7 @@ static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *ctx,
 		active_v_end = active_v_start + (p->yres * hsync_period) - 1;
 
 		display_v_start += p->hsync_pulse_width + p->h_back_porch;
+		display_v_end   -= p->h_front_porch; 
 
 		active_hctl = (active_h_end << 16) | active_h_start;
 		display_hctl = active_hctl;