• B
    drm/i915: Stop using AGP layer for GEN6+ · e76e9aeb
    Ben Widawsky 提交于
    As a quick hack we make the old intel_gtt structure mutable so we can
    fool a bunch of the existing code which depends on elements in that data
    structure. We can/should try to remove this in a subsequent patch.
    
    This should preserve the old gtt init behavior which upon writing these
    patches seems incorrect. The next patch will fix these things.
    
    The one exception is VLV which doesn't have the preserved flush control
    write behavior. Since we want to do that for all GEN6+ stuff, we'll
    handle that in a later patch. Mainstream VLV support doesn't actually
    exist yet anyway.
    
    v2: Update the comment to remove the "voodoo"
    Check that the last pte written matches what we readback
    
    v3: actually kill cache_level_to_agp_type since most of the flags will
    disappear in an upcoming patch
    
    v4: v3 was actually not what we wanted (Daniel)
    Make the ggtt bind assertions better and stricter (Chris)
    Fix some uncaught errors at gtt init (Chris)
    Some other random stuff that Chris wanted
    
    v5: check for i==0 in gen6_ggtt_bind_object to shut up gcc (Ben)
    Signed-off-by: NBen Widawsky <ben@bwidawsk.net>
    Reviewed-by [v4]: Chris Wilson <chris@chris-wilson.co.uk>
    [danvet: Make the cache_level -> agp_flags conversion for pre-gen6 a
    tad more robust by mapping everything != CACHE_NONE to the cached agp
    flag - we have a 1:1 uncached mapping, but different modes of
    cacheable (at least on later generations). Suggested by Chris Wilson.]
    Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
    e76e9aeb
i915_dma.c 50.7 KB