The configurable hdmi_ref output of the PLL block is derived from
the tvdpll_594m clock signal via a configurable PLL post-divider.
It is used as the PLL reference input to the HDMI PHY module.
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>
Acked-by: NJames Liao <jamesjj.liao@mediatek.com>
Acked-by: NStephen Boyd <sboyd@codeaurora.org>