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    SPEAr: clk: Add Fractional Synthesizer clock · 270b9f42
    Viresh Kumar 提交于
    All SPEAr SoC's contain Fractional Synthesizers. Their Fout is derived from
    following equations:
    
    Fout = Fin / (2 * div) (division factor)
    div is 17 bits:-
         0-13 (fractional part)
         14-16 (integer part)
         div is (16-14 bits).(13-0 bits) (in binary)
    
         Fout = Fin/(2 * div)
         Fout = ((Fin / 10000)/(2 * div)) * 10000
         Fout = (2^14 * (Fin / 10000)/(2^14 * (2 * div))) * 10000
         Fout = (((Fin / 10000) << 14)/(2 * (div << 14))) * 10000
    
    div << 14 is simply 17 bit value written at register.
    
    This patch adds in support for this type of clock.
    Signed-off-by: NViresh Kumar <viresh.kumar@st.com>
    Reviewed-by: NMike Turquette <mturquette@linaro.org>
    270b9f42
clk-frac-synth.c 3.8 KB