mainline inclusion
from mainline-5.2
commit 761fdd5e
category: x86/cpu
bugzilla: https://bugzilla.openeuler.org/show_bug.cgi?id=19
CVE: NA

----------------------------------------------------------------

Add x86 architecture support for new Zhaoxin processors.
Carve out initialization code needed by Zhaoxin processors into
a separate compilation unit.

To identify Zhaoxin CPU, add a new vendor type X86_VENDOR_ZHAOXIN
for system recognition.
Signed-off-by: NTony W Wang-oc <TonyWWang-oc@zhaoxin.com>
Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
Cc: "hpa@zytor.com" <hpa@zytor.com>
Cc: "gregkh@linuxfoundation.org" <gregkh@linuxfoundation.org>
Cc: "rjw@rjwysocki.net" <rjw@rjwysocki.net>
Cc: "lenb@kernel.org" <lenb@kernel.org>
Cc: David Wang <DavidWang@zhaoxin.com>
Cc: "Cooper Yan(BJ-RD)" <CooperYan@zhaoxin.com>
Cc: "Qiyuan Wang(BJ-RD)" <QiyuanWang@zhaoxin.com>
Cc: "Herry Yang(BJ-RD)" <HerryYang@zhaoxin.com>
Link: https://lkml.kernel.org/r/01042674b2f741b2aed1f797359bdffb@zhaoxin.comSigned-off-by: NLeoLiu-oc <LeoLiu-oc@zhaoxin.com>
Reviewed-by: NHanjun Guo <guohanjun@huawei.com>
Reviewed-by: NLeoLiu-oc <LeoLiu-oc@zhaoxin.com>
Signed-off-by: NCheng Jian <cj.chengjian@huawei.com>