i915_drv.h 41.9 KB
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/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
 */
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/*
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 *
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 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
 * All Rights Reserved.
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 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sub license, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
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 */
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#ifndef _I915_DRV_H_
#define _I915_DRV_H_

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#include "i915_reg.h"
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#include "intel_bios.h"
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#include "intel_ringbuffer.h"
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#include <linux/io-mapping.h>
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#include <linux/i2c.h>
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#include <drm/intel-gtt.h>
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/* General customization:
 */

#define DRIVER_AUTHOR		"Tungsten Graphics, Inc."

#define DRIVER_NAME		"i915"
#define DRIVER_DESC		"Intel Graphics"
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#define DRIVER_DATE		"20080730"
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enum pipe {
	PIPE_A = 0,
	PIPE_B,
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	PIPE_C,
	I915_MAX_PIPES
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};
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#define pipe_name(p) ((p) + 'A')
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enum plane {
	PLANE_A = 0,
	PLANE_B,
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	PLANE_C,
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};
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#define plane_name(p) ((p) + 'A')
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#define I915_GEM_GPU_DOMAINS	(~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))

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#define for_each_pipe(p) for ((p) = 0; (p) < dev_priv->num_pipe; (p)++)

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/* Interface history:
 *
 * 1.1: Original.
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 * 1.2: Add Power Management
 * 1.3: Add vblank support
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 * 1.4: Fix cmdbuffer path, add heap destroy
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 * 1.5: Add vblank pipe configuration
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 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
 *      - Support vertical blank on secondary display pipe
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 */
#define DRIVER_MAJOR		1
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#define DRIVER_MINOR		6
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#define DRIVER_PATCHLEVEL	0

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#define WATCH_COHERENCY	0
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#define WATCH_LISTS	0
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#define I915_GEM_PHYS_CURSOR_0 1
#define I915_GEM_PHYS_CURSOR_1 2
#define I915_GEM_PHYS_OVERLAY_REGS 3
#define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)

struct drm_i915_gem_phys_object {
	int id;
	struct page **page_list;
	drm_dma_handle_t *handle;
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	struct drm_i915_gem_object *cur_obj;
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};

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struct mem_block {
	struct mem_block *next;
	struct mem_block *prev;
	int start;
	int size;
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	struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
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};

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struct opregion_header;
struct opregion_acpi;
struct opregion_swsci;
struct opregion_asle;

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struct intel_opregion {
	struct opregion_header *header;
	struct opregion_acpi *acpi;
	struct opregion_swsci *swsci;
	struct opregion_asle *asle;
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	void *vbt;
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	u32 __iomem *lid_state;
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};
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#define OPREGION_SIZE            (8*1024)
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struct intel_overlay;
struct intel_overlay_error_state;

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struct drm_i915_master_private {
	drm_local_map_t *sarea;
	struct _drm_i915_sarea *sarea_priv;
};
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#define I915_FENCE_REG_NONE -1

struct drm_i915_fence_reg {
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	struct list_head lru_list;
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	struct drm_i915_gem_object *obj;
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	uint32_t setup_seqno;
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};
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struct sdvo_device_mapping {
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	u8 initialized;
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	u8 dvo_port;
	u8 slave_addr;
	u8 dvo_wiring;
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	u8 i2c_pin;
	u8 i2c_speed;
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	u8 ddc_pin;
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};

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struct intel_display_error_state;

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struct drm_i915_error_state {
	u32 eir;
	u32 pgtbl_er;
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	u32 pipestat[I915_MAX_PIPES];
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	u32 ipeir;
	u32 ipehr;
	u32 instdone;
	u32 acthd;
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	u32 error; /* gen6+ */
	u32 bcs_acthd; /* gen6+ blt engine */
	u32 bcs_ipehr;
	u32 bcs_ipeir;
	u32 bcs_instdone;
	u32 bcs_seqno;
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	u32 vcs_acthd; /* gen6+ bsd engine */
	u32 vcs_ipehr;
	u32 vcs_ipeir;
	u32 vcs_instdone;
	u32 vcs_seqno;
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	u32 instpm;
	u32 instps;
	u32 instdone1;
	u32 seqno;
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	u64 bbaddr;
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	u64 fence[16];
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	struct timeval time;
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	struct drm_i915_error_object {
		int page_count;
		u32 gtt_offset;
		u32 *pages[0];
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	} *ringbuffer[I915_NUM_RINGS], *batchbuffer[I915_NUM_RINGS];
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	struct drm_i915_error_buffer {
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		u32 size;
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		u32 name;
		u32 seqno;
		u32 gtt_offset;
		u32 read_domains;
		u32 write_domain;
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		s32 fence_reg:5;
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		s32 pinned:2;
		u32 tiling:2;
		u32 dirty:1;
		u32 purgeable:1;
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		u32 ring:4;
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		u32 cache_level:2;
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	} *active_bo, *pinned_bo;
	u32 active_bo_count, pinned_bo_count;
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	struct intel_overlay_error_state *overlay;
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	struct intel_display_error_state *display;
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};

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struct drm_i915_display_funcs {
	void (*dpms)(struct drm_crtc *crtc, int mode);
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	bool (*fbc_enabled)(struct drm_device *dev);
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	void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval);
	void (*disable_fbc)(struct drm_device *dev);
	int (*get_display_clock_speed)(struct drm_device *dev);
	int (*get_fifo_size)(struct drm_device *dev, int plane);
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	void (*update_wm)(struct drm_device *dev);
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	int (*crtc_mode_set)(struct drm_crtc *crtc,
			     struct drm_display_mode *mode,
			     struct drm_display_mode *adjusted_mode,
			     int x, int y,
			     struct drm_framebuffer *old_fb);
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	void (*fdi_link_train)(struct drm_crtc *crtc);
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	void (*init_clock_gating)(struct drm_device *dev);
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	void (*init_pch_clock_gating)(struct drm_device *dev);
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	int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
			  struct drm_framebuffer *fb,
			  struct drm_i915_gem_object *obj);
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	int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb,
			    int x, int y);
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	/* clock updates for mode set */
	/* cursor updates */
	/* render clock increase/decrease */
	/* display clock increase/decrease */
	/* pll clock increase/decrease */
};

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struct intel_device_info {
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	u8 gen;
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	u8 is_mobile : 1;
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	u8 is_i85x : 1;
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	u8 is_i915g : 1;
	u8 is_i945gm : 1;
	u8 is_g33 : 1;
	u8 need_gfx_hws : 1;
	u8 is_g4x : 1;
	u8 is_pineview : 1;
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	u8 is_broadwater : 1;
	u8 is_crestline : 1;
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	u8 is_ivybridge : 1;
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	u8 has_fbc : 1;
	u8 has_pipe_cxsr : 1;
	u8 has_hotplug : 1;
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	u8 cursor_needs_physical : 1;
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	u8 has_overlay : 1;
	u8 overlay_needs_physical : 1;
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	u8 supports_tv : 1;
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	u8 has_bsd_ring : 1;
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	u8 has_blt_ring : 1;
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};

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enum no_fbc_reason {
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	FBC_NO_OUTPUT, /* no outputs enabled to compress */
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	FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */
	FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
	FBC_MODE_TOO_LARGE, /* mode too large for compression */
	FBC_BAD_PLANE, /* fbc not supported on plane */
	FBC_NOT_TILED, /* buffer not tiled */
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	FBC_MULTIPLE_PIPES, /* more than one pipe active */
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	FBC_MODULE_PARAM,
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};

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enum intel_pch {
	PCH_IBX,	/* Ibexpeak PCH */
	PCH_CPT,	/* Cougarpoint PCH */
};

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#define QUIRK_PIPEA_FORCE (1<<0)

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struct intel_fbdev;
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typedef struct drm_i915_private {
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	struct drm_device *dev;

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	const struct intel_device_info *info;

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	int has_gem;
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	int relative_constants_mode;
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	void __iomem *regs;
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	struct intel_gmbus {
		struct i2c_adapter adapter;
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		struct i2c_adapter *force_bit;
		u32 reg0;
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	} *gmbus;

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	struct pci_dev *bridge_dev;
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	struct intel_ring_buffer ring[I915_NUM_RINGS];
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	uint32_t next_seqno;
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	drm_dma_handle_t *status_page_dmah;
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	uint32_t counter;
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	drm_local_map_t hws_map;
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	struct drm_i915_gem_object *pwrctx;
	struct drm_i915_gem_object *renderctx;
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	struct resource mch_res;

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	unsigned int cpp;
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	int back_offset;
	int front_offset;
	int current_page;
	int page_flipping;

	atomic_t irq_received;
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	/* protects the irq masks */
	spinlock_t irq_lock;
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	/** Cached value of IMR to avoid reads in updating the bitfield */
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	u32 pipestat[2];
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	u32 irq_mask;
	u32 gt_irq_mask;
	u32 pch_irq_mask;
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	u32 hotplug_supported_mask;
	struct work_struct hotplug_work;

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	int tex_lru_log_granularity;
	int allow_batchbuffer;
	struct mem_block *agp_heap;
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	unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
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	int vblank_pipe;
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	int num_pipe;
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	/* For hangcheck timer */
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#define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
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	struct timer_list hangcheck_timer;
	int hangcheck_count;
	uint32_t last_acthd;
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	uint32_t last_instdone;
	uint32_t last_instdone1;
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	unsigned long cfb_size;
	unsigned long cfb_pitch;
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	unsigned long cfb_offset;
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	int cfb_fence;
	int cfb_plane;
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	int cfb_y;
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	struct intel_opregion opregion;

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	/* overlay */
	struct intel_overlay *overlay;

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	/* LVDS info */
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	int backlight_level;  /* restore backlight to this value */
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	bool backlight_enabled;
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	struct drm_display_mode *panel_fixed_mode;
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	struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
	struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
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	/* Feature bits from the VBIOS */
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	unsigned int int_tv_support:1;
	unsigned int lvds_dither:1;
	unsigned int lvds_vbt:1;
	unsigned int int_crt_support:1;
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	unsigned int lvds_use_ssc:1;
	int lvds_ssc_freq;
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	struct {
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		int rate;
		int lanes;
		int preemphasis;
		int vswing;

		bool initialized;
		bool support;
		int bpp;
		struct edp_power_seq pps;
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	} edp;
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	bool no_aux_handshake;
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	struct notifier_block lid_notifier;

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	int crt_ddc_pin;
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	struct drm_i915_fence_reg fence_regs[16]; /* assume 965 */
	int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
	int num_fence_regs; /* 8 on pre-965, 16 otherwise */

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	unsigned int fsb_freq, mem_freq, is_ddr3;
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	spinlock_t error_lock;
	struct drm_i915_error_state *first_error;
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	struct work_struct error_work;
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	struct completion error_completion;
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	struct workqueue_struct *wq;
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	/* Display functions */
	struct drm_i915_display_funcs display;

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	/* PCH chipset type */
	enum intel_pch pch_type;

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	unsigned long quirks;

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	/* Register state */
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	bool modeset_on_lid;
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	u8 saveLBB;
	u32 saveDSPACNTR;
	u32 saveDSPBCNTR;
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	u32 saveDSPARB;
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	u32 saveHWS;
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	u32 savePIPEACONF;
	u32 savePIPEBCONF;
	u32 savePIPEASRC;
	u32 savePIPEBSRC;
	u32 saveFPA0;
	u32 saveFPA1;
	u32 saveDPLL_A;
	u32 saveDPLL_A_MD;
	u32 saveHTOTAL_A;
	u32 saveHBLANK_A;
	u32 saveHSYNC_A;
	u32 saveVTOTAL_A;
	u32 saveVBLANK_A;
	u32 saveVSYNC_A;
	u32 saveBCLRPAT_A;
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	u32 saveTRANSACONF;
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	u32 saveTRANS_HTOTAL_A;
	u32 saveTRANS_HBLANK_A;
	u32 saveTRANS_HSYNC_A;
	u32 saveTRANS_VTOTAL_A;
	u32 saveTRANS_VBLANK_A;
	u32 saveTRANS_VSYNC_A;
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	u32 savePIPEASTAT;
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	u32 saveDSPASTRIDE;
	u32 saveDSPASIZE;
	u32 saveDSPAPOS;
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	u32 saveDSPAADDR;
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	u32 saveDSPASURF;
	u32 saveDSPATILEOFF;
	u32 savePFIT_PGM_RATIOS;
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	u32 saveBLC_HIST_CTL;
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	u32 saveBLC_PWM_CTL;
	u32 saveBLC_PWM_CTL2;
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	u32 saveBLC_CPU_PWM_CTL;
	u32 saveBLC_CPU_PWM_CTL2;
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	u32 saveFPB0;
	u32 saveFPB1;
	u32 saveDPLL_B;
	u32 saveDPLL_B_MD;
	u32 saveHTOTAL_B;
	u32 saveHBLANK_B;
	u32 saveHSYNC_B;
	u32 saveVTOTAL_B;
	u32 saveVBLANK_B;
	u32 saveVSYNC_B;
	u32 saveBCLRPAT_B;
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	u32 saveTRANSBCONF;
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	u32 saveTRANS_HTOTAL_B;
	u32 saveTRANS_HBLANK_B;
	u32 saveTRANS_HSYNC_B;
	u32 saveTRANS_VTOTAL_B;
	u32 saveTRANS_VBLANK_B;
	u32 saveTRANS_VSYNC_B;
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	u32 savePIPEBSTAT;
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	u32 saveDSPBSTRIDE;
	u32 saveDSPBSIZE;
	u32 saveDSPBPOS;
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	u32 saveDSPBADDR;
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	u32 saveDSPBSURF;
	u32 saveDSPBTILEOFF;
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	u32 saveVGA0;
	u32 saveVGA1;
	u32 saveVGA_PD;
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	u32 saveVGACNTRL;
	u32 saveADPA;
	u32 saveLVDS;
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	u32 savePP_ON_DELAYS;
	u32 savePP_OFF_DELAYS;
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	u32 saveDVOA;
	u32 saveDVOB;
	u32 saveDVOC;
	u32 savePP_ON;
	u32 savePP_OFF;
	u32 savePP_CONTROL;
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	u32 savePP_DIVISOR;
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	u32 savePFIT_CONTROL;
	u32 save_palette_a[256];
	u32 save_palette_b[256];
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	u32 saveDPFC_CB_BASE;
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	u32 saveFBC_CFB_BASE;
	u32 saveFBC_LL_BASE;
	u32 saveFBC_CONTROL;
	u32 saveFBC_CONTROL2;
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	u32 saveIER;
	u32 saveIIR;
	u32 saveIMR;
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	u32 saveDEIER;
	u32 saveDEIMR;
	u32 saveGTIER;
	u32 saveGTIMR;
	u32 saveFDI_RXA_IMR;
	u32 saveFDI_RXB_IMR;
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	u32 saveCACHE_MODE_0;
	u32 saveMI_ARB_STATE;
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	u32 saveSWF0[16];
	u32 saveSWF1[16];
	u32 saveSWF2[3];
	u8 saveMSR;
	u8 saveSR[8];
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	u8 saveGR[25];
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	u8 saveAR_INDEX;
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	u8 saveAR[21];
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	u8 saveDACMASK;
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	u8 saveCR[37];
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	uint64_t saveFENCE[16];
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	u32 saveCURACNTR;
	u32 saveCURAPOS;
	u32 saveCURABASE;
	u32 saveCURBCNTR;
	u32 saveCURBPOS;
	u32 saveCURBBASE;
	u32 saveCURSIZE;
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	u32 saveDP_B;
	u32 saveDP_C;
	u32 saveDP_D;
	u32 savePIPEA_GMCH_DATA_M;
	u32 savePIPEB_GMCH_DATA_M;
	u32 savePIPEA_GMCH_DATA_N;
	u32 savePIPEB_GMCH_DATA_N;
	u32 savePIPEA_DP_LINK_M;
	u32 savePIPEB_DP_LINK_M;
	u32 savePIPEA_DP_LINK_N;
	u32 savePIPEB_DP_LINK_N;
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	u32 saveFDI_RXA_CTL;
	u32 saveFDI_TXA_CTL;
	u32 saveFDI_RXB_CTL;
	u32 saveFDI_TXB_CTL;
	u32 savePFA_CTL_1;
	u32 savePFB_CTL_1;
	u32 savePFA_WIN_SZ;
	u32 savePFB_WIN_SZ;
	u32 savePFA_WIN_POS;
	u32 savePFB_WIN_POS;
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	u32 savePCH_DREF_CONTROL;
	u32 saveDISP_ARB_CTL;
	u32 savePIPEA_DATA_M1;
	u32 savePIPEA_DATA_N1;
	u32 savePIPEA_LINK_M1;
	u32 savePIPEA_LINK_N1;
	u32 savePIPEB_DATA_M1;
	u32 savePIPEB_DATA_N1;
	u32 savePIPEB_LINK_M1;
	u32 savePIPEB_LINK_N1;
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	u32 saveMCHBAR_RENDER_STANDBY;
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	struct {
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		/** Bridge to intel-gtt-ko */
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		const struct intel_gtt *gtt;
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		/** Memory allocator for GTT stolen memory */
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		struct drm_mm stolen;
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		/** Memory allocator for GTT */
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		struct drm_mm gtt_space;
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		/** List of all objects in gtt_space. Used to restore gtt
		 * mappings on resume */
		struct list_head gtt_list;
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		/** Usable portion of the GTT for GEM */
		unsigned long gtt_start;
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		unsigned long gtt_mappable_end;
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		unsigned long gtt_end;
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		struct io_mapping *gtt_mapping;
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		int gtt_mtrr;
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		struct shrinker inactive_shrinker;
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		/**
		 * List of objects currently involved in rendering.
		 *
		 * Includes buffers having the contents of their GPU caches
		 * flushed, not necessarily primitives.  last_rendering_seqno
		 * represents when the rendering involved will be completed.
		 *
		 * A reference is held on the buffer while on this list.
		 */
		struct list_head active_list;

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		/**
		 * List of objects which are not in the ringbuffer but which
		 * still have a write_domain which needs to be flushed before
		 * unbinding.
		 *
583 584
		 * last_rendering_seqno is 0 while an object is in this list.
		 *
585 586 587 588 589 590 591 592
		 * A reference is held on the buffer while on this list.
		 */
		struct list_head flushing_list;

		/**
		 * LRU list of objects which are not in the ringbuffer and
		 * are ready to unbind, but are still in the GTT.
		 *
593 594
		 * last_rendering_seqno is 0 while an object is in this list.
		 *
595 596 597 598 599 600
		 * A reference is not held on the buffer while on this list,
		 * as merely being GTT-bound shouldn't prevent its being
		 * freed, and we'll pull it off the list in the free path.
		 */
		struct list_head inactive_list;

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		/**
		 * LRU list of objects which are not in the ringbuffer but
		 * are still pinned in the GTT.
		 */
		struct list_head pinned_list;

607 608 609
		/** LRU list of objects with fence regs on them. */
		struct list_head fence_list;

610 611 612 613 614 615 616 617
		/**
		 * List of objects currently pending being freed.
		 *
		 * These objects are no longer in use, but due to a signal
		 * we were prevented from freeing them at the appointed time.
		 */
		struct list_head deferred_free_list;

618 619 620 621 622 623 624 625 626
		/**
		 * We leave the user IRQ off as much as possible,
		 * but this means that requests will finish and never
		 * be retired once the system goes idle. Set a timer to
		 * fire periodically while the ring is running. When it
		 * fires, go retire requests.
		 */
		struct delayed_work retire_work;

627 628 629 630 631 632
		/**
		 * Are we in a non-interruptible section of code like
		 * modesetting?
		 */
		bool interruptible;

633 634 635 636 637 638 639 640 641 642 643 644 645 646
		/**
		 * Flag if the X Server, and thus DRM, is not currently in
		 * control of the device.
		 *
		 * This is set between LeaveVT and EnterVT.  It needs to be
		 * replaced with a semaphore.  It also needs to be
		 * transitioned away from for kernel modesetting.
		 */
		int suspended;

		/**
		 * Flag if the hardware appears to be wedged.
		 *
		 * This is set when attempts to idle the device timeout.
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		 * It prevents command submission from occurring and makes
648 649
		 * every pending request fail
		 */
650
		atomic_t wedged;
651 652 653 654 655

		/** Bit 6 swizzling required for X tiling */
		uint32_t bit_6_swizzle_x;
		/** Bit 6 swizzling required for Y tiling */
		uint32_t bit_6_swizzle_y;
656 657 658

		/* storage for physical objects */
		struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
659

660 661
		/* accounting, useful for userland debugging */
		size_t gtt_total;
662 663
		size_t mappable_gtt_total;
		size_t object_memory;
664
		u32 object_count;
665
	} mm;
666
	struct sdvo_device_mapping sdvo_mappings[2];
667 668
	/* indicate whether the LVDS_BORDER should be enabled or not */
	unsigned int lvds_border_bits;
669 670
	/* Panel fitter placement and size for Ironlake+ */
	u32 pch_pf_pos, pch_pf_size;
671
	int panel_t3, panel_t12;
672

673 674 675
	struct drm_crtc *plane_to_crtc_mapping[2];
	struct drm_crtc *pipe_to_crtc_mapping[2];
	wait_queue_head_t pending_flip_queue;
676
	bool flip_pending_is_done;
677

678 679 680
	/* Reclocking support */
	bool render_reclock_avail;
	bool lvds_downclock_avail;
681 682
	/* indicates the reduced downclock for LVDS*/
	int lvds_downclock;
683 684 685 686
	struct work_struct idle_work;
	struct timer_list idle_timer;
	bool busy;
	u16 orig_clock;
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Zhao Yakui 已提交
687 688
	int child_dev_num;
	struct child_device_config *child_dev;
689
	struct drm_connector *int_lvds_connector;
690

691
	bool mchbar_need_disable;
692

693 694 695 696
	struct work_struct rps_work;
	spinlock_t rps_lock;
	u32 pm_iir;

697 698 699
	u8 cur_delay;
	u8 min_delay;
	u8 max_delay;
700 701 702
	u8 fmax;
	u8 fstart;

703 704 705 706 707 708 709 710
	u64 last_count1;
	unsigned long last_time1;
	u64 last_count2;
	struct timespec last_time2;
	unsigned long gfx_power;
	int c_m;
	int r_t;
	u8 corr;
711
	spinlock_t *mchdev_lock;
712 713

	enum no_fbc_reason no_fbc_reason;
714

715 716
	struct drm_mm_node *compressed_fb;
	struct drm_mm_node *compressed_llb;
717

718 719
	unsigned long last_gpu_reset;

720 721
	/* list of fbdev register on this device */
	struct intel_fbdev *fbdev;
722 723

	struct drm_property *broadcast_rgb_property;
724
	struct drm_property *force_audio_property;
725 726

	atomic_t forcewake_count;
L
Linus Torvalds 已提交
727 728
} drm_i915_private_t;

729 730 731 732 733 734
enum i915_cache_level {
	I915_CACHE_NONE,
	I915_CACHE_LLC,
	I915_CACHE_LLC_MLC, /* gen6+ */
};

735
struct drm_i915_gem_object {
736
	struct drm_gem_object base;
737 738 739

	/** Current space allocated to this object in the GTT, if any. */
	struct drm_mm_node *gtt_space;
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Daniel Vetter 已提交
740
	struct list_head gtt_list;
741 742

	/** This object's place on the active/flushing/inactive lists */
743 744
	struct list_head ring_list;
	struct list_head mm_list;
745 746
	/** This object's place on GPU write list */
	struct list_head gpu_write_list;
747 748
	/** This object's place in the batchbuffer or on the eviction list */
	struct list_head exec_list;
749 750 751 752 753 754

	/**
	 * This is set if the object is on the active or flushing lists
	 * (has pending rendering), and is not set if it's on inactive (ready
	 * to be unbound).
	 */
755
	unsigned int active : 1;
756 757 758 759 760

	/**
	 * This is set if the object has been written to since last bound
	 * to the GTT
	 */
761 762
	unsigned int dirty : 1;

763 764 765 766 767 768
	/**
	 * This is set if the object has been written to since the last
	 * GPU flush.
	 */
	unsigned int pending_gpu_write : 1;

769 770 771 772 773 774 775
	/**
	 * Fence register bits (if any) for this object.  Will be set
	 * as needed when mapped into the GTT.
	 * Protected by dev->struct_mutex.
	 *
	 * Size: 4 bits for 16 fences + sign (for FENCE_REG_NONE)
	 */
776
	signed int fence_reg : 5;
777 778 779 780 781 782 783 784 785 786

	/**
	 * Advice: are the backing pages purgeable?
	 */
	unsigned int madv : 2;

	/**
	 * Current tiling mode for the object.
	 */
	unsigned int tiling_mode : 2;
787
	unsigned int tiling_changed : 1;
788 789 790 791 792 793 794 795 796 797

	/** How many users have pinned this object in GTT space. The following
	 * users can each hold at most one reference: pwrite/pread, pin_ioctl
	 * (via user_pin_count), execbuffer (objects are not allowed multiple
	 * times for the same batchbuffer), and the framebuffer code. When
	 * switching/pageflipping, the framebuffer code has at most two buffers
	 * pinned per crtc.
	 *
	 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
	 * bits with absolutely no headroom. So use 4 bits. */
798
	unsigned int pin_count : 4;
799
#define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
800

801 802 803 804 805 806
	/**
	 * Is the object at the current location in the gtt mappable and
	 * fenceable? Used to avoid costly recalculations.
	 */
	unsigned int map_and_fenceable : 1;

807 808 809 810 811 812 813 814
	/**
	 * Whether the current gtt mapping needs to be mappable (and isn't just
	 * mappable by accident). Track pin and fault separate for a more
	 * accurate mappable working set.
	 */
	unsigned int fault_mappable : 1;
	unsigned int pin_mappable : 1;

815 816 817 818 819 820
	/*
	 * Is the GPU currently using a fence to access this buffer,
	 */
	unsigned int pending_fenced_gpu_access:1;
	unsigned int fenced_gpu_access:1;

821 822
	unsigned int cache_level:2;

823
	struct page **pages;
824

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	/**
	 * DMAR support
	 */
	struct scatterlist *sg_list;
	int num_sg;

831 832 833 834 835
	/**
	 * Used for performing relocations during execbuffer insertion.
	 */
	struct hlist_node exec_node;
	unsigned long exec_handle;
836
	struct drm_i915_gem_exec_object2 *exec_entry;
837

838 839 840 841 842 843
	/**
	 * Current offset of the object in GTT space.
	 *
	 * This is the same as gtt_space->start
	 */
	uint32_t gtt_offset;
844

845 846
	/** Breadcrumb of last rendering to the buffer. */
	uint32_t last_rendering_seqno;
847 848 849 850 851
	struct intel_ring_buffer *ring;

	/** Breadcrumb of last fenced GPU access to the buffer. */
	uint32_t last_fenced_seqno;
	struct intel_ring_buffer *last_fenced_ring;
852

853
	/** Current tiling stride for the object, if it's tiled. */
854
	uint32_t stride;
855

856
	/** Record of address bit 17 of each page at last unbind. */
857
	unsigned long *bit_17;
858

859

860
	/**
861 862
	 * If present, while GEM_DOMAIN_CPU is in the read domain this array
	 * flags which individual pages are valid.
863 864
	 */
	uint8_t *page_cpu_valid;
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865 866 867 868

	/** User space pin count and filp owning the pin */
	uint32_t user_pin_count;
	struct drm_file *pin_filp;
869 870 871

	/** for phy allocated objects */
	struct drm_i915_gem_phys_object *phys_obj;
872

873 874 875 876 877 878
	/**
	 * Number of crtcs where this object is currently the fb, but
	 * will be page flipped away on the next vblank.  When it
	 * reaches 0, dev_priv->pending_flip_queue will be woken up.
	 */
	atomic_t pending_flip;
879 880
};

881
#define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
882

883 884 885 886 887 888 889 890 891 892 893
/**
 * Request queue structure.
 *
 * The request queue allows us to note sequence numbers that have been emitted
 * and may be associated with active buffers to be retired.
 *
 * By keeping this list, we can avoid having to do questionable
 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
 * an emission time with seqnos for tracking how far ahead of the GPU we are.
 */
struct drm_i915_gem_request {
894 895 896
	/** On Which ring this request was generated */
	struct intel_ring_buffer *ring;

897 898 899 900 901 902
	/** GEM sequence number associated with this request. */
	uint32_t seqno;

	/** Time at which this request was emitted, in jiffies. */
	unsigned long emitted_jiffies;

903
	/** global list entry for this request */
904
	struct list_head list;
905

906
	struct drm_i915_file_private *file_priv;
907 908
	/** file_priv list entry for this request */
	struct list_head client_list;
909 910 911 912
};

struct drm_i915_file_private {
	struct {
913
		struct spinlock lock;
914
		struct list_head request_list;
915 916 917
	} mm;
};

918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937
#define INTEL_INFO(dev)	(((struct drm_i915_private *) (dev)->dev_private)->info)

#define IS_I830(dev)		((dev)->pci_device == 0x3577)
#define IS_845G(dev)		((dev)->pci_device == 0x2562)
#define IS_I85X(dev)		(INTEL_INFO(dev)->is_i85x)
#define IS_I865G(dev)		((dev)->pci_device == 0x2572)
#define IS_I915G(dev)		(INTEL_INFO(dev)->is_i915g)
#define IS_I915GM(dev)		((dev)->pci_device == 0x2592)
#define IS_I945G(dev)		((dev)->pci_device == 0x2772)
#define IS_I945GM(dev)		(INTEL_INFO(dev)->is_i945gm)
#define IS_BROADWATER(dev)	(INTEL_INFO(dev)->is_broadwater)
#define IS_CRESTLINE(dev)	(INTEL_INFO(dev)->is_crestline)
#define IS_GM45(dev)		((dev)->pci_device == 0x2A42)
#define IS_G4X(dev)		(INTEL_INFO(dev)->is_g4x)
#define IS_PINEVIEW_G(dev)	((dev)->pci_device == 0xa001)
#define IS_PINEVIEW_M(dev)	((dev)->pci_device == 0xa011)
#define IS_PINEVIEW(dev)	(INTEL_INFO(dev)->is_pineview)
#define IS_G33(dev)		(INTEL_INFO(dev)->is_g33)
#define IS_IRONLAKE_D(dev)	((dev)->pci_device == 0x0042)
#define IS_IRONLAKE_M(dev)	((dev)->pci_device == 0x0046)
938
#define IS_IVYBRIDGE(dev)	(INTEL_INFO(dev)->is_ivybridge)
939 940
#define IS_MOBILE(dev)		(INTEL_INFO(dev)->is_mobile)

941 942 943 944 945 946
/*
 * The genX designation typically refers to the render engine, so render
 * capability related checks should use IS_GEN, while display and other checks
 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
 * chips, etc.).
 */
947 948 949 950 951
#define IS_GEN2(dev)	(INTEL_INFO(dev)->gen == 2)
#define IS_GEN3(dev)	(INTEL_INFO(dev)->gen == 3)
#define IS_GEN4(dev)	(INTEL_INFO(dev)->gen == 4)
#define IS_GEN5(dev)	(INTEL_INFO(dev)->gen == 5)
#define IS_GEN6(dev)	(INTEL_INFO(dev)->gen == 6)
952
#define IS_GEN7(dev)	(INTEL_INFO(dev)->gen == 7)
953 954 955 956 957

#define HAS_BSD(dev)            (INTEL_INFO(dev)->has_bsd_ring)
#define HAS_BLT(dev)            (INTEL_INFO(dev)->has_blt_ring)
#define I915_NEED_GFX_HWS(dev)	(INTEL_INFO(dev)->need_gfx_hws)

958
#define HAS_OVERLAY(dev)		(INTEL_INFO(dev)->has_overlay)
959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978
#define OVERLAY_NEEDS_PHYSICAL(dev)	(INTEL_INFO(dev)->overlay_needs_physical)

/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
 * rows, which changed the alignment requirements and fence programming.
 */
#define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
						      IS_I915GM(dev)))
#define SUPPORTS_DIGITAL_OUTPUTS(dev)	(!IS_GEN2(dev) && !IS_PINEVIEW(dev))
#define SUPPORTS_INTEGRATED_HDMI(dev)	(IS_G4X(dev) || IS_GEN5(dev))
#define SUPPORTS_INTEGRATED_DP(dev)	(IS_G4X(dev) || IS_GEN5(dev))
#define SUPPORTS_EDP(dev)		(IS_IRONLAKE_M(dev))
#define SUPPORTS_TV(dev)		(INTEL_INFO(dev)->supports_tv)
#define I915_HAS_HOTPLUG(dev)		 (INTEL_INFO(dev)->has_hotplug)
/* dsparb controlled by hw only */
#define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))

#define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
#define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
#define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)

979 980
#define HAS_PCH_SPLIT(dev) (IS_GEN5(dev) || IS_GEN6(dev) || IS_IVYBRIDGE(dev))
#define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5)
981 982 983 984 985

#define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
#define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
#define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)

986 987
#include "i915_trace.h"

988
extern struct drm_ioctl_desc i915_ioctls[];
989
extern int i915_max_ioctl;
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Jesse Barnes 已提交
990
extern unsigned int i915_fbpercrtc;
991
extern int i915_panel_ignore_lid;
992
extern unsigned int i915_powersave;
993
extern unsigned int i915_semaphores;
994
extern unsigned int i915_lvds_downclock;
995
extern unsigned int i915_panel_use_ssc;
996
extern int i915_vbt_sdvo_panel_type;
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Chris Wilson 已提交
997
extern unsigned int i915_enable_rc6;
998
extern unsigned int i915_enable_fbc;
999
extern bool i915_enable_hangcheck;
1000

1001 1002
extern int i915_suspend(struct drm_device *dev, pm_message_t state);
extern int i915_resume(struct drm_device *dev);
1003 1004 1005
extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);

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Linus Torvalds 已提交
1006
				/* i915_dma.c */
1007
extern void i915_kernel_lost_context(struct drm_device * dev);
1008
extern int i915_driver_load(struct drm_device *, unsigned long flags);
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Jesse Barnes 已提交
1009
extern int i915_driver_unload(struct drm_device *);
1010
extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
1011
extern void i915_driver_lastclose(struct drm_device * dev);
1012 1013
extern void i915_driver_preclose(struct drm_device *dev,
				 struct drm_file *file_priv);
1014 1015
extern void i915_driver_postclose(struct drm_device *dev,
				  struct drm_file *file_priv);
1016
extern int i915_driver_device_is_agp(struct drm_device * dev);
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Dave Airlie 已提交
1017 1018
extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
			      unsigned long arg);
1019
extern int i915_emit_box(struct drm_device *dev,
1020 1021
			 struct drm_clip_rect *box,
			 int DR1, int DR4);
1022
extern int i915_reset(struct drm_device *dev, u8 flags);
1023 1024 1025 1026 1027
extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);

1028

L
Linus Torvalds 已提交
1029
/* i915_irq.c */
B
Ben Gamari 已提交
1030
void i915_hangcheck_elapsed(unsigned long data);
1031
void i915_handle_error(struct drm_device *dev, bool wedged);
1032 1033 1034 1035
extern int i915_irq_emit(struct drm_device *dev, void *data,
			 struct drm_file *file_priv);
extern int i915_irq_wait(struct drm_device *dev, void *data,
			 struct drm_file *file_priv);
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Linus Torvalds 已提交
1036

1037
extern void intel_irq_init(struct drm_device *dev);
1038

1039 1040 1041 1042 1043 1044
extern int i915_vblank_pipe_set(struct drm_device *dev, void *data,
				struct drm_file *file_priv);
extern int i915_vblank_pipe_get(struct drm_device *dev, void *data,
				struct drm_file *file_priv);
extern int i915_vblank_swap(struct drm_device *dev, void *data,
			    struct drm_file *file_priv);
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Linus Torvalds 已提交
1045

1046 1047 1048 1049 1050 1051
void
i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);

void
i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);

1052 1053
void intel_enable_asle (struct drm_device *dev);

1054 1055 1056 1057 1058 1059
#ifdef CONFIG_DEBUG_FS
extern void i915_destroy_error_state(struct drm_device *dev);
#else
#define i915_destroy_error_state(x)
#endif

1060

L
Linus Torvalds 已提交
1061
/* i915_mem.c */
1062 1063 1064 1065 1066 1067 1068 1069
extern int i915_mem_alloc(struct drm_device *dev, void *data,
			  struct drm_file *file_priv);
extern int i915_mem_free(struct drm_device *dev, void *data,
			 struct drm_file *file_priv);
extern int i915_mem_init_heap(struct drm_device *dev, void *data,
			      struct drm_file *file_priv);
extern int i915_mem_destroy_heap(struct drm_device *dev, void *data,
				 struct drm_file *file_priv);
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Linus Torvalds 已提交
1070
extern void i915_mem_takedown(struct mem_block **heap);
1071
extern void i915_mem_release(struct drm_device * dev,
1072
			     struct drm_file *file_priv, struct mem_block *heap);
1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083
/* i915_gem.c */
int i915_gem_init_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
int i915_gem_create_ioctl(struct drm_device *dev, void *data,
			  struct drm_file *file_priv);
int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
			 struct drm_file *file_priv);
int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
			  struct drm_file *file_priv);
int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
1084 1085
int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
1086 1087 1088 1089 1090 1091
int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
			      struct drm_file *file_priv);
int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
			     struct drm_file *file_priv);
int i915_gem_execbuffer(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
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Jesse Barnes 已提交
1092 1093
int i915_gem_execbuffer2(struct drm_device *dev, void *data,
			 struct drm_file *file_priv);
1094 1095 1096 1097 1098 1099 1100 1101
int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
		       struct drm_file *file_priv);
int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
			 struct drm_file *file_priv);
int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
			    struct drm_file *file_priv);
1102 1103
int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
			   struct drm_file *file_priv);
1104 1105 1106 1107 1108 1109 1110 1111
int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
			   struct drm_file *file_priv);
int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
			   struct drm_file *file_priv);
int i915_gem_set_tiling(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
int i915_gem_get_tiling(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
1112 1113
int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
				struct drm_file *file_priv);
1114 1115
void i915_gem_load(struct drm_device *dev);
int i915_gem_init_object(struct drm_gem_object *obj);
C
Chris Wilson 已提交
1116
int __must_check i915_gem_flush_ring(struct intel_ring_buffer *ring,
1117 1118
				     uint32_t invalidate_domains,
				     uint32_t flush_domains);
1119 1120
struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
						  size_t size);
1121
void i915_gem_free_object(struct drm_gem_object *obj);
1122 1123 1124
int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj,
				     uint32_t alignment,
				     bool map_and_fenceable);
1125
void i915_gem_object_unpin(struct drm_i915_gem_object *obj);
1126
int __must_check i915_gem_object_unbind(struct drm_i915_gem_object *obj);
1127
void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
1128
void i915_gem_lastclose(struct drm_device *dev);
1129

1130
int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
1131
int __must_check i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj);
1132
void i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1133 1134
				    struct intel_ring_buffer *ring,
				    u32 seqno);
1135

1136 1137 1138 1139 1140 1141 1142
int i915_gem_dumb_create(struct drm_file *file_priv,
			 struct drm_device *dev,
			 struct drm_mode_create_dumb *args);
int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
		      uint32_t handle, uint64_t *offset);
int i915_gem_dumb_destroy(struct drm_file *file_priv, struct drm_device *dev,
			  uint32_t handle);			  
1143 1144 1145 1146 1147 1148 1149 1150 1151
/**
 * Returns true if seq1 is later than seq2.
 */
static inline bool
i915_seqno_passed(uint32_t seq1, uint32_t seq2)
{
	return (int32_t)(seq1 - seq2) >= 0;
}

1152
static inline u32
C
Chris Wilson 已提交
1153
i915_gem_next_request_seqno(struct intel_ring_buffer *ring)
1154
{
C
Chris Wilson 已提交
1155
	drm_i915_private_t *dev_priv = ring->dev->dev_private;
1156 1157 1158
	return ring->outstanding_lazy_request = dev_priv->next_seqno;
}

1159
int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj,
1160
					   struct intel_ring_buffer *pipelined);
1161
int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
1162

1163
void i915_gem_retire_requests(struct drm_device *dev);
1164
void i915_gem_reset(struct drm_device *dev);
1165
void i915_gem_clflush_object(struct drm_i915_gem_object *obj);
1166 1167 1168
int __must_check i915_gem_object_set_domain(struct drm_i915_gem_object *obj,
					    uint32_t read_domains,
					    uint32_t write_domain);
1169
int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj);
1170
int __must_check i915_gem_init_ringbuffer(struct drm_device *dev);
J
Jesse Barnes 已提交
1171
void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
1172 1173 1174 1175 1176 1177
void i915_gem_do_init(struct drm_device *dev,
		      unsigned long start,
		      unsigned long mappable_end,
		      unsigned long end);
int __must_check i915_gpu_idle(struct drm_device *dev);
int __must_check i915_gem_idle(struct drm_device *dev);
C
Chris Wilson 已提交
1178 1179 1180 1181
int __must_check i915_add_request(struct intel_ring_buffer *ring,
				  struct drm_file *file,
				  struct drm_i915_gem_request *request);
int __must_check i915_wait_request(struct intel_ring_buffer *ring,
1182
				   uint32_t seqno);
1183
int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
1184 1185 1186 1187
int __must_check
i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
				  bool write);
int __must_check
1188 1189
i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
				     u32 alignment,
1190
				     struct intel_ring_buffer *pipelined);
1191
int i915_gem_attach_phys_object(struct drm_device *dev,
1192
				struct drm_i915_gem_object *obj,
1193 1194
				int id,
				int align);
1195
void i915_gem_detach_phys_object(struct drm_device *dev,
1196
				 struct drm_i915_gem_object *obj);
1197
void i915_gem_free_all_phys_object(struct drm_device *dev);
1198
void i915_gem_release(struct drm_device *dev, struct drm_file *file);
1199

1200 1201 1202
uint32_t
i915_gem_get_unfenced_gtt_alignment(struct drm_i915_gem_object *obj);

1203 1204 1205
int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
				    enum i915_cache_level cache_level);

1206 1207
/* i915_gem_gtt.c */
void i915_gem_restore_gtt_mappings(struct drm_device *dev);
1208
int __must_check i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj);
1209 1210
void i915_gem_gtt_rebind_object(struct drm_i915_gem_object *obj,
				enum i915_cache_level cache_level);
1211
void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj);
1212

1213
/* i915_gem_evict.c */
1214 1215 1216 1217 1218 1219
int __must_check i915_gem_evict_something(struct drm_device *dev, int min_size,
					  unsigned alignment, bool mappable);
int __must_check i915_gem_evict_everything(struct drm_device *dev,
					   bool purgeable_only);
int __must_check i915_gem_evict_inactive(struct drm_device *dev,
					 bool purgeable_only);
1220

1221 1222
/* i915_gem_tiling.c */
void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
1223 1224
void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
1225 1226

/* i915_gem_debug.c */
1227
void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
1228
			  const char *where, uint32_t mark);
1229 1230
#if WATCH_LISTS
int i915_verify_lists(struct drm_device *dev);
1231
#else
1232
#define i915_verify_lists(dev) 0
1233
#endif
1234 1235 1236
void i915_gem_object_check_coherency(struct drm_i915_gem_object *obj,
				     int handle);
void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
1237
			  const char *where, uint32_t mark);
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Linus Torvalds 已提交
1238

1239
/* i915_debugfs.c */
1240 1241
int i915_debugfs_init(struct drm_minor *minor);
void i915_debugfs_cleanup(struct drm_minor *minor);
1242

1243 1244 1245
/* i915_suspend.c */
extern int i915_save_state(struct drm_device *dev);
extern int i915_restore_state(struct drm_device *dev);
1246 1247 1248 1249

/* i915_suspend.c */
extern int i915_save_state(struct drm_device *dev);
extern int i915_restore_state(struct drm_device *dev);
1250

1251 1252 1253
/* intel_i2c.c */
extern int intel_setup_gmbus(struct drm_device *dev);
extern void intel_teardown_gmbus(struct drm_device *dev);
C
Chris Wilson 已提交
1254 1255
extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
1256 1257 1258 1259
extern inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
{
	return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
}
1260 1261
extern void intel_i2c_reset(struct drm_device *dev);

1262
/* intel_opregion.c */
1263 1264 1265 1266
extern int intel_opregion_setup(struct drm_device *dev);
#ifdef CONFIG_ACPI
extern void intel_opregion_init(struct drm_device *dev);
extern void intel_opregion_fini(struct drm_device *dev);
1267 1268 1269
extern void intel_opregion_asle_intr(struct drm_device *dev);
extern void intel_opregion_gse_intr(struct drm_device *dev);
extern void intel_opregion_enable_asle(struct drm_device *dev);
1270
#else
1271 1272
static inline void intel_opregion_init(struct drm_device *dev) { return; }
static inline void intel_opregion_fini(struct drm_device *dev) { return; }
1273 1274 1275
static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
static inline void intel_opregion_gse_intr(struct drm_device *dev) { return; }
static inline void intel_opregion_enable_asle(struct drm_device *dev) { return; }
1276
#endif
1277

J
Jesse Barnes 已提交
1278 1279 1280 1281 1282 1283 1284 1285 1286
/* intel_acpi.c */
#ifdef CONFIG_ACPI
extern void intel_register_dsm_handler(void);
extern void intel_unregister_dsm_handler(void);
#else
static inline void intel_register_dsm_handler(void) { return; }
static inline void intel_unregister_dsm_handler(void) { return; }
#endif /* CONFIG_ACPI */

J
Jesse Barnes 已提交
1287 1288
/* modesetting */
extern void intel_modeset_init(struct drm_device *dev);
1289
extern void intel_modeset_gem_init(struct drm_device *dev);
J
Jesse Barnes 已提交
1290
extern void intel_modeset_cleanup(struct drm_device *dev);
1291
extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
1292
extern void i8xx_disable_fbc(struct drm_device *dev);
1293
extern void g4x_disable_fbc(struct drm_device *dev);
1294
extern void ironlake_disable_fbc(struct drm_device *dev);
1295 1296 1297
extern void intel_disable_fbc(struct drm_device *dev);
extern void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval);
extern bool intel_fbc_enabled(struct drm_device *dev);
1298
extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
J
Jesse Barnes 已提交
1299
extern void ironlake_enable_rc6(struct drm_device *dev);
1300
extern void gen6_set_rps(struct drm_device *dev, u8 val);
1301
extern void intel_detect_pch (struct drm_device *dev);
1302
extern int intel_trans_dp_port_sel (struct drm_crtc *crtc);
1303

1304
/* overlay */
1305
#ifdef CONFIG_DEBUG_FS
1306 1307
extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error);
1308 1309 1310 1311 1312

extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
extern void intel_display_print_error_state(struct seq_file *m,
					    struct drm_device *dev,
					    struct intel_display_error_state *error);
1313
#endif
1314

1315 1316 1317 1318 1319 1320 1321 1322 1323 1324 1325
#define LP_RING(d) (&((struct drm_i915_private *)(d))->ring[RCS])

#define BEGIN_LP_RING(n) \
	intel_ring_begin(LP_RING(dev_priv), (n))

#define OUT_RING(x) \
	intel_ring_emit(LP_RING(dev_priv), x)

#define ADVANCE_LP_RING() \
	intel_ring_advance(LP_RING(dev_priv))

1326 1327 1328 1329 1330 1331
/**
 * Lock test for when it's just for synchronization of ring access.
 *
 * In that case, we don't need to do it when GEM is initialized as nobody else
 * has access to the ring.
 */
1332
#define RING_LOCK_TEST_WITH_RETURN(dev, file) do {			\
1333
	if (LP_RING(dev->dev_private)->obj == NULL)			\
1334
		LOCK_TEST_WITH_RETURN(dev, file);			\
1335 1336
} while (0)

B
Ben Widawsky 已提交
1337 1338 1339 1340
/* On SNB platform, before reading ring registers forcewake bit
 * must be set to prevent GT core from power down and stale values being
 * returned.
 */
1341 1342
void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv);
void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv);
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Ben Widawsky 已提交
1343 1344 1345 1346 1347 1348 1349
void __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv);

/* We give fast paths for the really cool registers */
#define NEEDS_FORCE_WAKE(dev_priv, reg) \
	(((dev_priv)->info->gen >= 6) && \
	((reg) < 0x40000) && \
	((reg) != FORCEWAKE))
1350

1351 1352
#define __i915_read(x, y) \
static inline u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
B
Ben Widawsky 已提交
1353 1354
	u##x val = 0; \
	if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
1355
		gen6_gt_force_wake_get(dev_priv); \
B
Ben Widawsky 已提交
1356
		val = read##y(dev_priv->regs + reg); \
1357
		gen6_gt_force_wake_put(dev_priv); \
B
Ben Widawsky 已提交
1358 1359 1360
	} else { \
		val = read##y(dev_priv->regs + reg); \
	} \
C
Chris Wilson 已提交
1361
	trace_i915_reg_rw(false, reg, val, sizeof(val)); \
1362 1363
	return val; \
}
1364

1365 1366 1367 1368 1369 1370 1371 1372
__i915_read(8, b)
__i915_read(16, w)
__i915_read(32, l)
__i915_read(64, q)
#undef __i915_read

#define __i915_write(x, y) \
static inline void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
C
Chris Wilson 已提交
1373
	trace_i915_reg_rw(true, reg, val, sizeof(val)); \
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Ben Widawsky 已提交
1374 1375 1376
	if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
		__gen6_gt_wait_for_fifo(dev_priv); \
	} \
1377 1378 1379 1380 1381 1382 1383 1384 1385 1386 1387 1388 1389 1390 1391 1392 1393 1394
	write##y(val, dev_priv->regs + reg); \
}
__i915_write(8, b)
__i915_write(16, w)
__i915_write(32, l)
__i915_write(64, q)
#undef __i915_write

#define I915_READ8(reg)		i915_read8(dev_priv, (reg))
#define I915_WRITE8(reg, val)	i915_write8(dev_priv, (reg), (val))

#define I915_READ16(reg)	i915_read16(dev_priv, (reg))
#define I915_WRITE16(reg, val)	i915_write16(dev_priv, (reg), (val))
#define I915_READ16_NOTRACE(reg)	readw(dev_priv->regs + (reg))
#define I915_WRITE16_NOTRACE(reg, val)	writew(val, dev_priv->regs + (reg))

#define I915_READ(reg)		i915_read32(dev_priv, (reg))
#define I915_WRITE(reg, val)	i915_write32(dev_priv, (reg), (val))
1395 1396
#define I915_READ_NOTRACE(reg)		readl(dev_priv->regs + (reg))
#define I915_WRITE_NOTRACE(reg, val)	writel(val, dev_priv->regs + (reg))
1397 1398 1399

#define I915_WRITE64(reg, val)	i915_write64(dev_priv, (reg), (val))
#define I915_READ64(reg)	i915_read64(dev_priv, (reg))
1400 1401 1402 1403

#define POSTING_READ(reg)	(void)I915_READ_NOTRACE(reg)
#define POSTING_READ16(reg)	(void)I915_READ16_NOTRACE(reg)

1404

L
Linus Torvalds 已提交
1405
#endif