Skip to content

D
dragonwell8_hotspot

openanolis / dragonwell8_hotspot

通知 2
Star 2
Fork 0
D
dragonwell8_hotspot
提交 326dca6e 编写于 作者: T twisti
浏览文件
操作

6822110: Add AddressLiteral class on SPARC 

Summary: The Address class on SPARC currently handles both, addresses and address literals, what makes the Address class more complicated than it has to be.
Reviewed-by: never, kvn
上级 8a4ec7fd
展开全部 显示空白变更内容
内联 并排
Showing with 1120 addition and 1228 deletion
src/cpu/sparc/vm/c1_CodeStubs_sparc.cpp
浏览文件 @ 326dca6e
/*
* Copyright 1999-2007 Sun Microsystems, Inc. All Rights Reserved.
* Copyright 1999-2009 Sun Microsystems, Inc. All Rights Reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
......@@ -277,10 +277,11 @@ void PatchingStub::emit_code(LIR_Assembler* ce) {
if (_id == load_klass_id) {
// produce a copy of the load klass instruction for use by the being initialized case
#ifdef ASSERT
address start = __ pc();
Address addr = Address(_obj, address(NULL), oop_Relocation::spec(_oop_index));
__ sethi(addr, true);
__ add(addr, _obj, 0);
#endif
AddressLiteral addrlit(NULL, oop_Relocation::spec(_oop_index));
__ patchable_set(addrlit, _obj);
#ifdef ASSERT
for (int i = 0; i < _bytes_to_copy; i++) {
......
src/cpu/sparc/vm/c1_FrameMap_sparc.cpp
浏览文件 @ 326dca6e
/*
* Copyright 1999-2006 Sun Microsystems, Inc. All Rights Reserved.
* Copyright 1999-2009 Sun Microsystems, Inc. All Rights Reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
......@@ -327,7 +327,7 @@ void FrameMap::init () {
Address FrameMap::make_new_address(ByteSize sp_offset) const {
return Address(SP, 0, STACK_BIAS + in_bytes(sp_offset));
return Address(SP, STACK_BIAS + in_bytes(sp_offset));
}
......
src/cpu/sparc/vm/c1_LIRAssembler_sparc.cpp
浏览文件 @ 326dca6e
......@@ -196,7 +196,7 @@ void LIR_Assembler::osr_entry() {
// verify the interpreter's monitor has a non-null object
{
Label L;
__ ld_ptr(Address(OSR_buf, 0, slot_offset + BasicObjectLock::obj_offset_in_bytes()), O7);
__ ld_ptr(OSR_buf, slot_offset + BasicObjectLock::obj_offset_in_bytes(), O7);
__ cmp(G0, O7);
__ br(Assembler::notEqual, false, Assembler::pt, L);
__ delayed()->nop();
......@@ -205,9 +205,9 @@ void LIR_Assembler::osr_entry() {
}
#endif // ASSERT
// Copy the lock field into the compiled activation.
__ ld_ptr(Address(OSR_buf, 0, slot_offset + BasicObjectLock::lock_offset_in_bytes()), O7);
__ ld_ptr(OSR_buf, slot_offset + BasicObjectLock::lock_offset_in_bytes(), O7);
__ st_ptr(O7, frame_map()->address_for_monitor_lock(i));
__ ld_ptr(Address(OSR_buf, 0, slot_offset + BasicObjectLock::obj_offset_in_bytes()), O7);
__ ld_ptr(OSR_buf, slot_offset + BasicObjectLock::obj_offset_in_bytes(), O7);
__ st_ptr(O7, frame_map()->address_for_monitor_object(i));
}
}
......@@ -238,21 +238,21 @@ void LIR_Assembler::emit_string_compare(LIR_Opr left, LIR_Opr right, LIR_Opr dst
int offset_offset = java_lang_String::offset_offset_in_bytes(); // first character position
int count_offset = java_lang_String:: count_offset_in_bytes();
__ ld_ptr(Address(str0, 0, value_offset), tmp0);
__ ld(Address(str0, 0, offset_offset), tmp2);
__ ld_ptr(str0, value_offset, tmp0);
__ ld(str0, offset_offset, tmp2);
__ add(tmp0, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp0);
__ ld(Address(str0, 0, count_offset), str0);
__ ld(str0, count_offset, str0);
__ sll(tmp2, exact_log2(sizeof(jchar)), tmp2);
// str1 may be null
add_debug_info_for_null_check_here(info);
__ ld_ptr(Address(str1, 0, value_offset), tmp1);
__ ld_ptr(str1, value_offset, tmp1);
__ add(tmp0, tmp2, tmp0);
__ ld(Address(str1, 0, offset_offset), tmp2);
__ ld(str1, offset_offset, tmp2);
__ add(tmp1, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp1);
__ ld(Address(str1, 0, count_offset), str1);
__ ld(str1, count_offset, str1);
__ sll(tmp2, exact_log2(sizeof(jchar)), tmp2);
__ subcc(str0, str1, O7);
__ add(tmp1, tmp2, tmp1);
......@@ -412,9 +412,9 @@ void LIR_Assembler::emit_deopt_handler() {
#endif // ASSERT
compilation()->offsets()->set_value(CodeOffsets::Deopt, code_offset());
Address deopt_blob(G3_scratch, SharedRuntime::deopt_blob()->unpack());
AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack());
__ JUMP(deopt_blob, 0); // sethi;jmp
__ JUMP(deopt_blob, G3_scratch, 0); // sethi;jmp
__ delayed()->nop();
assert(code_offset() - offset <= deopt_handler_size, "overflow");
......@@ -441,13 +441,12 @@ void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info)
int oop_index = __ oop_recorder()->allocate_index((jobject)NULL);
PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id, oop_index);
Address addr = Address(reg, address(NULL), oop_Relocation::spec(oop_index));
assert(addr.rspec().type() == relocInfo::oop_type, "must be an oop reloc");
AddressLiteral addrlit(NULL, oop_Relocation::spec(oop_index));
assert(addrlit.rspec().type() == relocInfo::oop_type, "must be an oop reloc");
// It may not seem necessary to use a sethi/add pair to load a NULL into dest, but the
// NULL will be dynamically patched later and the patched value may be large. We must
// therefore generate the sethi/add as a placeholders
__ sethi(addr, true);
__ add(addr, reg, 0);
__ patchable_set(addrlit, reg);
patching_epilog(patch, lir_patch_normal, reg, info);
}
......@@ -706,7 +705,7 @@ void LIR_Assembler::ic_call(address entry, CodeEmitInfo* info) {
void LIR_Assembler::vtable_call(int vtable_offset, CodeEmitInfo* info) {
add_debug_info_for_null_check_here(info);
__ ld_ptr(Address(O0, 0, oopDesc::klass_offset_in_bytes()), G3_scratch);
__ ld_ptr(O0, oopDesc::klass_offset_in_bytes(), G3_scratch);
if (__ is_simm13(vtable_offset) ) {
__ ld_ptr(G3_scratch, vtable_offset, G5_method);
} else {
......@@ -715,7 +714,7 @@ void LIR_Assembler::vtable_call(int vtable_offset, CodeEmitInfo* info) {
// ld_ptr, set_hi, set
__ ld_ptr(G3_scratch, G5_method, G5_method);
}
__ ld_ptr(G5_method, in_bytes(methodOopDesc::from_compiled_offset()), G3_scratch);
__ ld_ptr(G5_method, methodOopDesc::from_compiled_offset(), G3_scratch);
__ callr(G3_scratch, G0);
// the peephole pass fills the delay slot
}
......@@ -738,8 +737,7 @@ int LIR_Assembler::load(Register s, int disp, Register d, BasicType ld_type, Cod
default : ShouldNotReachHere();
}
} else {
__ sethi(disp & ~0x3ff, O7, true);
__ add(O7, disp & 0x3ff, O7);
__ set(disp, O7);
if (info != NULL) add_debug_info_for_null_check_here(info);
load_offset = code_offset();
switch(ld_type) {
......@@ -775,8 +773,7 @@ void LIR_Assembler::store(Register value, Register base, int offset, BasicType t
default : ShouldNotReachHere();
}
} else {
__ sethi(offset & ~0x3ff, O7, true);
__ add(O7, offset & 0x3ff, O7);
__ set(offset, O7);
if (info != NULL) add_debug_info_for_null_check_here(info);
switch (type) {
case T_BOOLEAN: // fall through
......@@ -813,8 +810,7 @@ void LIR_Assembler::load(Register s, int disp, FloatRegister d, BasicType ld_typ
__ ldf(w, s, disp, d);
}
} else {
__ sethi(disp & ~0x3ff, O7, true);
__ add(O7, disp & 0x3ff, O7);
__ set(disp, O7);
if (info != NULL) add_debug_info_for_null_check_here(info);
__ ldf(w, s, O7, d);
}
......@@ -839,8 +835,7 @@ void LIR_Assembler::store(FloatRegister value, Register base, int offset, BasicT
__ stf(w, value, base, offset);
}
} else {
__ sethi(offset & ~0x3ff, O7, true);
__ add(O7, offset & 0x3ff, O7);
__ set(offset, O7);
if (info != NULL) add_debug_info_for_null_check_here(info);
__ stf(w, value, O7, base);
}
......@@ -852,8 +847,7 @@ int LIR_Assembler::store(LIR_Opr from_reg, Register base, int offset, BasicType
if (!Assembler::is_simm13(offset + (type == T_LONG) ? wordSize : 0)) {
assert(!unaligned, "can't handle this");
// for offsets larger than a simm13 we setup the offset in O7
__ sethi(offset & ~0x3ff, O7, true);
__ add(O7, offset & 0x3ff, O7);
__ set(offset, O7);
store_offset = store(from_reg, base, O7, type);
} else {
if (type == T_ARRAY || type == T_OBJECT) __ verify_oop(from_reg->as_register());
......@@ -937,8 +931,7 @@ int LIR_Assembler::load(Register base, int offset, LIR_Opr to_reg, BasicType typ
assert(base != O7, "destroying register");
assert(!unaligned, "can't handle this");
// for offsets larger than a simm13 we setup the offset in O7
__ sethi(offset & ~0x3ff, O7, true);
__ add(O7, offset & 0x3ff, O7);
__ set(offset, O7);
load_offset = load(base, O7, to_reg, type);
} else {
load_offset = code_offset();
......@@ -1213,7 +1206,7 @@ void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_cod
assert(to_reg->is_single_fpu(), "wrong register kind");
__ set(con, O7);
Address temp_slot(SP, 0, (frame::register_save_words * wordSize) + STACK_BIAS);
Address temp_slot(SP, (frame::register_save_words * wordSize) + STACK_BIAS);
__ st(O7, temp_slot);
__ ldf(FloatRegisterImpl::S, temp_slot, to_reg->as_float_reg());
}
......@@ -1238,8 +1231,8 @@ void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_cod
} else {
ShouldNotReachHere();
assert(to_reg->is_double_fpu(), "wrong register kind");
Address temp_slot_lo(SP, 0, ((frame::register_save_words ) * wordSize) + STACK_BIAS);
Address temp_slot_hi(SP, 0, ((frame::register_save_words) * wordSize) + (longSize/2) + STACK_BIAS);
Address temp_slot_lo(SP, ((frame::register_save_words ) * wordSize) + STACK_BIAS);
Address temp_slot_hi(SP, ((frame::register_save_words) * wordSize) + (longSize/2) + STACK_BIAS);
__ set(low(con), O7);
__ st(O7, temp_slot_lo);
__ set(high(con), O7);
......@@ -1267,17 +1260,16 @@ void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_cod
break;
}
RelocationHolder rspec = internal_word_Relocation::spec(const_addr);
AddressLiteral const_addrlit(const_addr, rspec);
if (to_reg->is_single_fpu()) {
__ sethi( (intx)const_addr & ~0x3ff, O7, true, rspec);
__ patchable_sethi(const_addrlit, O7);
__ relocate(rspec);
int offset = (intx)const_addr & 0x3ff;
__ ldf (FloatRegisterImpl::S, O7, offset, to_reg->as_float_reg());
__ ldf(FloatRegisterImpl::S, O7, const_addrlit.low10(), to_reg->as_float_reg());
} else {
assert(to_reg->is_single_cpu(), "Must be a cpu register.");
__ set((intx)const_addr, O7, rspec);
__ set(const_addrlit, O7);
load(O7, 0, to_reg->as_register(), T_INT);
}
}
......@@ -1293,10 +1285,10 @@ void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_cod
RelocationHolder rspec = internal_word_Relocation::spec(const_addr);
if (to_reg->is_double_fpu()) {
__ sethi( (intx)const_addr & ~0x3ff, O7, true, rspec);
int offset = (intx)const_addr & 0x3ff;
AddressLiteral const_addrlit(const_addr, rspec);
__ patchable_sethi(const_addrlit, O7);
__ relocate(rspec);
__ ldf (FloatRegisterImpl::D, O7, offset, to_reg->as_double_reg());
__ ldf (FloatRegisterImpl::D, O7, const_addrlit.low10(), to_reg->as_double_reg());
} else {
assert(to_reg->is_double_cpu(), "Must be a long register.");
#ifdef _LP64
......@@ -1317,7 +1309,7 @@ void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_cod
Address LIR_Assembler::as_Address(LIR_Address* addr) {
Register reg = addr->base()->as_register();
return Address(reg, 0, addr->disp());
return Address(reg, addr->disp());
}
......@@ -1360,13 +1352,13 @@ void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
Address base = as_Address(addr);
return Address(base.base(), 0, base.disp() + hi_word_offset_in_bytes);
return Address(base.base(), base.disp() + hi_word_offset_in_bytes);
}
Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
Address base = as_Address(addr);
return Address(base.base(), 0, base.disp() + lo_word_offset_in_bytes);
return Address(base.base(), base.disp() + lo_word_offset_in_bytes);
}
......@@ -1396,8 +1388,7 @@ void LIR_Assembler::mem2reg(LIR_Opr src_opr, LIR_Opr dest, BasicType type,
if (addr->index()->is_illegal()) {
if (!Assembler::is_simm13(disp_value) && (!unaligned || Assembler::is_simm13(disp_value + 4))) {
if (needs_patching) {
__ sethi(0, O7, true);
__ add(O7, 0, O7);
__ patchable_set(0, O7);
} else {
__ set(disp_value, O7);
}
......@@ -1544,8 +1535,7 @@ void LIR_Assembler::reg2mem(LIR_Opr from_reg, LIR_Opr dest, BasicType type,
if (addr->index()->is_illegal()) {
if (!Assembler::is_simm13(disp_value) && (!unaligned || Assembler::is_simm13(disp_value + 4))) {
if (needs_patching) {
__ sethi(0, O7, true);
__ add(O7, 0, O7);
__ patchable_set(0, O7);
} else {
__ set(disp_value, O7);
}
......@@ -1627,8 +1617,8 @@ void LIR_Assembler::emit_static_call_stub() {
__ set_oop(NULL, G5);
// must be set to -1 at code generation time
Address a(G3, (address)-1);
__ jump_to(a, 0);
AddressLiteral addrlit(-1);
__ jump_to(addrlit, G3);
__ delayed()->nop();
assert(__ offset() - start <= call_stub_size, "stub too big");
......@@ -2063,7 +2053,7 @@ void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmit
address pc_for_athrow = __ pc();
int pc_for_athrow_offset = __ offset();
RelocationHolder rspec = internal_word_Relocation::spec(pc_for_athrow);
__ set((intptr_t)pc_for_athrow, Oissuing_pc, rspec);
__ set(pc_for_athrow, Oissuing_pc, rspec);
add_call_info(pc_for_athrow_offset, info); // for exception handler
__ call(Runtime1::entry_for(Runtime1::handle_exception_id), relocInfo::runtime_call_type);
......@@ -2451,7 +2441,7 @@ void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
}
Address flags_addr(mdo, 0, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias);
Address flags_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias);
__ ldub(flags_addr, data_val);
__ or3(data_val, BitData::null_seen_byte_constant(), data_val);
__ stb(data_val, flags_addr);
......@@ -2738,7 +2728,7 @@ void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
__ add(mdo, O7, mdo);
}
Address counter_addr(mdo, 0, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias);
Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias);
__ lduw(counter_addr, tmp1);
__ add(tmp1, DataLayout::counter_increment, tmp1);
__ stw(tmp1, counter_addr);
......@@ -2764,7 +2754,7 @@ void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
for (i = 0; i < VirtualCallData::row_limit(); i++) {
ciKlass* receiver = vc_data->receiver(i);
if (known_klass->equals(receiver)) {
Address data_addr(mdo, 0, md->byte_offset_of_slot(data,
Address data_addr(mdo, md->byte_offset_of_slot(data,
VirtualCallData::receiver_count_offset(i)) -
mdo_offset_bias);
__ lduw(data_addr, tmp1);
......@@ -2782,11 +2772,11 @@ void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
for (i = 0; i < VirtualCallData::row_limit(); i++) {
ciKlass* receiver = vc_data->receiver(i);
if (receiver == NULL) {
Address recv_addr(mdo, 0, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)) -
Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)) -
mdo_offset_bias);
jobject2reg(known_klass->encoding(), tmp1);
__ st_ptr(tmp1, recv_addr);
Address data_addr(mdo, 0, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) -
Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) -
mdo_offset_bias);
__ lduw(data_addr, tmp1);
__ add(tmp1, DataLayout::counter_increment, tmp1);
......@@ -2795,20 +2785,20 @@ void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
}
}
} else {
load(Address(recv, 0, oopDesc::klass_offset_in_bytes()), recv, T_OBJECT);
load(Address(recv, oopDesc::klass_offset_in_bytes()), recv, T_OBJECT);
Label update_done;
uint i;
for (i = 0; i < VirtualCallData::row_limit(); i++) {
Label next_test;
// See if the receiver is receiver[n].
Address receiver_addr(mdo, 0, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)) -
Address receiver_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)) -
mdo_offset_bias);
__ ld_ptr(receiver_addr, tmp1);
__ verify_oop(tmp1);
__ cmp(recv, tmp1);
__ brx(Assembler::notEqual, false, Assembler::pt, next_test);
__ delayed()->nop();
Address data_addr(mdo, 0, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) -
Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) -
mdo_offset_bias);
__ lduw(data_addr, tmp1);
__ add(tmp1, DataLayout::counter_increment, tmp1);
......@@ -2821,7 +2811,7 @@ void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
// Didn't find receiver; find next empty slot and fill it in
for (i = 0; i < VirtualCallData::row_limit(); i++) {
Label next_test;
Address recv_addr(mdo, 0, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)) -
Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)) -
mdo_offset_bias);
load(recv_addr, tmp1, T_OBJECT);
__ tst(tmp1);
......@@ -2829,8 +2819,8 @@ void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
__ delayed()->nop();
__ st_ptr(recv, recv_addr);
__ set(DataLayout::counter_increment, tmp1);
__ st_ptr(tmp1, Address(mdo, 0, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) -
mdo_offset_bias));
__ st_ptr(tmp1, mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) -
mdo_offset_bias);
if (i < (VirtualCallData::row_limit() - 1)) {
__ br(Assembler::always, false, Assembler::pt, update_done);
__ delayed()->nop();
......
src/cpu/sparc/vm/c1_MacroAssembler_sparc.cpp
浏览文件 @ 326dca6e
/*
* Copyright 1999-2008 Sun Microsystems, Inc. All Rights Reserved.
* Copyright 1999-2009 Sun Microsystems, Inc. All Rights Reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
......@@ -29,13 +29,13 @@ void C1_MacroAssembler::inline_cache_check(Register receiver, Register iCache) {
Label L;
const Register temp_reg = G3_scratch;
// Note: needs more testing of out-of-line vs. inline slow case
Address ic_miss(temp_reg, SharedRuntime::get_ic_miss_stub());
verify_oop(receiver);
ld_ptr(receiver, oopDesc::klass_offset_in_bytes(), temp_reg);
cmp(temp_reg, iCache);
brx(Assembler::equal, true, Assembler::pt, L);
delayed()->nop();
jump_to(ic_miss, 0);
AddressLiteral ic_miss(SharedRuntime::get_ic_miss_stub());
jump_to(ic_miss, temp_reg);
delayed()->nop();
align(CodeEntryAlignment);
bind(L);
......@@ -84,7 +84,7 @@ void C1_MacroAssembler::lock_object(Register Rmark, Register Roop, Register Rbox
Label done;
Address mark_addr(Roop, 0, oopDesc::mark_offset_in_bytes());
Address mark_addr(Roop, oopDesc::mark_offset_in_bytes());
// The following move must be the first instruction of emitted since debug
// information may be generated for it.
......@@ -132,7 +132,7 @@ void C1_MacroAssembler::unlock_object(Register Rmark, Register Roop, Register Rb
Label done;
Address mark_addr(Roop, 0, oopDesc::mark_offset_in_bytes());
Address mark_addr(Roop, oopDesc::mark_offset_in_bytes());
assert(mark_addr.disp() == 0, "cas must take a zero displacement");
if (UseBiasedLocking) {
......@@ -370,7 +370,7 @@ void C1_MacroAssembler::allocate_array(
void C1_MacroAssembler::verify_stack_oop(int stack_offset) {
if (!VerifyOops) return;
verify_oop_addr(Address(SP, 0, stack_offset + STACK_BIAS));
verify_oop_addr(Address(SP, stack_offset + STACK_BIAS));
}
void C1_MacroAssembler::verify_not_null_oop(Register r) {
......
src/cpu/sparc/vm/c1_Runtime1_sparc.cpp
浏览文件 @ 326dca6e
/*
* Copyright 1999-2007 Sun Microsystems, Inc. All Rights Reserved.
* Copyright 1999-2009 Sun Microsystems, Inc. All Rights Reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
......@@ -57,13 +57,13 @@ int StubAssembler::call_RT(Register oop_result1, Register oop_result2, address e
// check for pending exceptions
{ Label L;
Address exception_addr(G2_thread, 0, in_bytes(Thread::pending_exception_offset()));
Address exception_addr(G2_thread, Thread::pending_exception_offset());
ld_ptr(exception_addr, Gtemp);
br_null(Gtemp, false, pt, L);
delayed()->nop();
Address vm_result_addr(G2_thread, 0, in_bytes(JavaThread::vm_result_offset()));
Address vm_result_addr(G2_thread, JavaThread::vm_result_offset());
st_ptr(G0, vm_result_addr);
Address vm_result_addr_2(G2_thread, 0, in_bytes(JavaThread::vm_result_2_offset()));
Address vm_result_addr_2(G2_thread, JavaThread::vm_result_2_offset());
st_ptr(G0, vm_result_addr_2);
if (frame_size() == no_frame_size) {
......@@ -73,8 +73,8 @@ int StubAssembler::call_RT(Register oop_result1, Register oop_result2, address e
} else if (_stub_id == Runtime1::forward_exception_id) {
should_not_reach_here();
} else {
Address exc(G4, Runtime1::entry_for(Runtime1::forward_exception_id));
jump_to(exc, 0);
AddressLiteral exc(Runtime1::entry_for(Runtime1::forward_exception_id));
jump_to(exc, G4);
delayed()->nop();
}
bind(L);
......@@ -85,7 +85,7 @@ int StubAssembler::call_RT(Register oop_result1, Register oop_result2, address e
get_vm_result (oop_result1);
} else {
// be a little paranoid and clear the result
Address vm_result_addr(G2_thread, 0, in_bytes(JavaThread::vm_result_offset()));
Address vm_result_addr(G2_thread, JavaThread::vm_result_offset());
st_ptr(G0, vm_result_addr);
}
......@@ -93,7 +93,7 @@ int StubAssembler::call_RT(Register oop_result1, Register oop_result2, address e
get_vm_result_2(oop_result2);
} else {
// be a little paranoid and clear the result
Address vm_result_addr_2(G2_thread, 0, in_bytes(JavaThread::vm_result_2_offset()));
Address vm_result_addr_2(G2_thread, JavaThread::vm_result_2_offset());
st_ptr(G0, vm_result_addr_2);
}
......@@ -479,7 +479,7 @@ OopMapSet* Runtime1::generate_code_for(StubID id, StubAssembler* sasm) {
Register G4_length = G4; // Incoming
Register O0_obj = O0; // Outgoing
Address klass_lh(G5_klass, 0, ((klassOopDesc::header_size() * HeapWordSize)
Address klass_lh(G5_klass, ((klassOopDesc::header_size() * HeapWordSize)
+ Klass::layout_helper_offset_in_bytes()));
assert(Klass::_lh_header_size_shift % BitsPerByte == 0, "bytewise");
assert(Klass::_lh_header_size_mask == 0xFF, "bytewise");
......@@ -902,8 +902,8 @@ OopMapSet* Runtime1::generate_code_for(StubID id, StubAssembler* sasm) {
__ srl(addr, CardTableModRefBS::card_shift, addr);
#endif
Address rs(cardtable, (address)byte_map_base);
__ load_address(rs); // cardtable := <card table base>
AddressLiteral rs(byte_map_base);
__ set(rs, cardtable); // cardtable := <card table base>
__ ldub(addr, cardtable, tmp); // tmp := [addr + cardtable]
__ br_on_reg_cond(Assembler::rc_nz, /*annul*/false, Assembler::pt,
......@@ -1022,8 +1022,8 @@ void Runtime1::generate_handle_exception(StubAssembler* sasm, OopMapSet* oop_map
__ restore();
Address exc(G4, Runtime1::entry_for(Runtime1::unwind_exception_id));
__ jump_to(exc, 0);
AddressLiteral exc(Runtime1::entry_for(Runtime1::unwind_exception_id));
__ jump_to(exc, G4);
__ delayed()->nop();
......
src/cpu/sparc/vm/dump_sparc.cpp
浏览文件 @ 326dca6e
/*
* Copyright 2004-2007 Sun Microsystems, Inc. All Rights Reserved.
* Copyright 2004-2009 Sun Microsystems, Inc. All Rights Reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
......@@ -106,8 +106,7 @@ void CompactingPermGenGen::generate_vtable_methods(void** vtbl_list,
__ and3(L0, 255, L4); // Isolate L3 = method offset;.
__ sll(L4, LogBytesPerWord, L4);
__ ld_ptr(L3, L4, L4); // Get address of correct virtual method
Address method(L4, 0);
__ jmpl(method, G0); // Jump to correct method.
__ jmpl(L4, 0, G0); // Jump to correct method.
__ delayed()->restore(); // Restore registers.
__ flush();
......
src/cpu/sparc/vm/icBuffer_sparc.cpp
浏览文件 @ 326dca6e
/*
* Copyright 1997-2006 Sun Microsystems, Inc. All Rights Reserved.
* Copyright 1997-2009 Sun Microsystems, Inc. All Rights Reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
......@@ -46,14 +46,13 @@ void InlineCacheBuffer::assemble_ic_buffer_code(address code_begin, oop cached_o
// (1) the oop is old (i.e., doesn't matter for scavenges)
// (2) these ICStubs are removed *before* a GC happens, so the roots disappear
assert(cached_oop == NULL || cached_oop->is_perm(), "must be old oop");
Address cached_oop_addr(G5_inline_cache_reg, address(cached_oop));
// Force the sethi to generate the fixed sequence so next_instruction_address works
masm->sethi(cached_oop_addr, true /* ForceRelocatable */ );
masm->add(cached_oop_addr, G5_inline_cache_reg);
AddressLiteral cached_oop_addrlit(cached_oop, relocInfo::none);
// Force the set to generate the fixed sequence so next_instruction_address works
masm->patchable_set(cached_oop_addrlit, G5_inline_cache_reg);
assert(G3_scratch != G5_method, "Do not clobber the method oop in the transition stub");
assert(G3_scratch != G5_inline_cache_reg, "Do not clobber the inline cache register in the transition stub");
Address entry(G3_scratch, entry_point);
masm->JUMP(entry, 0);
AddressLiteral entry(entry_point);
masm->JUMP(entry, G3_scratch, 0);
masm->delayed()->nop();
masm->flush();
}
......
src/cpu/sparc/vm/interp_masm_sparc.cpp
浏览文件 @ 326dca6e
/*
* Copyright 1997-2008 Sun Microsystems, Inc. All Rights Reserved.
* Copyright 1997-2009 Sun Microsystems, Inc. All Rights Reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
......@@ -35,8 +35,8 @@
// This file specializes the assember with interpreter-specific macros
const Address InterpreterMacroAssembler::l_tmp( FP, 0, (frame::interpreter_frame_l_scratch_fp_offset * wordSize ) + STACK_BIAS);
const Address InterpreterMacroAssembler::d_tmp( FP, 0, (frame::interpreter_frame_d_scratch_fp_offset * wordSize) + STACK_BIAS);
const Address InterpreterMacroAssembler::l_tmp(FP, (frame::interpreter_frame_l_scratch_fp_offset * wordSize) + STACK_BIAS);
const Address InterpreterMacroAssembler::d_tmp(FP, (frame::interpreter_frame_d_scratch_fp_offset * wordSize) + STACK_BIAS);
#else // CC_INTERP
#ifndef STATE
......@@ -80,12 +80,10 @@ void InterpreterMacroAssembler::dispatch_prolog(TosState state, int bcp_incr) {
#else
ldub( Lbcp, bcp_incr, Lbyte_code); // load next bytecode
// dispatch table to use
Address tbl(G3_scratch, (address)Interpreter::dispatch_table(state));
sethi(tbl);
AddressLiteral tbl(Interpreter::dispatch_table(state));
sll(Lbyte_code, LogBytesPerWord, Lbyte_code); // multiply by wordSize
add(tbl, tbl.base(), 0);
ld_ptr( G3_scratch, Lbyte_code, IdispatchAddress); // get entry addr
set(tbl, G3_scratch); // compute addr of table
ld_ptr(G3_scratch, Lbyte_code, IdispatchAddress); // get entry addr
#endif
}
......@@ -165,8 +163,7 @@ void InterpreterMacroAssembler::check_and_handle_popframe(Register scratch_reg)
Label L;
// Check the "pending popframe condition" flag in the current thread
Address popframe_condition_addr(G2_thread, 0, in_bytes(JavaThread::popframe_condition_offset()));
ld(popframe_condition_addr, scratch_reg);
ld(G2_thread, JavaThread::popframe_condition_offset(), scratch_reg);
// Initiate popframe handling only if it is not already being processed. If the flag
// has the popframe_processing bit set, it means that this code is called *during* popframe
......@@ -192,11 +189,10 @@ void InterpreterMacroAssembler::check_and_handle_popframe(Register scratch_reg)
void InterpreterMacroAssembler::load_earlyret_value(TosState state) {
Register thr_state = G4_scratch;
ld_ptr(Address(G2_thread, 0, in_bytes(JavaThread::jvmti_thread_state_offset())),
thr_state);
const Address tos_addr(thr_state, 0, in_bytes(JvmtiThreadState::earlyret_tos_offset()));
const Address oop_addr(thr_state, 0, in_bytes(JvmtiThreadState::earlyret_oop_offset()));
const Address val_addr(thr_state, 0, in_bytes(JvmtiThreadState::earlyret_value_offset()));
ld_ptr(G2_thread, JavaThread::jvmti_thread_state_offset(), thr_state);
const Address tos_addr(thr_state, JvmtiThreadState::earlyret_tos_offset());
const Address oop_addr(thr_state, JvmtiThreadState::earlyret_oop_offset());
const Address val_addr(thr_state, JvmtiThreadState::earlyret_value_offset());
switch (state) {
case ltos: ld_long(val_addr, Otos_l); break;
case atos: ld_ptr(oop_addr, Otos_l);
......@@ -222,8 +218,7 @@ void InterpreterMacroAssembler::check_and_handle_earlyret(Register scratch_reg)
if (JvmtiExport::can_force_early_return()) {
Label L;
Register thr_state = G3_scratch;
ld_ptr(Address(G2_thread, 0, in_bytes(JavaThread::jvmti_thread_state_offset())),
thr_state);
ld_ptr(G2_thread, JavaThread::jvmti_thread_state_offset(), thr_state);
tst(thr_state);
br(zero, false, pt, L); // if (thread->jvmti_thread_state() == NULL) exit;
delayed()->nop();
......@@ -231,16 +226,14 @@ void InterpreterMacroAssembler::check_and_handle_earlyret(Register scratch_reg)
// Initiate earlyret handling only if it is not already being processed.
// If the flag has the earlyret_processing bit set, it means that this code
// is called *during* earlyret handling - we don't want to reenter.
ld(Address(thr_state, 0, in_bytes(JvmtiThreadState::earlyret_state_offset())),
G4_scratch);
ld(thr_state, JvmtiThreadState::earlyret_state_offset(), G4_scratch);
cmp(G4_scratch, JvmtiThreadState::earlyret_pending);
br(Assembler::notEqual, false, pt, L);
delayed()->nop();
// Call Interpreter::remove_activation_early_entry() to get the address of the
// same-named entrypoint in the generated interpreter code
Address tos_addr(thr_state, 0, in_bytes(JvmtiThreadState::earlyret_tos_offset()));
ld(tos_addr, Otos_l1);
ld(thr_state, JvmtiThreadState::earlyret_tos_offset(), Otos_l1);
call_VM_leaf(noreg, CAST_FROM_FN_PTR(address, Interpreter::remove_activation_early_entry), Otos_l1);
// Jump to Interpreter::_remove_activation_early_entry
......@@ -294,10 +287,9 @@ void InterpreterMacroAssembler::dispatch_Lbyte_code(TosState state, address* tab
} else {
#endif
// dispatch table to use
Address tbl(G3_scratch, (address)table);
AddressLiteral tbl(table);
sll(Lbyte_code, LogBytesPerWord, Lbyte_code); // multiply by wordSize
load_address(tbl); // compute addr of table
set(tbl, G3_scratch); // compute addr of table
ld_ptr(G3_scratch, Lbyte_code, G3_scratch); // get entry addr
#ifdef FAST_DISPATCH
}
......@@ -601,26 +593,17 @@ void InterpreterMacroAssembler::empty_expression_stack() {
// Reset SP by subtracting more space from Lesp.
Label done;
const Address max_stack (Lmethod, 0, in_bytes(methodOopDesc::max_stack_offset()));
const Address access_flags(Lmethod, 0, in_bytes(methodOopDesc::access_flags_offset()));
verify_oop(Lmethod);
assert( G4_scratch != Gframe_size,
"Only you can prevent register aliasing!");
assert(G4_scratch != Gframe_size, "Only you can prevent register aliasing!");
// A native does not need to do this, since its callee does not change SP.
ld(access_flags, Gframe_size);
ld(Lmethod, methodOopDesc::access_flags_offset(), Gframe_size); // Load access flags.
btst(JVM_ACC_NATIVE, Gframe_size);
br(Assembler::notZero, false, Assembler::pt, done);
delayed()->nop();
//
// Compute max expression stack+register save area
//
lduh( max_stack, Gframe_size );
lduh(Lmethod, in_bytes(methodOopDesc::max_stack_offset()), Gframe_size); // Load max stack.
if (TaggedStackInterpreter) sll ( Gframe_size, 1, Gframe_size); // max_stack * 2 for TAGS
add( Gframe_size, frame::memory_parameter_word_sp_offset, Gframe_size );
......@@ -721,8 +704,7 @@ void InterpreterMacroAssembler::call_from_interpreter(Register target, Register
verify_thread();
Label skip_compiled_code;
const Address interp_only (G2_thread, 0, in_bytes(JavaThread::interp_only_mode_offset()));
const Address interp_only(G2_thread, JavaThread::interp_only_mode_offset());
ld(interp_only, scratch);
tst(scratch);
br(Assembler::notZero, true, Assembler::pn, skip_compiled_code);
......@@ -916,8 +898,8 @@ void InterpreterMacroAssembler::throw_if_not_2( address throw_entry_point,
Register Rscratch,
Label& ok ) {
assert(throw_entry_point != NULL, "entry point must be generated by now");
Address dest(Rscratch, throw_entry_point);
jump_to(dest);
AddressLiteral dest(throw_entry_point);
jump_to(dest, Rscratch);
delayed()->nop();
bind(ok);
}
......@@ -1035,18 +1017,18 @@ void InterpreterMacroAssembler::unlock_if_synchronized_method(TosState state,
Label unlocked, unlock, no_unlock;
// get the value of _do_not_unlock_if_synchronized into G1_scratch
const Address do_not_unlock_if_synchronized(G2_thread, 0,
in_bytes(JavaThread::do_not_unlock_if_synchronized_offset()));
const Address do_not_unlock_if_synchronized(G2_thread,
JavaThread::do_not_unlock_if_synchronized_offset());
ldbool(do_not_unlock_if_synchronized, G1_scratch);
stbool(G0, do_not_unlock_if_synchronized); // reset the flag
// check if synchronized method
const Address access_flags(Lmethod, 0, in_bytes(methodOopDesc::access_flags_offset()));
const Address access_flags(Lmethod, methodOopDesc::access_flags_offset());
interp_verify_oop(Otos_i, state, __FILE__, __LINE__);
push(state); // save tos
ld(access_flags, G3_scratch);
ld(access_flags, G3_scratch); // Load access flags.
btst(JVM_ACC_SYNCHRONIZED, G3_scratch);
br( zero, false, pt, unlocked);
br(zero, false, pt, unlocked);
delayed()->nop();
// Don't unlock anything if the _do_not_unlock_if_synchronized flag
......@@ -1236,8 +1218,8 @@ void InterpreterMacroAssembler::lock_object(Register lock_reg, Register Object)
Register obj_reg = Object;
Register mark_reg = G4_scratch;
Register temp_reg = G1_scratch;
Address lock_addr = Address(lock_reg, 0, BasicObjectLock::lock_offset_in_bytes());
Address mark_addr = Address(obj_reg, 0, oopDesc::mark_offset_in_bytes());
Address lock_addr(lock_reg, BasicObjectLock::lock_offset_in_bytes());
Address mark_addr(obj_reg, oopDesc::mark_offset_in_bytes());
Label done;
Label slow_case;
......@@ -1315,9 +1297,8 @@ void InterpreterMacroAssembler::unlock_object(Register lock_reg) {
Register obj_reg = G3_scratch;
Register mark_reg = G4_scratch;
Register displaced_header_reg = G1_scratch;
Address lock_addr = Address(lock_reg, 0, BasicObjectLock::lock_offset_in_bytes());
Address lockobj_addr = Address(lock_reg, 0, BasicObjectLock::obj_offset_in_bytes());
Address mark_addr = Address(obj_reg, 0, oopDesc::mark_offset_in_bytes());
Address lockobj_addr(lock_reg, BasicObjectLock::obj_offset_in_bytes());
Address mark_addr(obj_reg, oopDesc::mark_offset_in_bytes());
Label done;
if (UseBiasedLocking) {
......@@ -1328,7 +1309,8 @@ void InterpreterMacroAssembler::unlock_object(Register lock_reg) {
}
// Test first if we are in the fast recursive case
ld_ptr(lock_addr, displaced_header_reg, BasicLock::displaced_header_offset_in_bytes());
Address lock_addr(lock_reg, BasicObjectLock::lock_offset_in_bytes() + BasicLock::displaced_header_offset_in_bytes());
ld_ptr(lock_addr, displaced_header_reg);
br_null(displaced_header_reg, true, Assembler::pn, done);
delayed()->st_ptr(G0, lockobj_addr); // free entry
......@@ -1384,7 +1366,7 @@ void InterpreterMacroAssembler::set_method_data_pointer_for_bcp() {
Label zero_continue;
// Test MDO to avoid the call if it is NULL.
ld_ptr(Lmethod, in_bytes(methodOopDesc::method_data_offset()), ImethodDataPtr);
ld_ptr(Lmethod, methodOopDesc::method_data_offset(), ImethodDataPtr);
test_method_data_pointer(zero_continue);
call_VM_leaf(noreg, CAST_FROM_FN_PTR(address, InterpreterRuntime::bcp_to_di), Lmethod, Lbcp);
set_method_data_pointer_offset(O0);
......@@ -1413,7 +1395,7 @@ void InterpreterMacroAssembler::verify_method_data_pointer() {
// If the mdp is valid, it will point to a DataLayout header which is
// consistent with the bcp. The converse is highly probable also.
lduh(ImethodDataPtr, in_bytes(DataLayout::bci_offset()), G3_scratch);
ld_ptr(Address(Lmethod, 0, in_bytes(methodOopDesc::const_offset())), O5);
ld_ptr(Lmethod, methodOopDesc::const_offset(), O5);
add(G3_scratch, in_bytes(constMethodOopDesc::codes_offset()), G3_scratch);
add(G3_scratch, O5, G3_scratch);
cmp(Lbcp, G3_scratch);
......@@ -1424,7 +1406,7 @@ void InterpreterMacroAssembler::verify_method_data_pointer() {
// %%% should use call_VM_leaf here?
//call_VM_leaf(noreg, ..., Lmethod, Lbcp, ImethodDataPtr);
save_frame_and_mov(sizeof(jdouble) / wordSize, Lmethod, O0, Lbcp, O1);
Address d_save(FP, 0, -sizeof(jdouble) + STACK_BIAS);
Address d_save(FP, -sizeof(jdouble) + STACK_BIAS);
stf(FloatRegisterImpl::D, Ftos_d, d_save);
mov(temp_reg->after_save(), O2);
save_thread(L7_thread_cache);
......@@ -1456,14 +1438,14 @@ void InterpreterMacroAssembler::test_invocation_counter_for_mdp(Register invocat
#endif
// Test to see if we should create a method data oop
Address profile_limit(Rtmp, (address)&InvocationCounter::InterpreterProfileLimit);
AddressLiteral profile_limit((address) &InvocationCounter::InterpreterProfileLimit);
#ifdef _LP64
delayed()->nop();
sethi(profile_limit);
sethi(profile_limit, Rtmp);
#else
delayed()->sethi(profile_limit);
delayed()->sethi(profile_limit, Rtmp);
#endif
ld(profile_limit, Rtmp);
ld(Rtmp, profile_limit.low10(), Rtmp);
cmp(invocation_count, Rtmp);
br(Assembler::lessUnsigned, false, Assembler::pn, profile_continue);
delayed()->nop();
......@@ -1521,7 +1503,7 @@ void InterpreterMacroAssembler::increment_mdp_data_at(int constant,
Register bumped_count,
bool decrement) {
// Locate the counter at a fixed offset from the mdp:
Address counter(ImethodDataPtr, 0, constant);
Address counter(ImethodDataPtr, constant);
increment_mdp_data_at(counter, bumped_count, decrement);
}
......@@ -1535,7 +1517,7 @@ void InterpreterMacroAssembler::increment_mdp_data_at(Register reg,
bool decrement) {
// Add the constant to reg to get the offset.
add(ImethodDataPtr, reg, scratch2);
Address counter(scratch2, 0, constant);
Address counter(scratch2, constant);
increment_mdp_data_at(counter, bumped_count, decrement);
}
......@@ -2201,7 +2183,7 @@ int InterpreterMacroAssembler::top_most_monitor_byte_offset() {
Address InterpreterMacroAssembler::top_most_monitor() {
return Address(FP, 0, top_most_monitor_byte_offset());
return Address(FP, top_most_monitor_byte_offset());
}
......@@ -2214,15 +2196,15 @@ void InterpreterMacroAssembler::compute_stack_base( Register Rdest ) {
void InterpreterMacroAssembler::increment_invocation_counter( Register Rtmp, Register Rtmp2 ) {
assert(UseCompiler, "incrementing must be useful");
#ifdef CC_INTERP
Address inv_counter(G5_method, 0, in_bytes(methodOopDesc::invocation_counter_offset()
+ InvocationCounter::counter_offset()));
Address be_counter(G5_method, 0, in_bytes(methodOopDesc::backedge_counter_offset()
+ InvocationCounter::counter_offset()));
Address inv_counter(G5_method, methodOopDesc::invocation_counter_offset() +
InvocationCounter::counter_offset());
Address be_counter (G5_method, methodOopDesc::backedge_counter_offset() +
InvocationCounter::counter_offset());
#else
Address inv_counter(Lmethod, 0, in_bytes(methodOopDesc::invocation_counter_offset()
+ InvocationCounter::counter_offset()));
Address be_counter(Lmethod, 0, in_bytes(methodOopDesc::backedge_counter_offset()
+ InvocationCounter::counter_offset()));
Address inv_counter(Lmethod, methodOopDesc::invocation_counter_offset() +
InvocationCounter::counter_offset());
Address be_counter (Lmethod, methodOopDesc::backedge_counter_offset() +
InvocationCounter::counter_offset());
#endif /* CC_INTERP */
int delta = InvocationCounter::count_increment;
......@@ -2250,15 +2232,15 @@ void InterpreterMacroAssembler::increment_invocation_counter( Register Rtmp, Reg
void InterpreterMacroAssembler::increment_backedge_counter( Register Rtmp, Register Rtmp2 ) {
assert(UseCompiler, "incrementing must be useful");
#ifdef CC_INTERP
Address be_counter(G5_method, 0, in_bytes(methodOopDesc::backedge_counter_offset()
+ InvocationCounter::counter_offset()));
Address inv_counter(G5_method, 0, in_bytes(methodOopDesc::invocation_counter_offset()
+ InvocationCounter::counter_offset()));
Address be_counter (G5_method, methodOopDesc::backedge_counter_offset() +
InvocationCounter::counter_offset());
Address inv_counter(G5_method, methodOopDesc::invocation_counter_offset() +
InvocationCounter::counter_offset());
#else
Address be_counter(Lmethod, 0, in_bytes(methodOopDesc::backedge_counter_offset()
+ InvocationCounter::counter_offset()));
Address inv_counter(Lmethod, 0, in_bytes(methodOopDesc::invocation_counter_offset()
+ InvocationCounter::counter_offset()));
Address be_counter (Lmethod, methodOopDesc::backedge_counter_offset() +
InvocationCounter::counter_offset());
Address inv_counter(Lmethod, methodOopDesc::invocation_counter_offset() +
InvocationCounter::counter_offset());
#endif /* CC_INTERP */
int delta = InvocationCounter::count_increment;
// Load each counter in a register
......@@ -2289,7 +2271,7 @@ void InterpreterMacroAssembler::test_backedge_count_for_osr( Register backedge_c
assert_different_registers(backedge_count, Rtmp, branch_bcp);
assert(UseOnStackReplacement,"Must UseOnStackReplacement to test_backedge_count_for_osr");
Address limit(Rtmp, address(&InvocationCounter::InterpreterBackwardBranchLimit));
AddressLiteral limit(&InvocationCounter::InterpreterBackwardBranchLimit);
load_contents(limit, Rtmp);
cmp(backedge_count, Rtmp);
br(Assembler::lessUnsigned, false, Assembler::pt, did_not_overflow);
......@@ -2435,9 +2417,7 @@ void InterpreterMacroAssembler::notify_method_entry() {
if (JvmtiExport::can_post_interpreter_events()) {
Label L;
Register temp_reg = O5;
const Address interp_only (G2_thread, 0, in_bytes(JavaThread::interp_only_mode_offset()));
const Address interp_only(G2_thread, JavaThread::interp_only_mode_offset());
ld(interp_only, temp_reg);
tst(temp_reg);
br(zero, false, pt, L);
......@@ -2489,9 +2469,7 @@ void InterpreterMacroAssembler::notify_method_exit(bool is_native_method,
if (mode == NotifyJVMTI && JvmtiExport::can_post_interpreter_events()) {
Label L;
Register temp_reg = O5;
const Address interp_only (G2_thread, 0, in_bytes(JavaThread::interp_only_mode_offset()));
const Address interp_only(G2_thread, JavaThread::interp_only_mode_offset());
ld(interp_only, temp_reg);
tst(temp_reg);
br(zero, false, pt, L);
......
src/cpu/sparc/vm/interpreterRT_sparc.cpp
浏览文件 @ 326dca6e
/*
* Copyright 1998-2006 Sun Microsystems, Inc. All Rights Reserved.
* Copyright 1998-2009 Sun Microsystems, Inc. All Rights Reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
......@@ -105,7 +105,7 @@ void InterpreterRuntime::SignatureHandlerGenerator::pass_object() {
// the handle for a receiver will never be null
bool do_NULL_check = offset() != 0 || is_static();
Address h_arg = Address(Llocals, 0, Interpreter::local_offset_in_bytes(offset()));
Address h_arg = Address(Llocals, Interpreter::local_offset_in_bytes(offset()));
__ ld_ptr(h_arg, Rtmp1);
#ifdef ASSERT
if (TaggedStackInterpreter) {
......@@ -120,14 +120,14 @@ void InterpreterRuntime::SignatureHandlerGenerator::pass_object() {
}
#endif // ASSERT
if (!do_NULL_check) {
__ add(h_arg, Rtmp2);
__ add(h_arg.base(), h_arg.disp(), Rtmp2);
} else {
if (Rtmp1 == Rtmp2)
__ tst(Rtmp1);
else __ addcc(G0, Rtmp1, Rtmp2); // optimize mov/test pair
Label L;
__ brx(Assembler::notZero, true, Assembler::pt, L);
__ delayed()->add(h_arg, Rtmp2);
__ delayed()->add(h_arg.base(), h_arg.disp(), Rtmp2);
__ bind(L);
}
__ store_ptr_argument(Rtmp2, jni_arg); // this is often a no-op
......@@ -140,10 +140,10 @@ void InterpreterRuntime::SignatureHandlerGenerator::generate(uint64_t fingerprin
iterate(fingerprint);
// return result handler
Address result_handler(Lscratch, Interpreter::result_handler(method()->result_type()));
__ sethi(result_handler);
AddressLiteral result_handler(Interpreter::result_handler(method()->result_type()));
__ sethi(result_handler, Lscratch);
__ retl();
__ delayed()->add(result_handler, result_handler.base());
__ delayed()->add(Lscratch, result_handler.low10(), Lscratch);
__ flush();
}
......
src/cpu/sparc/vm/jniFastGetField_sparc.cpp
浏览文件 @ 326dca6e
/*
* Copyright 2004-2006 Sun Microsystems, Inc. All Rights Reserved.
* Copyright 2004-2009 Sun Microsystems, Inc. All Rights Reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
......@@ -57,10 +57,10 @@ address JNI_FastGetField::generate_fast_get_int_field0(BasicType type) {
Label label1, label2;
address cnt_addr = SafepointSynchronize::safepoint_counter_addr();
Address ca(O3, cnt_addr);
__ sethi (ca);
__ ld (ca, G4);
AddressLiteral cnt_addrlit(SafepointSynchronize::safepoint_counter_addr());
__ sethi (cnt_addrlit, O3);
Address cnt_addr(O3, cnt_addrlit.low10());
__ ld (cnt_addr, G4);
__ andcc (G4, 1, G0);
__ br (Assembler::notZero, false, Assembler::pn, label1);
__ delayed()->srl (O2, 2, O4);
......@@ -77,7 +77,7 @@ address JNI_FastGetField::generate_fast_get_int_field0(BasicType type) {
default: ShouldNotReachHere();
}
__ ld (ca, O5);
__ ld (cnt_addr, O5);
__ cmp (O5, G4);
__ br (Assembler::notEqual, false, Assembler::pn, label2);
__ delayed()->mov (O7, G1);
......@@ -136,10 +136,10 @@ address JNI_FastGetField::generate_fast_get_long_field() {
Label label1, label2;
address cnt_addr = SafepointSynchronize::safepoint_counter_addr();
Address ca(G3, cnt_addr);
__ sethi (ca);
__ ld (ca, G4);
AddressLiteral cnt_addrlit(SafepointSynchronize::safepoint_counter_addr());
__ sethi (cnt_addrlit, G3);
Address cnt_addr(G3, cnt_addrlit.low10());
__ ld (cnt_addr, G4);
__ andcc (G4, 1, G0);
__ br (Assembler::notZero, false, Assembler::pn, label1);
__ delayed()->srl (O2, 2, O4);
......@@ -159,7 +159,7 @@ address JNI_FastGetField::generate_fast_get_long_field() {
__ ldx (O5, 0, O3);
#endif
__ ld (ca, G1);
__ ld (cnt_addr, G1);
__ cmp (G1, G4);
__ br (Assembler::notEqual, false, Assembler::pn, label2);
__ delayed()->mov (O7, G1);
......@@ -208,10 +208,10 @@ address JNI_FastGetField::generate_fast_get_float_field0(BasicType type) {
Label label1, label2;
address cnt_addr = SafepointSynchronize::safepoint_counter_addr();
Address ca(O3, cnt_addr);
__ sethi (ca);
__ ld (ca, G4);
AddressLiteral cnt_addrlit(SafepointSynchronize::safepoint_counter_addr());
__ sethi (cnt_addrlit, O3);
Address cnt_addr(O3, cnt_addrlit.low10());
__ ld (cnt_addr, G4);
__ andcc (G4, 1, G0);
__ br (Assembler::notZero, false, Assembler::pn, label1);
__ delayed()->srl (O2, 2, O4);
......@@ -225,7 +225,7 @@ address JNI_FastGetField::generate_fast_get_float_field0(BasicType type) {
default: ShouldNotReachHere();
}
__ ld (ca, O5);
__ ld (cnt_addr, O5);
__ cmp (O5, G4);
__ br (Assembler::notEqual, false, Assembler::pn, label2);
__ delayed()->mov (O7, G1);
......
src/cpu/sparc/vm/nativeInst_sparc.cpp
浏览文件 @ 326dca6e
/*
* Copyright 1997-2008 Sun Microsystems, Inc. All Rights Reserved.
* Copyright 1997-2009 Sun Microsystems, Inc. All Rights Reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
......@@ -38,8 +38,7 @@ void NativeInstruction::set_data64_sethi(address instaddr, intptr_t x) {
destreg = inv_rd(*(unsigned int *)instaddr);
// Generate a the new sequence
Address dest( destreg, (address)x );
_masm->sethi( dest, true );
_masm->patchable_sethi(x, destreg);
ICache::invalidate_range(instaddr, 7 * BytesPerInstWord);
}
......@@ -227,8 +226,8 @@ void NativeFarCall::set_destination(address dest) {
CodeBuffer buf(addr_at(0), instruction_size + 1);
MacroAssembler* _masm = new MacroAssembler(&buf);
// Generate the new sequence
Address(O7, dest);
_masm->jumpl_to(dest, O7);
AddressLiteral(dest);
_masm->jumpl_to(dest, O7, O7);
ICache::invalidate_range(addr_at(0), instruction_size );
#endif
}
......@@ -361,10 +360,12 @@ void NativeMovConstReg::test() {
VM_Version::allow_all();
a->sethi(0xaaaabbbb, I3, true, RelocationHolder::none);
a->add(I3, low10(0xaaaabbbb), I3);
a->sethi(0xccccdddd, O2, true, RelocationHolder::none);
a->add(O2, low10(0xccccdddd), O2);
AddressLiteral al1(0xaaaabbbb, relocInfo::external_word_type);
a->sethi(al1, I3);
a->add(I3, al1.low10(), I3);
AddressLiteral al2(0xccccdddd, relocInfo::external_word_type);
a->sethi(al2, O2);
a->add(O2, al2.low10(), O2);
nm = nativeMovConstReg_at( cb.code_begin() );
nm->print();
......@@ -468,12 +469,14 @@ void NativeMovConstRegPatching::test() {
VM_Version::allow_all();
a->sethi(0xaaaabbbb, I3, true, RelocationHolder::none);
AddressLiteral al1(0xaaaabbbb, relocInfo::external_word_type);
a->sethi(al1, I3);
a->nop();
a->add(I3, low10(0xaaaabbbb), I3);
a->sethi(0xccccdddd, O2, true, RelocationHolder::none);
a->add(I3, al1.low10(), I3);
AddressLiteral al2(0xccccdddd, relocInfo::external_word_type);
a->sethi(al2, O2);
a->nop();
a->add(O2, low10(0xccccdddd), O2);
a->add(O2, al2.low10(), O2);
nm = nativeMovConstRegPatching_at( cb.code_begin() );
nm->print();
......@@ -562,51 +565,53 @@ void NativeMovRegMem::test() {
VM_Version::allow_all();
a->ldsw( G5, low10(0xffffffff), G4 ); idx++;
a->sethi(0xaaaabbbb, I3, true, RelocationHolder::none); a->add(I3, low10(0xaaaabbbb), I3);
AddressLiteral al1(0xffffffff, relocInfo::external_word_type);
AddressLiteral al2(0xaaaabbbb, relocInfo::external_word_type);
a->ldsw( G5, al1.low10(), G4 ); idx++;
a->sethi(al2, I3); a->add(I3, al2.low10(), I3);
a->ldsw( G5, I3, G4 ); idx++;
a->ldsb( G5, low10(0xffffffff), G4 ); idx++;
a->sethi(0xaaaabbbb, I3, true, RelocationHolder::none); a->add(I3, low10(0xaaaabbbb), I3);
a->ldsb( G5, al1.low10(), G4 ); idx++;
a->sethi(al2, I3); a->add(I3, al2.low10(), I3);
a->ldsb( G5, I3, G4 ); idx++;
a->ldsh( G5, low10(0xffffffff), G4 ); idx++;
a->sethi(0xaaaabbbb, I3, true, RelocationHolder::none); a->add(I3, low10(0xaaaabbbb), I3);
a->ldsh( G5, al1.low10(), G4 ); idx++;
a->sethi(al2, I3); a->add(I3, al2.low10(), I3);
a->ldsh( G5, I3, G4 ); idx++;
a->lduw( G5, low10(0xffffffff), G4 ); idx++;
a->sethi(0xaaaabbbb, I3, true, RelocationHolder::none); a->add(I3, low10(0xaaaabbbb), I3);
a->lduw( G5, al1.low10(), G4 ); idx++;
a->sethi(al2, I3); a->add(I3, al2.low10(), I3);
a->lduw( G5, I3, G4 ); idx++;
a->ldub( G5, low10(0xffffffff), G4 ); idx++;
a->sethi(0xaaaabbbb, I3, true, RelocationHolder::none); a->add(I3, low10(0xaaaabbbb), I3);
a->ldub( G5, al1.low10(), G4 ); idx++;
a->sethi(al2, I3); a->add(I3, al2.low10(), I3);
a->ldub( G5, I3, G4 ); idx++;
a->lduh( G5, low10(0xffffffff), G4 ); idx++;
a->sethi(0xaaaabbbb, I3, true, RelocationHolder::none); a->add(I3, low10(0xaaaabbbb), I3);
a->lduh( G5, al1.low10(), G4 ); idx++;
a->sethi(al2, I3); a->add(I3, al2.low10(), I3);
a->lduh( G5, I3, G4 ); idx++;
a->ldx( G5, low10(0xffffffff), G4 ); idx++;
a->sethi(0xaaaabbbb, I3, true, RelocationHolder::none); a->add(I3, low10(0xaaaabbbb), I3);
a->ldx( G5, al1.low10(), G4 ); idx++;
a->sethi(al2, I3); a->add(I3, al2.low10(), I3);
a->ldx( G5, I3, G4 ); idx++;
a->ldd( G5, low10(0xffffffff), G4 ); idx++;
a->sethi(0xaaaabbbb, I3, true, RelocationHolder::none); a->add(I3, low10(0xaaaabbbb), I3);
a->ldd( G5, al1.low10(), G4 ); idx++;
a->sethi(al2, I3); a->add(I3, al2.low10(), I3);
a->ldd( G5, I3, G4 ); idx++;
a->ldf( FloatRegisterImpl::D, O2, -1, F14 ); idx++;
a->sethi(0xaaaabbbb, I3, true, RelocationHolder::none); a->add(I3, low10(0xaaaabbbb), I3);
a->sethi(al2, I3); a->add(I3, al2.low10(), I3);
a->ldf( FloatRegisterImpl::S, O0, I3, F15 ); idx++;
a->stw( G5, G4, low10(0xffffffff) ); idx++;
a->sethi(0xaaaabbbb, I3, true, RelocationHolder::none); a->add(I3, low10(0xaaaabbbb), I3);
a->stw( G5, G4, al1.low10() ); idx++;
a->sethi(al2, I3); a->add(I3, al2.low10(), I3);
a->stw( G5, G4, I3 ); idx++;
a->stb( G5, G4, low10(0xffffffff) ); idx++;
a->sethi(0xaaaabbbb, I3, true, RelocationHolder::none); a->add(I3, low10(0xaaaabbbb), I3);
a->stb( G5, G4, al1.low10() ); idx++;
a->sethi(al2, I3); a->add(I3, al2.low10(), I3);
a->stb( G5, G4, I3 ); idx++;
a->sth( G5, G4, low10(0xffffffff) ); idx++;
a->sethi(0xaaaabbbb, I3, true, RelocationHolder::none); a->add(I3, low10(0xaaaabbbb), I3);
a->sth( G5, G4, al1.low10() ); idx++;
a->sethi(al2, I3); a->add(I3, al2.low10(), I3);
a->sth( G5, G4, I3 ); idx++;
a->stx( G5, G4, low10(0xffffffff) ); idx++;
a->sethi(0xaaaabbbb, I3, true, RelocationHolder::none); a->add(I3, low10(0xaaaabbbb), I3);
a->stx( G5, G4, al1.low10() ); idx++;
a->sethi(al2, I3); a->add(I3, al2.low10(), I3);
a->stx( G5, G4, I3 ); idx++;
a->std( G5, G4, low10(0xffffffff) ); idx++;
a->sethi(0xaaaabbbb, I3, true, RelocationHolder::none); a->add(I3, low10(0xaaaabbbb), I3);
a->std( G5, G4, al1.low10() ); idx++;
a->sethi(al2, I3); a->add(I3, al2.low10(), I3);
a->std( G5, G4, I3 ); idx++;
a->stf( FloatRegisterImpl::S, F18, O2, -1 ); idx++;
a->sethi(0xaaaabbbb, I3, true, RelocationHolder::none); a->add(I3, low10(0xaaaabbbb), I3);
a->sethi(al2, I3); a->add(I3, al2.low10(), I3);
a->stf( FloatRegisterImpl::S, F15, O0, I3 ); idx++;
nm = nativeMovRegMem_at( cb.code_begin() );
......@@ -705,51 +710,52 @@ void NativeMovRegMemPatching::test() {
VM_Version::allow_all();
a->ldsw( G5, low10(0xffffffff), G4 ); idx++;
a->sethi(0xaaaabbbb, I3, true, RelocationHolder::none); a->nop(); a->add(I3, low10(0xaaaabbbb), I3);
AddressLiteral al(0xffffffff, relocInfo::external_word_type);
a->ldsw( G5, al.low10(), G4); idx++;
a->sethi(al, I3); a->nop(); a->add(I3, al.low10(), I3);
a->ldsw( G5, I3, G4 ); idx++;
a->ldsb( G5, low10(0xffffffff), G4 ); idx++;
a->sethi(0xaaaabbbb, I3, true, RelocationHolder::none); a->nop(); a->add(I3, low10(0xaaaabbbb), I3);
a->ldsb( G5, al.low10(), G4); idx++;
a->sethi(al, I3); a->nop(); a->add(I3, al.low10(), I3);
a->ldsb( G5, I3, G4 ); idx++;
a->ldsh( G5, low10(0xffffffff), G4 ); idx++;
a->sethi(0xaaaabbbb, I3, true, RelocationHolder::none); a->nop(); a->add(I3, low10(0xaaaabbbb), I3);
a->ldsh( G5, al.low10(), G4); idx++;
a->sethi(al, I3); a->nop(); a->add(I3, al.low10(), I3);
a->ldsh( G5, I3, G4 ); idx++;
a->lduw( G5, low10(0xffffffff), G4 ); idx++;
a->sethi(0xaaaabbbb, I3, true, RelocationHolder::none); a->nop(); a->add(I3, low10(0xaaaabbbb), I3);
a->lduw( G5, al.low10(), G4); idx++;
a->sethi(al, I3); a->nop(); a->add(I3, al.low10(), I3);
a->lduw( G5, I3, G4 ); idx++;
a->ldub( G5, low10(0xffffffff), G4 ); idx++;
a->sethi(0xaaaabbbb, I3, true, RelocationHolder::none); a->nop(); a->add(I3, low10(0xaaaabbbb), I3);
a->ldub( G5, al.low10(), G4); idx++;
a->sethi(al, I3); a->nop(); a->add(I3, al.low10(), I3);
a->ldub( G5, I3, G4 ); idx++;
a->lduh( G5, low10(0xffffffff), G4 ); idx++;
a->sethi(0xaaaabbbb, I3, true, RelocationHolder::none); a->nop(); a->add(I3, low10(0xaaaabbbb), I3);
a->lduh( G5, al.low10(), G4); idx++;
a->sethi(al, I3); a->nop(); a->add(I3, al.low10(), I3);
a->lduh( G5, I3, G4 ); idx++;
a->ldx( G5, low10(0xffffffff), G4 ); idx++;
a->sethi(0xaaaabbbb, I3, true, RelocationHolder::none); a->nop(); a->add(I3, low10(0xaaaabbbb), I3);
a->ldx( G5, al.low10(), G4); idx++;
a->sethi(al, I3); a->nop(); a->add(I3, al.low10(), I3);
a->ldx( G5, I3, G4 ); idx++;
a->ldd( G5, low10(0xffffffff), G4 ); idx++;
a->sethi(0xaaaabbbb, I3, true, RelocationHolder::none); a->nop(); a->add(I3, low10(0xaaaabbbb), I3);
a->ldd( G5, al.low10(), G4); idx++;
a->sethi(al, I3); a->nop(); a->add(I3, al.low10(), I3);
a->ldd( G5, I3, G4 ); idx++;
a->ldf( FloatRegisterImpl::D, O2, -1, F14 ); idx++;
a->sethi(0xaaaabbbb, I3, true, RelocationHolder::none); a->nop(); a->add(I3, low10(0xaaaabbbb), I3);
a->sethi(al, I3); a->nop(); a->add(I3, al.low10(), I3);
a->ldf( FloatRegisterImpl::S, O0, I3, F15 ); idx++;
a->stw( G5, G4, low10(0xffffffff) ); idx++;
a->sethi(0xaaaabbbb, I3, true, RelocationHolder::none); a->nop(); a->add(I3, low10(0xaaaabbbb), I3);
a->stw( G5, G4, al.low10()); idx++;
a->sethi(al, I3); a->nop(); a->add(I3, al.low10(), I3);
a->stw( G5, G4, I3 ); idx++;
a->stb( G5, G4, low10(0xffffffff) ); idx++;
a->sethi(0xaaaabbbb, I3, true, RelocationHolder::none); a->nop(); a->add(I3, low10(0xaaaabbbb), I3);
a->stb( G5, G4, al.low10()); idx++;
a->sethi(al, I3); a->nop(); a->add(I3, al.low10(), I3);
a->stb( G5, G4, I3 ); idx++;
a->sth( G5, G4, low10(0xffffffff) ); idx++;
a->sethi(0xaaaabbbb, I3, true, RelocationHolder::none); a->nop(); a->add(I3, low10(0xaaaabbbb), I3);
a->sth( G5, G4, al.low10()); idx++;
a->sethi(al, I3); a->nop(); a->add(I3, al.low10(), I3);
a->sth( G5, G4, I3 ); idx++;
a->stx( G5, G4, low10(0xffffffff) ); idx++;
a->sethi(0xaaaabbbb, I3, true, RelocationHolder::none); a->nop(); a->add(I3, low10(0xaaaabbbb), I3);
a->stx( G5, G4, al.low10()); idx++;
a->sethi(al, I3); a->nop(); a->add(I3, al.low10(), I3);
a->stx( G5, G4, I3 ); idx++;
a->std( G5, G4, low10(0xffffffff) ); idx++;
a->sethi(0xaaaabbbb, I3, true, RelocationHolder::none); a->nop(); a->add(I3, low10(0xaaaabbbb), I3);
a->std( G5, G4, al.low10()); idx++;
a->sethi(al, I3); a->nop(); a->add(I3, al.low10(), I3);
a->std( G5, G4, I3 ); idx++;
a->stf( FloatRegisterImpl::S, F18, O2, -1 ); idx++;
a->sethi(0xaaaabbbb, I3, true, RelocationHolder::none); a->nop(); a->add(I3, low10(0xaaaabbbb), I3);
a->sethi(al, I3); a->nop(); a->add(I3, al.low10(), I3);
a->stf( FloatRegisterImpl::S, F15, O0, I3 ); idx++;
nm = nativeMovRegMemPatching_at( cb.code_begin() );
......@@ -833,11 +839,12 @@ void NativeJump::test() {
VM_Version::allow_all();
a->sethi(0x7fffbbbb, I3, true, RelocationHolder::none);
a->jmpl(I3, low10(0x7fffbbbb), G0, RelocationHolder::none);
AddressLiteral al(0x7fffbbbb, relocInfo::external_word_type);
a->sethi(al, I3);
a->jmpl(I3, al.low10(), G0, RelocationHolder::none);
a->delayed()->nop();
a->sethi(0x7fffbbbb, I3, true, RelocationHolder::none);
a->jmpl(I3, low10(0x7fffbbbb), L3, RelocationHolder::none);
a->sethi(al, I3);
a->jmpl(I3, al.low10(), L3, RelocationHolder::none);
a->delayed()->nop();
nj = nativeJump_at( cb.code_begin() );
......
src/cpu/sparc/vm/relocInfo_sparc.cpp
浏览文件 @ 326dca6e
/*
* Copyright 1998-2008 Sun Microsystems, Inc. All Rights Reserved.
* Copyright 1998-2009 Sun Microsystems, Inc. All Rights Reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
......@@ -99,13 +99,6 @@ void Relocation::pd_set_data_value(address x, intptr_t o) {
break;
}
ip->set_data64_sethi( ip->addr_at(0), (intptr_t)x );
#ifdef COMPILER2
// [RGV] Someone must have missed putting in a reloc entry for the
// add in compiler2.
inst2 = ip->long_at( NativeMovConstReg::add_offset );
guarantee(Assembler::inv_op(inst2)==Assembler::arith_op, "arith op");
ip->set_long_at(NativeMovConstReg::add_offset,ip->set_data32_simm13( inst2, (intptr_t)x+o));
#endif
#else
guarantee(Assembler::inv_op2(inst)==Assembler::sethi_op2, "must be sethi");
inst &= ~Assembler::hi22( -1);
......
src/cpu/sparc/vm/runtime_sparc.cpp
浏览文件 @ 326dca6e
/*
* Copyright 1998-2006 Sun Microsystems, Inc. All Rights Reserved.
* Copyright 1998-2009 Sun Microsystems, Inc. All Rights Reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
......@@ -74,8 +74,8 @@ void OptoRuntime::generate_exception_blob() {
int start = __ offset();
__ verify_thread();
__ st_ptr(Oexception, Address(G2_thread, 0, in_bytes(JavaThread::exception_oop_offset())));
__ st_ptr(Oissuing_pc, Address(G2_thread, 0, in_bytes(JavaThread::exception_pc_offset())));
__ st_ptr(Oexception, G2_thread, JavaThread::exception_oop_offset());
__ st_ptr(Oissuing_pc, G2_thread, JavaThread::exception_pc_offset());
// This call does all the hard work. It checks if an exception catch
// exists in the method.
......@@ -120,19 +120,19 @@ void OptoRuntime::generate_exception_blob() {
// Since this may be the deopt blob we must set O7 to look like we returned
// from the original pc that threw the exception
__ ld_ptr(Address(G2_thread, 0, in_bytes(JavaThread::exception_pc_offset())), O7);
__ ld_ptr(G2_thread, JavaThread::exception_pc_offset(), O7);
__ sub(O7, frame::pc_return_offset, O7);
assert(Assembler::is_simm13(in_bytes(JavaThread::exception_oop_offset())), "exception offset overflows simm13, following ld instruction cannot be in delay slot");
__ ld_ptr(Address(G2_thread, 0, in_bytes(JavaThread::exception_oop_offset())), Oexception); // O0
__ ld_ptr(G2_thread, JavaThread::exception_oop_offset(), Oexception); // O0
#ifdef ASSERT
__ st_ptr(G0, Address(G2_thread, 0, in_bytes(JavaThread::exception_handler_pc_offset())));
__ st_ptr(G0, Address(G2_thread, 0, in_bytes(JavaThread::exception_pc_offset())));
__ st_ptr(G0, G2_thread, JavaThread::exception_handler_pc_offset());
__ st_ptr(G0, G2_thread, JavaThread::exception_pc_offset());
#endif
__ JMP(G3_scratch, 0);
// Clear the exception oop so GC no longer processes it as a root.
__ delayed()->st_ptr(G0, Address(G2_thread, 0, in_bytes(JavaThread::exception_oop_offset())));
__ delayed()->st_ptr(G0, G2_thread, JavaThread::exception_oop_offset());
// -------------
// make sure all code is generated
......
src/cpu/sparc/vm/sharedRuntime_sparc.cpp
浏览文件 @ 326dca6e
......@@ -625,9 +625,9 @@ void AdapterGenerator::patch_callers_callsite() {
__ mov(I7, O1); // VM needs caller's callsite
// Must be a leaf call...
// can be very far once the blob has been relocated
Address dest(O7, CAST_FROM_FN_PTR(address, SharedRuntime::fixup_callers_callsite));
AddressLiteral dest(CAST_FROM_FN_PTR(address, SharedRuntime::fixup_callers_callsite));
__ relocate(relocInfo::runtime_call_type);
__ jumpl_to(dest, O7);
__ jumpl_to(dest, O7, O7);
__ delayed()->mov(G2_thread, L7_thread_cache);
__ mov(L7_thread_cache, G2_thread);
__ mov(L1, G1);
......@@ -1152,7 +1152,7 @@ void AdapterGenerator::gen_i2c_adapter(
#ifndef _LP64
if (g3_crushed) {
// Rats load was wasted, at least it is in cache...
__ ld_ptr(G5_method, in_bytes(methodOopDesc::from_compiled_offset()), G3);
__ ld_ptr(G5_method, methodOopDesc::from_compiled_offset(), G3);
}
#endif /* _LP64 */
......@@ -1165,7 +1165,7 @@ void AdapterGenerator::gen_i2c_adapter(
// we try and find the callee by normal means a safepoint
// is possible. So we stash the desired callee in the thread
// and the vm will find there should this case occur.
Address callee_target_addr(G2_thread, 0, in_bytes(JavaThread::callee_target_offset()));
Address callee_target_addr(G2_thread, JavaThread::callee_target_offset());
__ st_ptr(G5_method, callee_target_addr);
if (StressNonEntrant) {
......@@ -1218,7 +1218,7 @@ AdapterHandlerEntry* SharedRuntime::generate_i2c2i_adapters(MacroAssembler *masm
Register R_temp = G1; // another scratch register
#endif
Address ic_miss(G3_scratch, SharedRuntime::get_ic_miss_stub());
AddressLiteral ic_miss(SharedRuntime::get_ic_miss_stub());
__ verify_oop(O0);
__ verify_oop(G5_method);
......@@ -1240,7 +1240,7 @@ AdapterHandlerEntry* SharedRuntime::generate_i2c2i_adapters(MacroAssembler *masm
Label ok, ok2;
__ brx(Assembler::equal, false, Assembler::pt, ok);
__ delayed()->ld_ptr(G5_method, compiledICHolderOopDesc::holder_method_offset(), G5_method);
__ jump_to(ic_miss);
__ jump_to(ic_miss, G3_scratch);
__ delayed()->nop();
__ bind(ok);
......@@ -1251,7 +1251,7 @@ AdapterHandlerEntry* SharedRuntime::generate_i2c2i_adapters(MacroAssembler *masm
__ bind(ok2);
__ br_null(G3_scratch, false, __ pt, skip_fixup);
__ delayed()->ld_ptr(G5_method, in_bytes(methodOopDesc::interpreter_entry_offset()), G3_scratch);
__ jump_to(ic_miss);
__ jump_to(ic_miss, G3_scratch);
__ delayed()->nop();
}
......@@ -1444,8 +1444,8 @@ static void check_forward_pending_exception(MacroAssembler *masm, Register Rex_o
// without calling into the VM: it's the empty function. Just pop this
// frame and then jump to forward_exception_entry; O7 will contain the
// native caller's return PC.
Address exception_entry(G3_scratch, StubRoutines::forward_exception_entry());
__ jump_to(exception_entry);
AddressLiteral exception_entry(StubRoutines::forward_exception_entry());
__ jump_to(exception_entry, G3_scratch);
__ delayed()->restore(); // Pop this frame off.
__ bind(L);
}
......@@ -1822,14 +1822,14 @@ nmethod *SharedRuntime::generate_native_wrapper(MacroAssembler* masm,
{
Label L;
const Register temp_reg = G3_scratch;
Address ic_miss(temp_reg, SharedRuntime::get_ic_miss_stub());
AddressLiteral ic_miss(SharedRuntime::get_ic_miss_stub());
__ verify_oop(O0);
__ load_klass(O0, temp_reg);
__ cmp(temp_reg, G5_inline_cache_reg);
__ brx(Assembler::equal, true, Assembler::pt, L);
__ delayed()->nop();
__ jump_to(ic_miss, 0);
__ jump_to(ic_miss, temp_reg);
__ delayed()->nop();
__ align(CodeEntryAlignment);
__ bind(L);
......@@ -2261,21 +2261,19 @@ nmethod *SharedRuntime::generate_native_wrapper(MacroAssembler* masm,
// Transition from _thread_in_Java to _thread_in_native.
__ set(_thread_in_native, G3_scratch);
__ st(G3_scratch, G2_thread, in_bytes(JavaThread::thread_state_offset()));
__ st(G3_scratch, G2_thread, JavaThread::thread_state_offset());
// We flushed the windows ages ago now mark them as flushed
// mark windows as flushed
__ set(JavaFrameAnchor::flushed, G3_scratch);
Address flags(G2_thread,
0,
in_bytes(JavaThread::frame_anchor_offset()) + in_bytes(JavaFrameAnchor::flags_offset()));
Address flags(G2_thread, JavaThread::frame_anchor_offset() + JavaFrameAnchor::flags_offset());
#ifdef _LP64
Address dest(O7, method->native_function());
AddressLiteral dest(method->native_function());
__ relocate(relocInfo::runtime_call_type);
__ jumpl_to(dest, O7);
__ jumpl_to(dest, O7, O7);
#else
__ call(method->native_function(), relocInfo::runtime_call_type);
#endif
......@@ -2316,7 +2314,7 @@ nmethod *SharedRuntime::generate_native_wrapper(MacroAssembler* masm,
// Block, if necessary, before resuming in _thread_in_Java state.
// In order for GC to work, don't clear the last_Java_sp until after blocking.
{ Label no_block;
Address sync_state(G3_scratch, SafepointSynchronize::address_of_state());
AddressLiteral sync_state(SafepointSynchronize::address_of_state());
// Switch thread to "native transition" state before reading the synchronization state.
// This additional state is necessary because reading and testing the synchronization
......@@ -2326,7 +2324,7 @@ nmethod *SharedRuntime::generate_native_wrapper(MacroAssembler* masm,
// Thread A is resumed to finish this native method, but doesn't block here since it
// didn't see any synchronization is progress, and escapes.
__ set(_thread_in_native_trans, G3_scratch);
__ st(G3_scratch, G2_thread, in_bytes(JavaThread::thread_state_offset()));
__ st(G3_scratch, G2_thread, JavaThread::thread_state_offset());
if(os::is_MP()) {
if (UseMembar) {
// Force this write out before the read below
......@@ -2343,10 +2341,9 @@ nmethod *SharedRuntime::generate_native_wrapper(MacroAssembler* masm,
__ cmp(G3_scratch, SafepointSynchronize::_not_synchronized);
Label L;
Address suspend_state(G2_thread, 0, in_bytes(JavaThread::suspend_flags_offset()));
Address suspend_state(G2_thread, JavaThread::suspend_flags_offset());
__ br(Assembler::notEqual, false, Assembler::pn, L);
__ delayed()->
ld(suspend_state, G3_scratch);
__ delayed()->ld(suspend_state, G3_scratch);
__ cmp(G3_scratch, 0);
__ br(Assembler::equal, false, Assembler::pt, no_block);
__ delayed()->nop();
......@@ -2372,11 +2369,11 @@ nmethod *SharedRuntime::generate_native_wrapper(MacroAssembler* masm,
__ set(_thread_in_Java, G3_scratch);
__ st(G3_scratch, G2_thread, in_bytes(JavaThread::thread_state_offset()));
__ st(G3_scratch, G2_thread, JavaThread::thread_state_offset());
Label no_reguard;
__ ld(G2_thread, in_bytes(JavaThread::stack_guard_state_offset()), G3_scratch);
__ ld(G2_thread, JavaThread::stack_guard_state_offset(), G3_scratch);
__ cmp(G3_scratch, JavaThread::stack_guard_yellow_disabled);
__ br(Assembler::notEqual, false, Assembler::pt, no_reguard);
__ delayed()->nop();
......@@ -2684,14 +2681,14 @@ nmethod *SharedRuntime::generate_dtrace_nmethod(
{
Label L;
const Register temp_reg = G3_scratch;
Address ic_miss(temp_reg, SharedRuntime::get_ic_miss_stub());
AddressLiteral ic_miss(SharedRuntime::get_ic_miss_stub());
__ verify_oop(O0);
__ ld_ptr(O0, oopDesc::klass_offset_in_bytes(), temp_reg);
__ cmp(temp_reg, G5_inline_cache_reg);
__ brx(Assembler::equal, true, Assembler::pt, L);
__ delayed()->nop();
__ jump_to(ic_miss, 0);
__ jump_to(ic_miss, temp_reg);
__ delayed()->nop();
__ align(CodeEntryAlignment);
__ bind(L);
......@@ -3155,15 +3152,13 @@ static void make_new_frames(MacroAssembler* masm, bool deopt) {
// Do this after the caller's return address is on top of stack
if (UseStackBanging) {
// Get total frame size for interpreted frames
__ ld(Address(O2UnrollBlock, 0,
Deoptimization::UnrollBlock::total_frame_sizes_offset_in_bytes()), O4);
__ ld(O2UnrollBlock, Deoptimization::UnrollBlock::total_frame_sizes_offset_in_bytes(), O4);
__ bang_stack_size(O4, O3, G3_scratch);
}
__ ld(Address(O2UnrollBlock, 0, Deoptimization::UnrollBlock::number_of_frames_offset_in_bytes()), O4array_size);
__ ld_ptr(Address(O2UnrollBlock, 0, Deoptimization::UnrollBlock::frame_pcs_offset_in_bytes()), G3pcs);
__ ld_ptr(Address(O2UnrollBlock, 0, Deoptimization::UnrollBlock::frame_sizes_offset_in_bytes()), O3array);
__ ld(O2UnrollBlock, Deoptimization::UnrollBlock::number_of_frames_offset_in_bytes(), O4array_size);
__ ld_ptr(O2UnrollBlock, Deoptimization::UnrollBlock::frame_pcs_offset_in_bytes(), G3pcs);
__ ld_ptr(O2UnrollBlock, Deoptimization::UnrollBlock::frame_sizes_offset_in_bytes(), O3array);
// Adjust old interpreter frame to make space for new frame's extra java locals
//
......@@ -3176,7 +3171,7 @@ static void make_new_frames(MacroAssembler* masm, bool deopt) {
// for each frame we create and keep up the illusion every where.
//
__ ld(Address(O2UnrollBlock, 0, Deoptimization::UnrollBlock::caller_adjustment_offset_in_bytes()), O7);
__ ld(O2UnrollBlock, Deoptimization::UnrollBlock::caller_adjustment_offset_in_bytes(), O7);
__ mov(SP, O5_savedSP); // remember initial sender's original sp before adjustment
__ sub(SP, O7, SP);
......@@ -3225,9 +3220,9 @@ void SharedRuntime::generate_deopt_blob() {
Register I5exception_tmp = I5;
Register G4exception_tmp = G4_scratch;
int frame_size_words;
Address saved_Freturn0_addr(FP, 0, -sizeof(double) + STACK_BIAS);
Address saved_Freturn0_addr(FP, -sizeof(double) + STACK_BIAS);
#if !defined(_LP64) && defined(COMPILER2)
Address saved_Greturn1_addr(FP, 0, -sizeof(double) -sizeof(jlong) + STACK_BIAS);
Address saved_Greturn1_addr(FP, -sizeof(double) -sizeof(jlong) + STACK_BIAS);
#endif
Label cont;
......@@ -3289,7 +3284,7 @@ void SharedRuntime::generate_deopt_blob() {
// save exception oop in JavaThread and fall through into the
// exception_in_tls case since they are handled in same way except
// for where the pending exception is kept.
__ st_ptr(Oexception, G2_thread, in_bytes(JavaThread::exception_oop_offset()));
__ st_ptr(Oexception, G2_thread, JavaThread::exception_oop_offset());
//
// Vanilla deoptimization with an exception pending in exception_oop
......@@ -3306,7 +3301,7 @@ void SharedRuntime::generate_deopt_blob() {
{
// verify that there is really an exception oop in exception_oop
Label has_exception;
__ ld_ptr(G2_thread, in_bytes(JavaThread::exception_oop_offset()), Oexception);
__ ld_ptr(G2_thread, JavaThread::exception_oop_offset(), Oexception);
__ br_notnull(Oexception, false, Assembler::pt, has_exception);
__ delayed()-> nop();
__ stop("no exception in thread");
......@@ -3314,7 +3309,7 @@ void SharedRuntime::generate_deopt_blob() {
// verify that there is no pending exception
Label no_pending_exception;
Address exception_addr(G2_thread, 0, in_bytes(Thread::pending_exception_offset()));
Address exception_addr(G2_thread, Thread::pending_exception_offset());
__ ld_ptr(exception_addr, Oexception);
__ br_null(Oexception, false, Assembler::pt, no_pending_exception);
__ delayed()->nop();
......
src/cpu/sparc/vm/sparc.ad
浏览文件 @ 326dca6e
此差异已折叠。
src/cpu/sparc/vm/stubGenerator_sparc.cpp
浏览文件 @ 326dca6e
/*
* Copyright 1997-2008 Sun Microsystems, Inc. All Rights Reserved.
* Copyright 1997-2009 Sun Microsystems, Inc. All Rights Reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
......@@ -68,16 +68,9 @@ class StubGenerator: public StubCodeGenerator {
#ifdef PRODUCT
#define inc_counter_np(a,b,c) (0)
#else
void inc_counter_np_(int& counter, Register t1, Register t2) {
Address counter_addr(t2, (address) &counter);
__ sethi(counter_addr);
__ ld(counter_addr, t1);
__ inc(t1);
__ st(t1, counter_addr);
}
#define inc_counter_np(counter, t1, t2) \
BLOCK_COMMENT("inc_counter " #counter); \
inc_counter_np_(counter, t1, t2);
__ inc_counter(&counter, t1, t2);
#endif
//----------------------------------------------------------------------------------------------------
......@@ -325,9 +318,9 @@ class StubGenerator: public StubCodeGenerator {
__ verify_thread();
const Register& temp_reg = Gtemp;
Address pending_exception_addr (G2_thread, 0, in_bytes(Thread::pending_exception_offset()));
Address exception_file_offset_addr(G2_thread, 0, in_bytes(Thread::exception_file_offset ()));
Address exception_line_offset_addr(G2_thread, 0, in_bytes(Thread::exception_line_offset ()));
Address pending_exception_addr (G2_thread, Thread::pending_exception_offset());
Address exception_file_offset_addr(G2_thread, Thread::exception_file_offset ());
Address exception_line_offset_addr(G2_thread, Thread::exception_line_offset ());
// set pending exception
__ verify_oop(Oexception);
......@@ -340,8 +333,8 @@ class StubGenerator: public StubCodeGenerator {
// complete return to VM
assert(StubRoutines::_call_stub_return_address != NULL, "must have been generated before");
Address stub_ret(temp_reg, StubRoutines::_call_stub_return_address);
__ jump_to(stub_ret);
AddressLiteral stub_ret(StubRoutines::_call_stub_return_address);
__ jump_to(stub_ret, temp_reg);
__ delayed()->nop();
return start;
......@@ -366,7 +359,7 @@ class StubGenerator: public StubCodeGenerator {
const Register& handler_reg = Gtemp;
Address exception_addr (G2_thread, 0, in_bytes(Thread::pending_exception_offset()));
Address exception_addr(G2_thread, Thread::pending_exception_offset());
#ifdef ASSERT
// make sure that this code is only executed if there is a pending exception
......@@ -456,8 +449,7 @@ class StubGenerator: public StubCodeGenerator {
int frame_complete = __ offset();
if (restore_saved_exception_pc) {
Address saved_exception_pc(G2_thread, 0, in_bytes(JavaThread::saved_exception_pc_offset()));
__ ld_ptr(saved_exception_pc, I7);
__ ld_ptr(G2_thread, JavaThread::saved_exception_pc_offset(), I7);
__ sub(I7, frame::pc_return_offset, I7);
}
......@@ -481,7 +473,7 @@ class StubGenerator: public StubCodeGenerator {
#ifdef ASSERT
Label L;
Address exception_addr(G2_thread, 0, in_bytes(Thread::pending_exception_offset()));
Address exception_addr(G2_thread, Thread::pending_exception_offset());
Register scratch_reg = Gtemp;
__ ld_ptr(exception_addr, scratch_reg);
__ br_notnull(scratch_reg, false, Assembler::pt, L);
......@@ -835,7 +827,7 @@ class StubGenerator: public StubCodeGenerator {
address start = __ pc();
const int preserve_register_words = (64 * 2);
Address preserve_addr(FP, 0, (-preserve_register_words * wordSize) + STACK_BIAS);
Address preserve_addr(FP, (-preserve_register_words * wordSize) + STACK_BIAS);
Register Lthread = L7_thread_cache;
int i;
......@@ -1106,21 +1098,19 @@ class StubGenerator: public StubCodeGenerator {
__ srl_ptr(addr, CardTableModRefBS::card_shift, addr);
__ srl_ptr(count, CardTableModRefBS::card_shift, count);
__ sub(count, addr, count);
Address rs(tmp, (address)ct->byte_map_base);
__ load_address(rs);
AddressLiteral rs(ct->byte_map_base);
__ set(rs, tmp);
__ BIND(L_loop);
__ stb(G0, rs.base(), addr);
__ stb(G0, tmp, addr);
__ subcc(count, 1, count);
__ brx(Assembler::greaterEqual, false, Assembler::pt, L_loop);
__ delayed()->add(addr, 1, addr);
}
break;
case BarrierSet::ModRef:
break;
default :
default:
ShouldNotReachHere();
}
}
......
src/cpu/sparc/vm/templateTable_sparc.cpp
浏览文件 @ 326dca6e
/*
* Copyright 1997-2008 Sun Microsystems, Inc. All Rights Reserved.
* Copyright 1997-2009 Sun Microsystems, Inc. All Rights Reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
......@@ -131,7 +131,7 @@ Assembler::Condition ccNot(TemplateTable::Condition cc) {
Address TemplateTable::at_bcp(int offset) {
assert(_desc->uses_bcp(), "inconsistent uses_bcp information");
return Address( Lbcp, 0, offset);
return Address(Lbcp, offset);
}
......@@ -217,9 +217,9 @@ void TemplateTable::fconst(int value) {
case 1: p = &one; break;
case 2: p = &two; break;
}
Address a(G3_scratch, (address)p);
__ sethi(a);
__ ldf(FloatRegisterImpl::S, a, Ftos_f);
AddressLiteral a(p);
__ sethi(a, G3_scratch);
__ ldf(FloatRegisterImpl::S, G3_scratch, a.low10(), Ftos_f);
}
......@@ -232,9 +232,9 @@ void TemplateTable::dconst(int value) {
case 0: p = &zero; break;
case 1: p = &one; break;
}
Address a(G3_scratch, (address)p);
__ sethi(a);
__ ldf(FloatRegisterImpl::D, a, Ftos_d);
AddressLiteral a(p);
__ sethi(a, G3_scratch);
__ ldf(FloatRegisterImpl::D, G3_scratch, a.low10(), Ftos_d);
}
......@@ -1548,7 +1548,7 @@ void TemplateTable::branch(bool is_jsr, bool is_wide) {
// non-JSR normal-branch stuff occurring below.
if( is_jsr ) {
// compute return address as bci in Otos_i
__ ld_ptr(Address(Lmethod, 0, in_bytes(methodOopDesc::const_offset())), G3_scratch);
__ ld_ptr(Lmethod, methodOopDesc::const_offset(), G3_scratch);
__ sub(Lbcp, G3_scratch, G3_scratch);
__ sub(G3_scratch, in_bytes(constMethodOopDesc::codes_offset()) - (is_wide ? 5 : 3), Otos_i);
......@@ -1665,7 +1665,7 @@ void TemplateTable::ret() {
__ profile_ret(vtos, Otos_i, G4_scratch);
__ ld_ptr(Address(Lmethod, 0, in_bytes(methodOopDesc::const_offset())), G3_scratch);
__ ld_ptr(Lmethod, methodOopDesc::const_offset(), G3_scratch);
__ add(G3_scratch, Otos_i, G3_scratch);
__ add(G3_scratch, in_bytes(constMethodOopDesc::codes_offset()), Lbcp);
__ dispatch_next(vtos);
......@@ -1680,7 +1680,7 @@ void TemplateTable::wide_ret() {
__ profile_ret(vtos, Otos_i, G4_scratch);
__ ld_ptr(Address(Lmethod, 0, in_bytes(methodOopDesc::const_offset())), G3_scratch);
__ ld_ptr(Lmethod, methodOopDesc::const_offset(), G3_scratch);
__ add(G3_scratch, Otos_i, G3_scratch);
__ add(G3_scratch, in_bytes(constMethodOopDesc::codes_offset()), Lbcp);
__ dispatch_next(vtos);
......@@ -1968,8 +1968,8 @@ void TemplateTable::resolve_cache_and_index(int byte_no, Register Rcache, Regist
Label resolved;
__ get_cache_and_index_at_bcp(Rcache, index, 1);
__ ld_ptr(Address(Rcache, 0, in_bytes(constantPoolCacheOopDesc::base_offset() +
ConstantPoolCacheEntry::indices_offset())), Lbyte_code);
__ ld_ptr(Rcache, constantPoolCacheOopDesc::base_offset() +
ConstantPoolCacheEntry::indices_offset(), Lbyte_code);
__ srl( Lbyte_code, shift_count, Lbyte_code );
__ and3( Lbyte_code, 0xFF, Lbyte_code );
......@@ -2029,11 +2029,11 @@ void TemplateTable::load_invoke_cp_cache_entry(int byte_no,
resolve_cache_and_index(byte_no, Rcache, Rscratch);
}
__ ld_ptr(Address(Rcache, 0, method_offset), Rmethod);
__ ld_ptr(Rcache, method_offset, Rmethod);
if (Ritable_index != noreg) {
__ ld_ptr(Address(Rcache, 0, index_offset), Ritable_index);
__ ld_ptr(Rcache, index_offset, Ritable_index);
}
__ ld_ptr(Address(Rcache, 0, flags_offset), Rflags);
__ ld_ptr(Rcache, flags_offset, Rflags);
}
// The Rcache register must be set before call
......@@ -2047,13 +2047,10 @@ void TemplateTable::load_field_cp_cache_entry(Register Robj,
ByteSize cp_base_offset = constantPoolCacheOopDesc::base_offset();
__ ld_ptr(Address(Rcache, 0, in_bytes(cp_base_offset +
ConstantPoolCacheEntry::flags_offset())), Rflags);
__ ld_ptr(Address(Rcache, 0, in_bytes(cp_base_offset +
ConstantPoolCacheEntry::f2_offset())), Roffset);
__ ld_ptr(Rcache, cp_base_offset + ConstantPoolCacheEntry::flags_offset(), Rflags);
__ ld_ptr(Rcache, cp_base_offset + ConstantPoolCacheEntry::f2_offset(), Roffset);
if (is_static) {
__ ld_ptr(Address(Rcache, 0, in_bytes(cp_base_offset +
ConstantPoolCacheEntry::f1_offset())), Robj);
__ ld_ptr(Rcache, cp_base_offset + ConstantPoolCacheEntry::f1_offset(), Robj);
}
}
......@@ -2070,9 +2067,7 @@ void TemplateTable::jvmti_post_field_access(Register Rcache,
// the time to call into the VM.
Label Label1;
assert_different_registers(Rcache, index, G1_scratch);
Address get_field_access_count_addr(G1_scratch,
(address)JvmtiExport::get_field_access_count_addr(),
relocInfo::none);
AddressLiteral get_field_access_count_addr(JvmtiExport::get_field_access_count_addr());
__ load_contents(get_field_access_count_addr, G1_scratch);
__ tst(G1_scratch);
__ br(Assembler::zero, false, Assembler::pt, Label1);
......@@ -2293,7 +2288,7 @@ void TemplateTable::fast_accessfield(TosState state) {
__ get_cache_and_index_at_bcp(Rcache, index, 1);
jvmti_post_field_access(Rcache, index, /*is_static*/false, /*has_tos*/true);
__ ld_ptr(Address(Rcache, 0, in_bytes(cp_base_offset + ConstantPoolCacheEntry::f2_offset())), Roffset);
__ ld_ptr(Rcache, cp_base_offset + ConstantPoolCacheEntry::f2_offset(), Roffset);
__ null_check(Otos_i);
__ verify_oop(Otos_i);
......@@ -2304,7 +2299,7 @@ void TemplateTable::fast_accessfield(TosState state) {
Assembler::Membar_mask_bits(Assembler::LoadLoad | Assembler::LoadStore);
if (__ membar_has_effect(membar_bits)) {
// Get volatile flag
__ ld_ptr(Address(Rcache, 0, in_bytes(cp_base_offset + ConstantPoolCacheEntry::f2_offset())), Rflags);
__ ld_ptr(Rcache, cp_base_offset + ConstantPoolCacheEntry::f2_offset(), Rflags);
__ set((1 << ConstantPoolCacheEntry::volatileField), Lscratch);
}
......@@ -2355,7 +2350,7 @@ void TemplateTable::jvmti_post_fast_field_mod() {
// Check to see if a field modification watch has been set before we take
// the time to call into the VM.
Label done;
Address get_field_modification_count_addr(G4_scratch, (address)JvmtiExport::get_field_modification_count_addr(), relocInfo::none);
AddressLiteral get_field_modification_count_addr(JvmtiExport::get_field_modification_count_addr());
__ load_contents(get_field_modification_count_addr, G4_scratch);
__ tst(G4_scratch);
__ br(Assembler::zero, false, Assembler::pt, done);
......@@ -2408,9 +2403,7 @@ void TemplateTable::jvmti_post_field_mod(Register Rcache, Register index, bool i
// the time to call into the VM.
Label Label1;
assert_different_registers(Rcache, index, G1_scratch);
Address get_field_modification_count_addr(G1_scratch,
(address)JvmtiExport::get_field_modification_count_addr(),
relocInfo::none);
AddressLiteral get_field_modification_count_addr(JvmtiExport::get_field_modification_count_addr());
__ load_contents(get_field_modification_count_addr, G1_scratch);
__ tst(G1_scratch);
__ br(Assembler::zero, false, Assembler::pt, Label1);
......@@ -2433,7 +2426,7 @@ void TemplateTable::jvmti_post_field_mod(Register Rcache, Register index, bool i
// the type to determine where the object is.
Label two_word, valsizeknown;
__ ld_ptr(Address(G1_scratch, 0, in_bytes(cp_base_offset + ConstantPoolCacheEntry::flags_offset())), Rflags);
__ ld_ptr(G1_scratch, cp_base_offset + ConstantPoolCacheEntry::flags_offset(), Rflags);
__ mov(Lesp, G4_scratch);
__ srl(Rflags, ConstantPoolCacheEntry::tosBits, Rflags);
// Make sure we don't need to mask Rflags for tosBits after the above shift
......@@ -2689,8 +2682,7 @@ void TemplateTable::fast_storefield(TosState state) {
Label notVolatile, checkVolatile, exit;
if (__ membar_has_effect(read_bits) || __ membar_has_effect(write_bits)) {
__ ld_ptr(Address(Rcache, 0, in_bytes(cp_base_offset +
ConstantPoolCacheEntry::flags_offset())), Rflags);
__ ld_ptr(Rcache, cp_base_offset + ConstantPoolCacheEntry::flags_offset(), Rflags);
__ set((1 << ConstantPoolCacheEntry::volatileField), Lscratch);
__ and3(Rflags, Lscratch, Lscratch);
if (__ membar_has_effect(read_bits)) {
......@@ -2702,8 +2694,7 @@ void TemplateTable::fast_storefield(TosState state) {
}
}
__ ld_ptr(Address(Rcache, 0, in_bytes(cp_base_offset +
ConstantPoolCacheEntry::f2_offset())), Roffset);
__ ld_ptr(Rcache, cp_base_offset + ConstantPoolCacheEntry::f2_offset(), Roffset);
pop_and_check_object(Rclass);
switch (bytecode()) {
......@@ -2755,7 +2746,7 @@ void TemplateTable::fast_xaccess(TosState state) {
// access constant pool cache (is resolved)
__ get_cache_and_index_at_bcp(Rcache, G4_scratch, 2);
__ ld_ptr(Address(Rcache, 0, in_bytes(constantPoolCacheOopDesc::base_offset() + ConstantPoolCacheEntry::f2_offset())), Roffset);
__ ld_ptr(Rcache, constantPoolCacheOopDesc::base_offset() + ConstantPoolCacheEntry::f2_offset(), Roffset);
__ add(Lbcp, 1, Lbcp); // needed to report exception at the correct bcp
__ verify_oop(Rreceiver);
......@@ -2775,7 +2766,7 @@ void TemplateTable::fast_xaccess(TosState state) {
if (__ membar_has_effect(membar_bits)) {
// Get is_volatile value in Rflags and check if membar is needed
__ ld_ptr(Address(Rcache, 0, in_bytes(constantPoolCacheOopDesc::base_offset() + ConstantPoolCacheEntry::flags_offset())), Rflags);
__ ld_ptr(Rcache, constantPoolCacheOopDesc::base_offset() + ConstantPoolCacheEntry::flags_offset(), Rflags);
// Test volatile
Label notVolatile;
......@@ -2853,8 +2844,8 @@ void TemplateTable::invokevirtual(int byte_no) {
__ verify_oop(O0);
// get return address
Address table(Rtemp, (address)Interpreter::return_3_addrs_by_index_table());
__ load_address(table);
AddressLiteral table(Interpreter::return_3_addrs_by_index_table());
__ set(table, Rtemp);
__ srl(Rret, ConstantPoolCacheEntry::tosBits, Rret); // get return type
// Make sure we don't need to mask Rret for tosBits after the above shift
ConstantPoolCacheEntry::verify_tosBits();
......@@ -2886,7 +2877,7 @@ void TemplateTable::invokevfinal_helper(Register Rscratch, Register Rret) {
__ verify_oop(G5_method);
// Load receiver from stack slot
__ lduh(Address(G5_method, 0, in_bytes(methodOopDesc::size_of_parameters_offset())), G4_scratch);
__ lduh(G5_method, in_bytes(methodOopDesc::size_of_parameters_offset()), G4_scratch);
__ load_receiver(G4_scratch, O0);
// receiver NULL check
......@@ -2895,8 +2886,8 @@ void TemplateTable::invokevfinal_helper(Register Rscratch, Register Rret) {
__ profile_final_call(O4);
// get return address
Address table(Rtemp, (address)Interpreter::return_3_addrs_by_index_table());
__ load_address(table);
AddressLiteral table(Interpreter::return_3_addrs_by_index_table());
__ set(table, Rtemp);
__ srl(Rret, ConstantPoolCacheEntry::tosBits, Rret); // get return type
// Make sure we don't need to mask Rret for tosBits after the above shift
ConstantPoolCacheEntry::verify_tosBits();
......@@ -2920,7 +2911,7 @@ void TemplateTable::invokespecial(int byte_no) {
__ verify_oop(G5_method);
__ lduh(Address(G5_method, 0, in_bytes(methodOopDesc::size_of_parameters_offset())), G4_scratch);
__ lduh(G5_method, in_bytes(methodOopDesc::size_of_parameters_offset()), G4_scratch);
__ load_receiver(G4_scratch, O0);
// receiver NULL check
......@@ -2929,8 +2920,8 @@ void TemplateTable::invokespecial(int byte_no) {
__ profile_call(O4);
// get return address
Address table(Rtemp, (address)Interpreter::return_3_addrs_by_index_table());
__ load_address(table);
AddressLiteral table(Interpreter::return_3_addrs_by_index_table());
__ set(table, Rtemp);
__ srl(Rret, ConstantPoolCacheEntry::tosBits, Rret); // get return type
// Make sure we don't need to mask Rret for tosBits after the above shift
ConstantPoolCacheEntry::verify_tosBits();
......@@ -2956,8 +2947,8 @@ void TemplateTable::invokestatic(int byte_no) {
__ profile_call(O4);
// get return address
Address table(Rtemp, (address)Interpreter::return_3_addrs_by_index_table());
__ load_address(table);
AddressLiteral table(Interpreter::return_3_addrs_by_index_table());
__ set(table, Rtemp);
__ srl(Rret, ConstantPoolCacheEntry::tosBits, Rret); // get return type
// Make sure we don't need to mask Rret for tosBits after the above shift
ConstantPoolCacheEntry::verify_tosBits();
......@@ -3021,8 +3012,8 @@ void TemplateTable::invokeinterface(int byte_no) {
__ mov(Rflags, Rret);
// get return address
Address table(Rscratch, (address)Interpreter::return_5_addrs_by_index_table());
__ load_address(table);
AddressLiteral table(Interpreter::return_5_addrs_by_index_table());
__ set(table, Rscratch);
__ srl(Rret, ConstantPoolCacheEntry::tosBits, Rret); // get return type
// Make sure we don't need to mask Rret for tosBits after the above shift
ConstantPoolCacheEntry::verify_tosBits();
......@@ -3059,7 +3050,7 @@ void TemplateTable::invokeinterface(int byte_no) {
Label search;
Register Rtemp = Rflags;
__ ld(Address(RklassOop, 0, instanceKlass::vtable_length_offset() * wordSize), Rtemp);
__ ld(RklassOop, instanceKlass::vtable_length_offset() * wordSize, Rtemp);
if (align_object_offset(1) > 1) {
__ round_to(Rtemp, align_object_offset(1));
}
......@@ -3624,9 +3615,9 @@ void TemplateTable::wide() {
transition(vtos, vtos);
__ ldub(Lbcp, 1, G3_scratch);// get next bc
__ sll(G3_scratch, LogBytesPerWord, G3_scratch);
Address ep(G4_scratch, (address)Interpreter::_wentry_point);
__ load_address(ep);
__ ld_ptr(ep.base(), G3_scratch, G3_scratch);
AddressLiteral ep(Interpreter::_wentry_point);
__ set(ep, G4_scratch);
__ ld_ptr(G4_scratch, G3_scratch, G3_scratch);
__ jmp(G3_scratch, G0);
__ delayed()->nop();
// Note: the Lbcp increment step is part of the individual wide bytecode implementations
......
src/cpu/sparc/vm/vtableStubs_sparc.cpp
浏览文件 @ 326dca6e
/*
* Copyright 1997-2008 Sun Microsystems, Inc. All Rights Reserved.
* Copyright 1997-2009 Sun Microsystems, Inc. All Rights Reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
......@@ -48,11 +48,7 @@ VtableStub* VtableStubs::create_vtable_stub(int vtable_index) {
#ifndef PRODUCT
if (CountCompiledCalls) {
Address ctr(G5, SharedRuntime::nof_megamorphic_calls_addr());
__ sethi(ctr);
__ ld(ctr, G3_scratch);
__ inc(G3_scratch);
__ st(G3_scratch, ctr);
__ inc_counter(SharedRuntime::nof_megamorphic_calls_addr(), G5, G3_scratch);
}
#endif /* PRODUCT */
......@@ -154,11 +150,7 @@ VtableStub* VtableStubs::create_itable_stub(int itable_index) {
#ifndef PRODUCT
if (CountCompiledCalls) {
Address ctr(L0, SharedRuntime::nof_megamorphic_calls_addr());
__ sethi(ctr);
__ ld(ctr, L1);
__ inc(L1);
__ st(L1, ctr);
__ inc_counter(SharedRuntime::nof_megamorphic_calls_addr(), L0, L1);
}
#endif /* PRODUCT */
......@@ -198,8 +190,8 @@ VtableStub* VtableStubs::create_itable_stub(int itable_index) {
__ delayed()->nop();
__ bind(throw_icce);
Address icce(G3_scratch, StubRoutines::throw_IncompatibleClassChangeError_entry());
__ jump_to(icce, 0);
AddressLiteral icce(StubRoutines::throw_IncompatibleClassChangeError_entry());
__ jump_to(icce, G3_scratch);
__ delayed()->restore();
masm->flush();
......
Markdown is supported
0% 或 .
You are about to add 0 people to the discussion. Proceed with caution.
先完成此消息的编辑！
想要评论请 注册 或