diff --git a/src/cpu/sparc/vm/sparc.ad b/src/cpu/sparc/vm/sparc.ad index af2262821e35b0c4d9e3035153bd079d98861db0..b4a94ac240a5381131395e28a3c90f60d1fbf2ba 100644 --- a/src/cpu/sparc/vm/sparc.ad +++ b/src/cpu/sparc/vm/sparc.ad @@ -762,7 +762,7 @@ void emit_form3_mem_reg(CodeBuffer &cbuf, const MachNode* n, int primary, int te case Assembler::stdf_op3: st_op = Op_StoreD; break; case Assembler::ldsb_op3: ld_op = Op_LoadB; break; - case Assembler::lduh_op3: ld_op = Op_LoadC; break; + case Assembler::lduh_op3: ld_op = Op_LoadUS; break; case Assembler::ldsh_op3: ld_op = Op_LoadS; break; case Assembler::ldx_op3: // may become LoadP or stay LoadI case Assembler::ldsw_op3: // may become LoadP or stay LoadI @@ -5316,9 +5316,9 @@ instruct loadUBL(iRegL dst, memory mem, immL_FF bytemask) %{ ins_pipe(iload_mask_mem); %} -// Load Char (16bit UNsigned) into a Long Register -instruct loadUCL(iRegL dst, memory mem, immL_FFFF bytemask) %{ - match(Set dst (AndL (ConvI2L (LoadC mem)) bytemask)); +// Load Unsigned Short/Char (16bit UNsigned) into a Long Register +instruct loadUS2L(iRegL dst, memory mem, immL_FFFF bytemask) %{ + match(Set dst (AndL (ConvI2L (LoadUS mem)) bytemask)); ins_cost(MEMORY_REF_COST); size(4); @@ -5328,9 +5328,9 @@ instruct loadUCL(iRegL dst, memory mem, immL_FFFF bytemask) %{ ins_pipe(iload_mask_mem); %} -// Load Char (16bit unsigned) -instruct loadC(iRegI dst, memory mem) %{ - match(Set dst (LoadC mem)); +// Load Unsigned Short/Char (16bit unsigned) +instruct loadUS(iRegI dst, memory mem) %{ + match(Set dst (LoadUS mem)); ins_cost(MEMORY_REF_COST); size(4); diff --git a/src/cpu/x86/vm/x86_32.ad b/src/cpu/x86/vm/x86_32.ad index 5f6f8724adb29014301d5c5747a58d5328187391..5f53cee46625a2379a18f3eb55e712c27879eeec 100644 --- a/src/cpu/x86/vm/x86_32.ad +++ b/src/cpu/x86/vm/x86_32.ad @@ -6413,9 +6413,9 @@ instruct loadUB(xRegI dst, memory mem, immI_255 bytemask) %{ ins_pipe( ialu_reg_mem ); %} -// Load Char (16bit unsigned) -instruct loadC(eRegI dst, memory mem) %{ - match(Set dst (LoadC mem)); +// Load Unsigned Short/Char (16bit unsigned) +instruct loadUS(eRegI dst, memory mem) %{ + match(Set dst (LoadUS mem)); ins_cost(125); format %{ "MOVZX $dst,$mem" %} diff --git a/src/cpu/x86/vm/x86_64.ad b/src/cpu/x86/vm/x86_64.ad index 9b5621f39030aef78f69f2a0750f0dfa90d5f5d6..e46f6857cdd09484ab56c564e780f29bf370dca2 100644 --- a/src/cpu/x86/vm/x86_64.ad +++ b/src/cpu/x86/vm/x86_64.ad @@ -6096,25 +6096,25 @@ instruct loadS(rRegI dst, memory mem) // ins_pipe(ialu_reg_mem); // %} -// Load Char (16 bit UNsigned) -instruct loadC(rRegI dst, memory mem) +// Load Unsigned Short/Char (16 bit UNsigned) +instruct loadUS(rRegI dst, memory mem) %{ - match(Set dst (LoadC mem)); + match(Set dst (LoadUS mem)); ins_cost(125); - format %{ "movzwl $dst, $mem\t# char" %} + format %{ "movzwl $dst, $mem\t# ushort/char" %} opcode(0x0F, 0xB7); ins_encode(REX_reg_mem(dst, mem), OpcP, OpcS, reg_mem(dst, mem)); ins_pipe(ialu_reg_mem); %} -// Load Char (16 bit UNsigned) into long -// instruct loadC2L(rRegL dst, memory mem) +// Load Unsigned Short/Char (16 bit UNsigned) into long +// instruct loadUS2L(rRegL dst, memory mem) // %{ -// match(Set dst (ConvI2L (LoadC mem))); +// match(Set dst (ConvI2L (LoadUS mem))); // ins_cost(125); -// format %{ "movzwl $dst, $mem\t# char -> long" %} +// format %{ "movzwl $dst, $mem\t# ushort/char -> long" %} // opcode(0x0F, 0xB7); // ins_encode(REX_reg_mem(dst, mem), OpcP, OpcS, reg_mem(dst, mem)); // ins_pipe(ialu_reg_mem); diff --git a/src/share/vm/adlc/forms.cpp b/src/share/vm/adlc/forms.cpp index e2083c6825965592ac7451b321ee3f34840086f9..cfcfd0a36d807d0b8b34d0e9befedd9bd1c46bed 100644 --- a/src/share/vm/adlc/forms.cpp +++ b/src/share/vm/adlc/forms.cpp @@ -248,7 +248,7 @@ Form::DataType Form::ideal_to_Reg_type(const char *name) const { // True if 'opType', an ideal name, loads or stores. Form::DataType Form::is_load_from_memory(const char *opType) const { if( strcmp(opType,"LoadB")==0 ) return Form::idealB; - if( strcmp(opType,"LoadC")==0 ) return Form::idealC; + if( strcmp(opType,"LoadUS")==0 ) return Form::idealC; if( strcmp(opType,"LoadD")==0 ) return Form::idealD; if( strcmp(opType,"LoadD_unaligned")==0 ) return Form::idealD; if( strcmp(opType,"LoadF")==0 ) return Form::idealF; diff --git a/src/share/vm/adlc/formssel.cpp b/src/share/vm/adlc/formssel.cpp index 65b511bcdb1d5a7fd866df7df369efa4efaa91e5..c265c1d04c798342c7ef1dc68a7eb61cdf87e172 100644 --- a/src/share/vm/adlc/formssel.cpp +++ b/src/share/vm/adlc/formssel.cpp @@ -3314,7 +3314,7 @@ int MatchNode::needs_ideal_memory_edge(FormDict &globals) const { "StoreI","StoreL","StoreP","StoreN","StoreD","StoreF" , "StoreB","StoreC","Store" ,"StoreFP", "LoadI" ,"LoadL", "LoadP" ,"LoadN", "LoadD" ,"LoadF" , - "LoadB" ,"LoadC" ,"LoadS" ,"Load" , + "LoadB" ,"LoadUS" ,"LoadS" ,"Load" , "Store4I","Store2I","Store2L","Store2D","Store4F","Store2F","Store16B", "Store8B","Store4B","Store8C","Store4C","Store2C", "Load4I" ,"Load2I" ,"Load2L" ,"Load2D" ,"Load4F" ,"Load2F" ,"Load16B" , diff --git a/src/share/vm/opto/classes.hpp b/src/share/vm/opto/classes.hpp index 14b431200598b0de7542fcd7d8e6a813dae42e09..bbb3e79990e9bd48b825235419e0fe7d5fd89db2 100644 --- a/src/share/vm/opto/classes.hpp +++ b/src/share/vm/opto/classes.hpp @@ -129,7 +129,7 @@ macro(JumpProj) macro(LShiftI) macro(LShiftL) macro(LoadB) -macro(LoadC) +macro(LoadUS) macro(LoadD) macro(LoadD_unaligned) macro(LoadF) diff --git a/src/share/vm/opto/compile.cpp b/src/share/vm/opto/compile.cpp index de05e5fb84a94e141ea73fb55fa7dd7abcea41b4..7c6f751f8ff7faacd1554821314bc827f56a440f 100644 --- a/src/share/vm/opto/compile.cpp +++ b/src/share/vm/opto/compile.cpp @@ -2005,7 +2005,7 @@ static void final_graph_reshaping_impl( Node *n, Final_Reshape_Counts &fpu ) { case Op_StoreP: case Op_StoreN: case Op_LoadB: - case Op_LoadC: + case Op_LoadUS: case Op_LoadI: case Op_LoadKlass: case Op_LoadNKlass: diff --git a/src/share/vm/opto/lcm.cpp b/src/share/vm/opto/lcm.cpp index 341ddb08c14e42981f71c7d51359eca273c59ff2..dcedbd61f83ad8cb411772d58a08171df7d61130 100644 --- a/src/share/vm/opto/lcm.cpp +++ b/src/share/vm/opto/lcm.cpp @@ -107,7 +107,7 @@ void Block::implicit_null_check(PhaseCFG *cfg, Node *proj, Node *val, int allowe was_store = false; switch( mach->ideal_Opcode() ) { case Op_LoadB: - case Op_LoadC: + case Op_LoadUS: case Op_LoadD: case Op_LoadF: case Op_LoadI: diff --git a/src/share/vm/opto/loopnode.cpp b/src/share/vm/opto/loopnode.cpp index 7e375992f1dc7b2393be2e36f66d3fa3ba149038..fba4a350bbb291d82d74581c10b2f72b24406c71 100644 --- a/src/share/vm/opto/loopnode.cpp +++ b/src/share/vm/opto/loopnode.cpp @@ -2654,7 +2654,7 @@ void PhaseIdealLoop::build_loop_late_post( Node *n, const PhaseIdealLoop *verify case Op_ModF: case Op_ModD: case Op_LoadB: // Same with Loads; they can sink - case Op_LoadC: // during loop optimizations. + case Op_LoadUS: // during loop optimizations. case Op_LoadD: case Op_LoadF: case Op_LoadI: diff --git a/src/share/vm/opto/matcher.cpp b/src/share/vm/opto/matcher.cpp index 582cf2740b9df2e081010f50d7f24d4dfd382ff1..e911c065ccd617fd961eb06b72d28b1b89fac2f3 100644 --- a/src/share/vm/opto/matcher.cpp +++ b/src/share/vm/opto/matcher.cpp @@ -1824,7 +1824,7 @@ void Matcher::find_shared( Node *n ) { mem_op = true; break; case Op_LoadB: - case Op_LoadC: + case Op_LoadUS: case Op_LoadD: case Op_LoadF: case Op_LoadI: diff --git a/src/share/vm/opto/memnode.cpp b/src/share/vm/opto/memnode.cpp index 896b11b6d0bf6049e17354d61b379075d6d50d24..296fb15ea4680aa67e8c175c08709ec6933cb79b 100644 --- a/src/share/vm/opto/memnode.cpp +++ b/src/share/vm/opto/memnode.cpp @@ -779,14 +779,14 @@ Node *LoadNode::make( PhaseGVN& gvn, Node *ctl, Node *mem, Node *adr, const Type "use LoadRangeNode instead"); switch (bt) { case T_BOOLEAN: - case T_BYTE: return new (C, 3) LoadBNode(ctl, mem, adr, adr_type, rt->is_int() ); - case T_INT: return new (C, 3) LoadINode(ctl, mem, adr, adr_type, rt->is_int() ); - case T_CHAR: return new (C, 3) LoadCNode(ctl, mem, adr, adr_type, rt->is_int() ); - case T_SHORT: return new (C, 3) LoadSNode(ctl, mem, adr, adr_type, rt->is_int() ); - case T_LONG: return new (C, 3) LoadLNode(ctl, mem, adr, adr_type, rt->is_long() ); - case T_FLOAT: return new (C, 3) LoadFNode(ctl, mem, adr, adr_type, rt ); - case T_DOUBLE: return new (C, 3) LoadDNode(ctl, mem, adr, adr_type, rt ); - case T_ADDRESS: return new (C, 3) LoadPNode(ctl, mem, adr, adr_type, rt->is_ptr() ); + case T_BYTE: return new (C, 3) LoadBNode (ctl, mem, adr, adr_type, rt->is_int() ); + case T_INT: return new (C, 3) LoadINode (ctl, mem, adr, adr_type, rt->is_int() ); + case T_CHAR: return new (C, 3) LoadUSNode(ctl, mem, adr, adr_type, rt->is_int() ); + case T_SHORT: return new (C, 3) LoadSNode (ctl, mem, adr, adr_type, rt->is_int() ); + case T_LONG: return new (C, 3) LoadLNode (ctl, mem, adr, adr_type, rt->is_long() ); + case T_FLOAT: return new (C, 3) LoadFNode (ctl, mem, adr, adr_type, rt ); + case T_DOUBLE: return new (C, 3) LoadDNode (ctl, mem, adr, adr_type, rt ); + case T_ADDRESS: return new (C, 3) LoadPNode (ctl, mem, adr, adr_type, rt->is_ptr() ); case T_OBJECT: #ifdef _LP64 if (adr->bottom_type()->is_ptr_to_narrowoop()) { @@ -1357,7 +1357,7 @@ Node *LoadNode::Ideal(PhaseGVN *phase, bool can_reshape) { // Steps (a), (b): Walk past independent stores to find an exact match. if (prev_mem != NULL && prev_mem != in(MemNode::Memory)) { // (c) See if we can fold up on the spot, but don't fold up here. - // Fold-up might require truncation (for LoadB/LoadS/LoadC) or + // Fold-up might require truncation (for LoadB/LoadS/LoadUS) or // just return a prior value, which is done by Identity calls. if (can_see_stored_value(prev_mem, phase)) { // Make ready for step (d): @@ -1606,14 +1606,14 @@ Node *LoadBNode::Ideal(PhaseGVN *phase, bool can_reshape) { return LoadNode::Ideal(phase, can_reshape); } -//--------------------------LoadCNode::Ideal-------------------------------------- +//--------------------------LoadUSNode::Ideal------------------------------------- // // If the previous store is to the same address as this load, // and the value stored was larger than a char, replace this load // with the value stored truncated to a char. If no truncation is // needed, the replacement is done in LoadNode::Identity(). // -Node *LoadCNode::Ideal(PhaseGVN *phase, bool can_reshape) { +Node *LoadUSNode::Ideal(PhaseGVN *phase, bool can_reshape) { Node* mem = in(MemNode::Memory); Node* value = can_see_stored_value(mem,phase); if( value && !phase->type(value)->higher_equal( _type ) ) diff --git a/src/share/vm/opto/memnode.hpp b/src/share/vm/opto/memnode.hpp index e1a84febc448ad28f7923d20579150a37334709f..63cb0d653f7ff5130883c082b9e3cad70b1ec4a4 100644 --- a/src/share/vm/opto/memnode.hpp +++ b/src/share/vm/opto/memnode.hpp @@ -207,11 +207,11 @@ public: virtual BasicType memory_type() const { return T_BYTE; } }; -//------------------------------LoadCNode-------------------------------------- -// Load a char (16bits unsigned) from memory -class LoadCNode : public LoadNode { +//------------------------------LoadUSNode------------------------------------- +// Load an unsigned short/char (16bits unsigned) from memory +class LoadUSNode : public LoadNode { public: - LoadCNode( Node *c, Node *mem, Node *adr, const TypePtr* at, const TypeInt *ti = TypeInt::CHAR ) + LoadUSNode( Node *c, Node *mem, Node *adr, const TypePtr* at, const TypeInt *ti = TypeInt::CHAR ) : LoadNode(c,mem,adr,at,ti) {} virtual int Opcode() const; virtual uint ideal_reg() const { return Op_RegI; } diff --git a/src/share/vm/opto/mulnode.cpp b/src/share/vm/opto/mulnode.cpp index 5cdcbafbc4b5d8f5d8936decb505c4123e08de93..c2e24eef916e90b20574e17a282cf351d2df47dc 100644 --- a/src/share/vm/opto/mulnode.cpp +++ b/src/share/vm/opto/mulnode.cpp @@ -442,7 +442,7 @@ Node *AndINode::Identity( PhaseTransform *phase ) { return load; } uint lop = load->Opcode(); - if( lop == Op_LoadC && + if( lop == Op_LoadUS && con == 0x0000FFFF ) // Already zero-extended return load; // Masking off the high bits of a unsigned-shift-right is not @@ -470,19 +470,19 @@ Node *AndINode::Ideal(PhaseGVN *phase, bool can_reshape) { uint lop = load->Opcode(); // Masking bits off of a Character? Hi bits are already zero. - if( lop == Op_LoadC && + if( lop == Op_LoadUS && (mask & 0xFFFF0000) ) // Can we make a smaller mask? return new (phase->C, 3) AndINode(load,phase->intcon(mask&0xFFFF)); // Masking bits off of a Short? Loading a Character does some masking if( lop == Op_LoadS && (mask & 0xFFFF0000) == 0 ) { - Node *ldc = new (phase->C, 3) LoadCNode(load->in(MemNode::Control), + Node *ldus = new (phase->C, 3) LoadUSNode(load->in(MemNode::Control), load->in(MemNode::Memory), load->in(MemNode::Address), load->adr_type()); - ldc = phase->transform(ldc); - return new (phase->C, 3) AndINode(ldc,phase->intcon(mask&0xFFFF)); + ldus = phase->transform(ldus); + return new (phase->C, 3) AndINode(ldus, phase->intcon(mask&0xFFFF)); } // Masking sign bits off of a Byte? Let the matcher use an unsigned load @@ -913,7 +913,7 @@ Node *RShiftINode::Ideal(PhaseGVN *phase, bool can_reshape) { set_req(2, phase->intcon(0)); return this; } - else if( ld->Opcode() == Op_LoadC ) + else if( ld->Opcode() == Op_LoadUS ) // Replace zero-extension-load with sign-extension-load return new (phase->C, 3) LoadSNode( ld->in(MemNode::Control), ld->in(MemNode::Memory), diff --git a/src/share/vm/opto/superword.cpp b/src/share/vm/opto/superword.cpp index acc8248500daf409b5d6bc35cdc1f0d3ff1ad6fb..4551162bff368646b8d24c9a978722fa510c5488 100644 --- a/src/share/vm/opto/superword.cpp +++ b/src/share/vm/opto/superword.cpp @@ -1444,7 +1444,7 @@ const Type* SuperWord::container_type(const Type* t) { // (Start, end] half-open range defining which operands are vector void SuperWord::vector_opd_range(Node* n, uint* start, uint* end) { switch (n->Opcode()) { - case Op_LoadB: case Op_LoadC: + case Op_LoadB: case Op_LoadUS: case Op_LoadI: case Op_LoadL: case Op_LoadF: case Op_LoadD: case Op_LoadP: diff --git a/src/share/vm/opto/vectornode.cpp b/src/share/vm/opto/vectornode.cpp index bf2cdc81ac8168213b41bcc0887687cc3a8af05b..7b6fef64bdf88110f6b013a9dc716a43c593e3fa 100644 --- a/src/share/vm/opto/vectornode.cpp +++ b/src/share/vm/opto/vectornode.cpp @@ -239,7 +239,7 @@ int VectorNode::opcode(int sopc, uint vlen, const Type* opd_t) { return Op_XorV; case Op_LoadB: - case Op_LoadC: + case Op_LoadUS: case Op_LoadS: case Op_LoadI: case Op_LoadL: @@ -269,7 +269,7 @@ int VectorLoadNode::opcode(int sopc, uint vlen) { case 16: return Op_Load16B; } break; - case Op_LoadC: + case Op_LoadUS: switch (vlen) { case 2: return Op_Load2C; case 4: return Op_Load4C;