/*
 * Device Tree Include file for Marvell Armada 370 and Armada XP SoC
 *
 * Copyright (C) 2012 Marvell
 *
 * Lior Amsalem <alior@marvell.com>
 * Gregory CLEMENT <gregory.clement@free-electrons.com>
 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
 * Ben Dooks <ben.dooks@codethink.co.uk>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 *
 * This file contains the definitions that are common to the Armada
 * 370 and Armada XP SoC.
 */

/include/ "skeleton.dtsi"

/ {
	model = "Marvell Armada 370 and XP SoC";
	compatible = "marvell,armada-370-xp";

	cpus {
		cpu@0 {
			compatible = "marvell,sheeva-v7";
		};
	};

	mpic: interrupt-controller@d0020000 {
	      compatible = "marvell,mpic";
	      #interrupt-cells = <1>;
	      #address-cells = <1>;
	      #size-cells = <1>;
	      interrupt-controller;
	};

	coherency-fabric@d0020200 {
		compatible = "marvell,coherency-fabric";
		reg = <0xd0020200 0xb0>,
		      <0xd0021810 0x1c>;
	};

	soc {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		interrupt-parent = <&mpic>;
		ranges;

		serial@d0012000 {
				compatible = "snps,dw-apb-uart";
				reg = <0xd0012000 0x100>;
				reg-shift = <2>;
				interrupts = <41>;
				reg-io-width = <4>;
				status = "disabled";
		};
		serial@d0012100 {
				compatible = "snps,dw-apb-uart";
				reg = <0xd0012100 0x100>;
				reg-shift = <2>;
				interrupts = <42>;
				reg-io-width = <4>;
				status = "disabled";
		};

		timer@d0020300 {
			       compatible = "marvell,armada-370-xp-timer";
			       reg = <0xd0020300 0x30>;
			       interrupts = <37>, <38>, <39>, <40>;
			       clocks = <&coreclk 2>;
		};

		addr-decoding@d0020000 {
			compatible = "marvell,armada-addr-decoding-controller";
			reg = <0xd0020000 0x258>;
		};

		sata@d00a0000 {
			compatible = "marvell,orion-sata";
			reg = <0xd00a0000 0x2400>;
			interrupts = <55>;
			clocks = <&gateclk 15>, <&gateclk 30>;
			clock-names = "0", "1";
			status = "disabled";
		};

		mdio {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "marvell,orion-mdio";
			reg = <0xd0072004 0x4>;
		};

		ethernet@d0070000 {
				compatible = "marvell,armada-370-neta";
				reg = <0xd0070000 0x2500>;
				interrupts = <8>;
				clocks = <&gateclk 4>;
				status = "disabled";
		};

		ethernet@d0074000 {
				compatible = "marvell,armada-370-neta";
				reg = <0xd0074000 0x2500>;
				interrupts = <10>;
				clocks = <&gateclk 3>;
				status = "disabled";
		};

		i2c0: i2c@d0011000 {
			compatible = "marvell,mv64xxx-i2c";
			reg = <0xd0011000 0x20>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <31>;
			timeout-ms = <1000>;
			clocks = <&coreclk 0>;
			status = "disabled";
		};

		i2c1: i2c@d0011100 {
			compatible = "marvell,mv64xxx-i2c";
			reg = <0xd0011100 0x20>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <32>;
			timeout-ms = <1000>;
			clocks = <&coreclk 0>;
			status = "disabled";
		};

		rtc@10300 {
			compatible = "marvell,orion-rtc";
			reg = <0xd0010300 0x20>;
			interrupts = <50>;
		};

		mvsdio@d00d4000 {
			compatible = "marvell,orion-sdio";
			reg = <0xd00d4000 0x200>;
			interrupts = <54>;
			clocks = <&gateclk 17>;
			status = "disabled";
		};
	};
};