1. 17 5月, 2017 5 次提交
  2. 03 5月, 2017 2 次提交
    • C
      drm/i915: Squash repeated awaits on the same fence · 47979480
      Chris Wilson 提交于
      Track the latest fence waited upon on each context, and only add a new
      asynchronous wait if the new fence is more recent than the recorded
      fence for that context. This requires us to filter out unordered
      timelines, which are noted by DMA_FENCE_NO_CONTEXT. However, in the
      absence of a universal identifier, we have to use our own
      i915->mm.unordered_timeline token.
      
      v2: Throw around the debug crutches
      v3: Inline the likely case of the pre-allocation cache being full.
      v4: Drop the pre-allocation support, we can lose the most recent fence
      in case of allocation failure -- it just means we may emit more awaits
      than strictly necessary but will not break.
      v5: Trim allocation size for leaf nodes, they only need an array of u32
      not pointers.
      v6: Create mock_timeline to tidy selftest writing
      v7: s/intel_timeline_sync_get/intel_timeline_sync_is_later/ (Tvrtko)
      v8: Prune the stale sync points when we idle.
      v9: Include a small benchmark in the kselftests
      v10: Separate the idr implementation into its own compartment. (Tvrkto)
      v11: Refactor igt_sync kselftests to avoid deep nesting (Tvrkto)
      v12: __sync_leaf_idx() to assert that p->height is 0 when checking leaves
      v13: kselftests to investigate struct i915_syncmap itself (Tvrtko)
      v14: Foray into ascii art graphs
      v15: Take into account that the random lookup/insert does 2 prng calls,
      not 1, when benchmarking, and use for_each_set_bit() (Tvrtko)
      v16: Improved ascii art
      Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
      Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
      Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
      Reviewed-by: NTvrtko Ursulin <tvrtko.ursulin@intel.com>
      Link: http://patchwork.freedesktop.org/patch/msgid/20170503093924.5320-4-chris@chris-wilson.co.uk
      47979480
    • C
      drm/i915: Mark up clflushes as belonging to an unordered timeline · 94312828
      Chris Wilson 提交于
      2 clflushes on two different objects are not ordered, and so do not
      belong to the same timeline (context). Either we use a unique context
      for each, or we reserve a special global context to mean unordered.
      Ideally, we would reserve 0 to mean unordered (DMA_FENCE_NO_CONTEXT) to
      have the same semantics everywhere.
      Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
      Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
      Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
      Reviewed-by: NJoonas Lahtinen <joonas.lahtinen@linux.intel.com>
      Link: http://patchwork.freedesktop.org/patch/msgid/20170503093924.5320-1-chris@chris-wilson.co.uk
      94312828
  3. 28 4月, 2017 2 次提交
  4. 26 4月, 2017 1 次提交
  5. 12 4月, 2017 2 次提交
  6. 11 4月, 2017 2 次提交
  7. 07 4月, 2017 5 次提交
  8. 06 4月, 2017 2 次提交
  9. 04 4月, 2017 1 次提交
  10. 31 3月, 2017 4 次提交
  11. 30 3月, 2017 1 次提交
  12. 27 3月, 2017 1 次提交
    • C
      drm/i915: Check we have an wake device before flushing GTT writes · e2a2aa36
      Chris Wilson 提交于
      We can assume that if the device is asleep then all pending GTT writes
      will have been posted, and so we can defer the flush from
      i915_gem_object_flush_gtt_write_domain()
      
      [ 1957.462568] WARNING: CPU: 0 PID: 6132 at drivers/gpu/drm/i915/intel_drv.h:1742 fwtable_read32+0x123/0x150 [i915]
      [ 1957.462582] RPM wakelock ref not held during HW access
      [ 1957.462583] Modules linked in: i915 intel_gtt drm_kms_helper prime_numbers
      [ 1957.462607] CPU: 0 PID: 6132 Comm: gem_concurrent_ Tainted: G     U          4.11.0-rc1+ #464
      [ 1957.462619] Hardware name:                  /        , BIOS PYBSWCEL.86A.0027.2015.0507.1758 05/07/2015
      [ 1957.462630] Call Trace:
      [ 1957.462646]  dump_stack+0x4d/0x6f
      [ 1957.462657]  __warn+0xc1/0xe0
      [ 1957.462667]  warn_slowpath_fmt+0x4a/0x50
      [ 1957.462709]  fwtable_read32+0x123/0x150 [i915]
      [ 1957.462750]  i915_gem_object_flush_gtt_write_domain+0x43/0x70 [i915]
      [ 1957.462791]  i915_gem_object_set_to_cpu_domain+0x46/0xa0 [i915]
      [ 1957.462831]  i915_gem_set_domain_ioctl+0x15d/0x220 [i915]
      [ 1957.462843]  drm_ioctl+0x1d7/0x440
      [ 1957.462885]  ? i915_gem_obj_prepare_shmem_write+0x1d0/0x1d0 [i915]
      [ 1957.462896]  ? pick_next_task_fair+0x436/0x440
      [ 1957.462906]  ? mntput+0x1f/0x30
      [ 1957.462915]  do_vfs_ioctl+0x8f/0x5c0
      [ 1957.462925]  ? __schedule+0x16f/0x5f0
      [ 1957.462935]  ? ____fput+0x9/0x10
      [ 1957.462943]  SyS_ioctl+0x3c/0x70
      [ 1957.462952]  entry_SYSCALL_64_fastpath+0x17/0x98
      [ 1957.462961] RIP: 0033:0x7fc542179ca7
      [ 1957.462968] RSP: 002b:00007ffeef12ff98 EFLAGS: 00000246 ORIG_RAX: 0000000000000010
      [ 1957.462982] RAX: ffffffffffffffda RBX: 00007ffeef1301d0 RCX: 00007fc542179ca7
      [ 1957.462990] RDX: 00007ffeef12ffd0 RSI: 00000000400c645f RDI: 0000000000000003
      [ 1957.462999] RBP: 0000000000000003 R08: 000055f433bc7c40 R09: 000000000000002c
      [ 1957.463006] R10: 0000000000000073 R11: 0000000000000246 R12: 0000000000000018
      [ 1957.463015] R13: 000055f432c89d20 R14: 000055f432c87690 R15: 0000000000000000
      
      Fixes: 3b5724d7 ("drm/i915: Wait for writes through the GTT to land before reading back")
      Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
      Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
      Link: http://patchwork.freedesktop.org/patch/msgid/20170323150053.28582-1-chris@chris-wilson.co.ukReviewed-by: NJoonas Lahtinen <joonas.lahtinen@linux.intel.com>
      e2a2aa36
  13. 23 3月, 2017 3 次提交
  14. 20 3月, 2017 1 次提交
  15. 18 3月, 2017 2 次提交
  16. 17 3月, 2017 2 次提交
  17. 15 3月, 2017 2 次提交
    • A
      drm/i915/guc: Simplify intel_guc_init_hw() · 6cd5a72c
      Arkadiusz Hiler 提交于
      Current version of intel_guc_init_hw() does a lot:
       - cares about submission
       - loads huc
       - implement WA
      
      This change offloads some of the logic to intel_uc_init_hw(), which now
      cares about the above.
      
      v2: rename guc_hw_reset and fix typo in define name (M. Wajdeczko)
      v3: rename once again
      v4: remove spurious comments and add some style (J. Lahtinen)
      v5: flow changes, got rid of dead checks (M. Wajdeczko)
      v6: rebase
      v7: rebase & onion teardown (J. Lahtinen)
      
      Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
      Cc: Michal Winiarski <michal.winiarski@intel.com>
      Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
      Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
      Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
      Signed-off-by: NArkadiusz Hiler <arkadiusz.hiler@intel.com>
      Reviewed-by: NJoonas Lahtinen <joonas.lahtinen@linux.intel.com>
      Signed-off-by: NJoonas Lahtinen <joonas.lahtinen@linux.intel.com>
      6cd5a72c
    • A
      drm/i915/uc: Rename intel_?uc_{setup, load}() to _init_hw() · 882d1db0
      Arkadiusz Hiler 提交于
      GuC historically has two "startup" functions called _init() and _setup()
      
      Then HuC came with it's _init() and _load().
      
      This commit renames intel_guc_setup() and intel_huc_load() to
      *uc_init_hw() as they called from the i915_gem_init_hw().
      
      The aim is to be consistent in that entry points called during
      particular driver init phases (e.g. init_hw) are all suffixed by that
      phase. When reading the leaf functions, it should be clear at what stage
      during the driver load it is called and therefore what operations are
      legal at that point.
      
      Also, since the functions start with intel_guc and intel_huc they take
      appropiate structure.
      
      v2: commit message update (Chris Wilson)
      v3: change taken parameters to be more "semantic" (M. Wajdeczko)
      
      Cc: Chris Wilson <chris@chris-wilson.co.uk>
      Cc: Michal Winiarski <michal.winiarski@intel.com>
      Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
      Signed-off-by: NArkadiusz Hiler <arkadiusz.hiler@intel.com>
      Reviewed-by: NJoonas Lahtinen <joonas.lahtinen@linux.intel.com>
      Signed-off-by: NJoonas Lahtinen <joonas.lahtinen@linux.intel.com>
      882d1db0
  18. 14 3月, 2017 2 次提交