1. 03 8月, 2018 1 次提交
  2. 26 7月, 2018 3 次提交
    • J
      drm/msm: Add SDM845 DPU support · 25fdd593
      Jeykumar Sankaran 提交于
      SDM845 SoC includes the Mobile Display Sub System (MDSS) which is a
      top level wrapper consisting of Display Processing Unit (DPU) and
      display peripheral modules such as Display Serial Interface (DSI)
      and DisplayPort (DP).
      
      MDSS functions essentially as a back-end composition engine. It blends
      video and graphic images stored in the frame buffers and scans out the
      composed image to a display sink (over DSI/DP).
      
      The following diagram represents hardware blocks for a simple pipeline
      (two planes are present on a given crtc which is connected to a DSI
      connector):
      
             MDSS
            +---------------------------------+
            | +-----------------------------+ |
            | | DPU                         | |
            | |  +--------+  +--------+     | |
            | |  |  SSPP  |  |  SSPP  |     | |
            | |  +----+---+  +----+---+     | |
            | |       |           |         | |
            | |  +----v-----------v---+     | |
            | |  |  Layer Mixer (LM)  |     | |
            | |  +--------------------+     | |
            | |  +--------------------+     | |
            | |  |    PingPong (PP)   |     | |
            | |  +--------------------+     | |
            | |  +--------------------+     | |
            | |  |  INTERFACE (VIDEO) |     | |
            | |  +---+----------------+     | |
            | +------|----------------------+ |
            |        |                        |
            | +------|---------------------+  |
            | |      | DISPLAY PERIPHERALS |  |
            | |  +---v-+      +-----+      |  |
            | |  | DSI |      |  DP |      |  |
            | |  +-----+      +-----+      |  |
            | +----------------------------+  |
            +---------------------------------+
      
      The number of DPU sub-blocks (i.e. SSPPs, LMs, PP blocks and INTFs)
      depends on SoC capabilities.
      
      Overview of DPU sub-blocks:
      ---------------------------
      * Source Surface Processor (SSPP):
       Refers to any of hardware pipes like ViG, DMA etc. Only ViG pipes are
       capable of performing format conversion, scaling and quality improvement
       for source surfaces.
      
      * Layer Mixer (LM):
       Blend source surfaces together (in requested zorder)
      
      * PingPong (PP):
       This block controls frame done interrupt output, EOL and EOF generation,
       overflow/underflow control.
      
      * Display interface (INTF):
       Timing generator and interface connecting the display peripherals.
      
      DRM components mapping to DPU architecture:
      ------------------------------------------
      PLANEs maps to SSPPs
      CRTC maps to LMs
      Encoder maps to PPs, INTFs
      
      Data flow setup:
      ---------------
      MDSS hardware can support various data flows (e.g.):
        - Dual pipe: Output from two LMs combined to single display.
        - Split display: Output from two LMs connected to two separate
                         interfaces.
      
      The hardware capabilities determine the number of concurrent data paths
      possible. Any control path (i.e. pipeline w/i DPU) can be routed to any
      of the hardware data paths. A given control path can be triggered,
      flushed and controlled independently.
      
      Changes in v3:
      - Move msm_media_info.h from uapi to dpu/ subdir
      - Remove preclose callback dpu (it's handled in core)
      - Fix kbuild warnings with parent_ops
      - Remove unused functions from dpu_core_irq
      - Rename mdss_phys to mdss
      - Rename mdp_phys address space to mdp
      - Drop _phys from vbif and regdma binding names
      Signed-off-by: NAbhinav Kumar <abhinavk@codeaurora.org>
      Signed-off-by: NArchit Taneja <architt@codeaurora.org>
      Signed-off-by: NChandan Uddaraju <chandanu@codeaurora.org>
      Signed-off-by: NJeykumar Sankaran <jsanka@codeaurora.org>
      Signed-off-by: NJordan Crouse <jcrouse@codeaurora.org>
      Signed-off-by: NRajesh Yadav <ryadav@codeaurora.org>
      Signed-off-by: NSravanthi Kollukuduru <skolluku@codeaurora.org>
      Signed-off-by: NSean Paul <seanpaul@chromium.org>
      [robclark minor rebase]
      Signed-off-by: NRob Clark <robdclark@gmail.com>
      25fdd593
    • J
      drm/msm: #define MAX_<OBJECT> in msm_drv.h · 7305a0ce
      Jeykumar Sankaran 提交于
      dpu uses these elsewhere in the driver (in addition to increasing
      MAX_PLANES, that'll come later), so pull them out into #define.
      
      Changes in v3:
      - None
      Signed-off-by: NJeykumar Sankaran <jsanka@codeaurora.org>
      [seanpaul pulled this out of the dpu megapatch]
      Signed-off-by: NSean Paul <seanpaul@chromium.org>
      Signed-off-by: NRob Clark <robdclark@gmail.com>
      7305a0ce
    • S
      drm/msm: Clean up dangling atomic_wq · 74312fc7
      Sean Paul 提交于
      I missed this during the atomic conversion
      
      Changes in v3:
      - None
      Signed-off-by: NSean Paul <seanpaul@chromium.org>
      Signed-off-by: NRob Clark <robdclark@gmail.com>
      74312fc7
  3. 25 7月, 2018 1 次提交
  4. 05 6月, 2018 3 次提交
  5. 19 3月, 2018 1 次提交
  6. 14 12月, 2017 1 次提交
    • A
      drm/msm: fix msm_rd_dump_submit prototype · e6756d7c
      Arnd Bergmann 提交于
      The prototype of msm_rd_dump_submit() has recently changed. However,
      we have two declarations of this functions, and the other one
      remains the old version, leading to this:
      
      drivers/gpu/drm/msm/msm_gpu.c: In function 'recover_worker':
      drivers/gpu/drm/msm/msm_gpu.c:295:23: error: passing argument 1 of 'msm_rd_dump_submit' from incompatible pointer type [-Werror=incompatible-pointer-types]
      
      This changes the second one to match the first again.
      
      Fixes: 2165e2b9 ("drm/msm: split rd debugfs file")
      Signed-off-by: NArnd Bergmann <arnd@arndb.de>
      Signed-off-by: NRob Clark <robdclark@gmail.com>
      e6756d7c
  7. 29 10月, 2017 4 次提交
  8. 28 10月, 2017 4 次提交
    • J
      drm/msm: Removed unused struct_mutex_task · 3ceaa141
      Jordan Crouse 提交于
      Recent changes to locking have rendered struct_mutex_task
      unused.
      
      Unused since 0e08270a.
      Signed-off-by: NJordan Crouse <jcrouse@codeaurora.org>
      Signed-off-by: NRob Clark <robdclark@gmail.com>
      3ceaa141
    • J
      drm/msm: Implement preemption for A5XX targets · b1fc2839
      Jordan Crouse 提交于
      Implement preemption for A5XX targets - this allows multiple
      ringbuffers for different priorities with automatic preemption
      of a lower priority ringbuffer if a higher one is ready.
      Signed-off-by: NJordan Crouse <jcrouse@codeaurora.org>
      Signed-off-by: NRob Clark <robdclark@gmail.com>
      b1fc2839
    • J
      drm/msm: Support multiple ringbuffers · f97decac
      Jordan Crouse 提交于
      Add the infrastructure to support the idea of multiple ringbuffers.
      Assign each ringbuffer an id and use that as an index for the various
      ring specific operations.
      
      The biggest delta is to support legacy fences. Each fence gets its own
      sequence number but the legacy functions expect to use a unique integer.
      To handle this we return a unique identifier for each submission but
      map it to a specific ring/sequence under the covers. Newer users use
      a dma_fence pointer anyway so they don't care about the actual sequence
      ID or ring.
      
      The actual mechanics for multiple ringbuffers are very target specific
      so this code just allows for the possibility but still only defines
      one ringbuffer for each target family.
      Signed-off-by: NJordan Crouse <jcrouse@codeaurora.org>
      Signed-off-by: NRob Clark <robdclark@gmail.com>
      f97decac
    • J
      drm/msm: Add per-instance submit queues · f7de1545
      Jordan Crouse 提交于
      Currently the behavior of a command stream is provided by the user
      application during submission and the application is expected to internally
      maintain the settings for each 'context' or 'rendering queue' and specify
      the correct ones.
      
      This works okay for simple cases but as applications become more
      complex we will want to set context specific flags and do various
      permission checks to allow certain contexts to enable additional
      privileges.
      
      Add kernel-side submit queues to be analogous to 'contexts' or
      'rendering queues' on the application side. Each file descriptor
      instance will maintain its own list of queues. Queues cannot be
      shared between file descriptors.
      
      For backwards compatibility context id '0' is defined as a default
      context specifying no priority and no special flags. This is
      intended to be the usual configuration for 99% of applications so
      that a garden variety application can function correctly without
      creating a queue. Only those applications requiring the specific
      benefit of different queues need create one.
      Signed-off-by: NJordan Crouse <jcrouse@codeaurora.org>
      Signed-off-by: NRob Clark <robdclark@gmail.com>
      f7de1545
  9. 23 8月, 2017 4 次提交
  10. 17 6月, 2017 1 次提交
  11. 16 6月, 2017 2 次提交
  12. 28 5月, 2017 1 次提交
  13. 08 4月, 2017 1 次提交
  14. 20 3月, 2017 1 次提交
  15. 08 3月, 2017 1 次提交
  16. 25 2月, 2017 1 次提交
  17. 07 2月, 2017 2 次提交
  18. 29 11月, 2016 1 次提交
    • R
      drm/msm: convert iova to 64b · 78babc16
      Rob Clark 提交于
      For a5xx the gpu is 64b so we need to change iova to 64b everywhere.  On
      the display side, iova is still 32b so it can ignore the upper bits.
      (Although all the armv8 devices have an iommu that can map 64b pa to 32b
      iova.)
      Signed-off-by: NRob Clark <robdclark@gmail.com>
      78babc16
  19. 28 11月, 2016 3 次提交
  20. 27 11月, 2016 1 次提交
  21. 25 10月, 2016 1 次提交
    • C
      dma-buf: Rename struct fence to dma_fence · f54d1867
      Chris Wilson 提交于
      I plan to usurp the short name of struct fence for a core kernel struct,
      and so I need to rename the specialised fence/timeline for DMA
      operations to make room.
      
      A consensus was reached in
      https://lists.freedesktop.org/archives/dri-devel/2016-July/113083.html
      that making clear this fence applies to DMA operations was a good thing.
      Since then the patch has grown a bit as usage increases, so hopefully it
      remains a good thing!
      
      (v2...: rebase, rerun spatch)
      v3: Compile on msm, spotted a manual fixup that I broke.
      v4: Try again for msm, sorry Daniel
      
      coccinelle script:
      @@
      
      @@
      - struct fence
      + struct dma_fence
      @@
      
      @@
      - struct fence_ops
      + struct dma_fence_ops
      @@
      
      @@
      - struct fence_cb
      + struct dma_fence_cb
      @@
      
      @@
      - struct fence_array
      + struct dma_fence_array
      @@
      
      @@
      - enum fence_flag_bits
      + enum dma_fence_flag_bits
      @@
      
      @@
      (
      - fence_init
      + dma_fence_init
      |
      - fence_release
      + dma_fence_release
      |
      - fence_free
      + dma_fence_free
      |
      - fence_get
      + dma_fence_get
      |
      - fence_get_rcu
      + dma_fence_get_rcu
      |
      - fence_put
      + dma_fence_put
      |
      - fence_signal
      + dma_fence_signal
      |
      - fence_signal_locked
      + dma_fence_signal_locked
      |
      - fence_default_wait
      + dma_fence_default_wait
      |
      - fence_add_callback
      + dma_fence_add_callback
      |
      - fence_remove_callback
      + dma_fence_remove_callback
      |
      - fence_enable_sw_signaling
      + dma_fence_enable_sw_signaling
      |
      - fence_is_signaled_locked
      + dma_fence_is_signaled_locked
      |
      - fence_is_signaled
      + dma_fence_is_signaled
      |
      - fence_is_later
      + dma_fence_is_later
      |
      - fence_later
      + dma_fence_later
      |
      - fence_wait_timeout
      + dma_fence_wait_timeout
      |
      - fence_wait_any_timeout
      + dma_fence_wait_any_timeout
      |
      - fence_wait
      + dma_fence_wait
      |
      - fence_context_alloc
      + dma_fence_context_alloc
      |
      - fence_array_create
      + dma_fence_array_create
      |
      - to_fence_array
      + to_dma_fence_array
      |
      - fence_is_array
      + dma_fence_is_array
      |
      - trace_fence_emit
      + trace_dma_fence_emit
      |
      - FENCE_TRACE
      + DMA_FENCE_TRACE
      |
      - FENCE_WARN
      + DMA_FENCE_WARN
      |
      - FENCE_ERR
      + DMA_FENCE_ERR
      )
       (
       ...
       )
      Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
      Reviewed-by: NGustavo Padovan <gustavo.padovan@collabora.co.uk>
      Acked-by: NSumit Semwal <sumit.semwal@linaro.org>
      Acked-by: NChristian König <christian.koenig@amd.com>
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      Link: http://patchwork.freedesktop.org/patch/msgid/20161025120045.28839-1-chris@chris-wilson.co.uk
      f54d1867
  22. 29 8月, 2016 1 次提交
  23. 16 7月, 2016 1 次提交