With the intc core improved it is now possible to put the intc data
structures in the initdata section.

Version two of this patch puts the __initdata inside DECLARE_INTC_DESC()
and removes the __initdata included in the board specific r2d code.
Signed-off-by: NMagnus Damm <damm@igel.co.jp>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

With the intc dual prio register support in place it is now possible
to add the ipi vectors to x3.
Signed-off-by: NMagnus Damm <damm@igel.co.jp>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This patch replaces all instances of CONFIG_VOYAGERGX with
CONFIG_MFD_SM501. While at it we make sure the r2d code compiles
both with and without SM501.
Signed-off-by: NMagnus Damm <damm@igel.co.jp>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This patch converts the board specific interrupt code for r2d to make
use of intc. While at it we improve the Kconfig to avoid confusion.

- Two sets of interrupt tables exist - one for R2D-1 and one for R2D-PLUS.
- R2D-1 and R2D-PLUS use the same irq constants.
- R2D-1 has AX88796 support, R2D-PLUS does not hook up that IRQ.
- R2D-PLUS has KEY support, R2D-1 does not hook up that IRQ.
- The number and order of IRQ values are disconnected from register bits.
- Interrupt sources now start from IRQ 100.
- The machvec demux function converts from irlm IRQ 0-14 to IRQ 100++.

Tested on R2D-1 and R2D-PLUS boards.

Version 2 adds CONFIG_RTS7751R2D_1 and CONFIG_RTS7751R2D_PLUS together
with intc structured as __initdata.
Signed-off-by: NMagnus Damm <damm@igel.co.jp>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This patch reworks the intc core, implementing the following features:

- Support dual priority registers - one set and one clear register
- All 8/16/32 bit register combinations are now supported
- Both single mask and single enable bitmap register are supported
- Add code to set interrupt priority
- Speedup sense and priority configuration code
- Allocate data using bootmem, allows intc data structures to be
  __initdata
- Save memory - allocated memory footprint is smaller than intc
  structures
Signed-off-by: NMagnus Damm <damm@igel.co.jp>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

We need a secondary register member in struct intc_prio_reg to support
dual priority registers used by ipi on x3.
Signed-off-by: NMagnus Damm <damm@igel.co.jp>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This makes sure the function prototype for setup_bootmem_node() gets
included. The file setup-shx3.c does not compile otherwise for
CONFIG_NUMA=n.
Signed-off-by: NMagnus Damm <damm@igel.co.jp>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This adds support for the SH7720 (SH3-DSP) CPU.

Signed-off by: Markus Brunner <super.firetwister@gmail.com>
Signed-off by: Mark Jonas <toertel@gmail.com>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

synchronize_irq() was being exported twice, kill off the duplicate
export.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Now that NODES_SHIFT is bumped up, we can plug in the CSM block as
a separate node, too.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This was at 1, which is where most subtypes want it. SH-X3 has
more nodes, so bump it up to 3.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Now that we have a way of enabling the IRQs, hook up the platform
devices and wrap in to ILSEL for mapping the vectors.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This adds functionality for the on-board ILSEL IRQs that chain
IRL mode events. Many on-board devices (ethernet, usb, etc.) rely
on ILSEL IRQs directly.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This adds initial support for the SH-X3 prototype board.
Only simple logic for the IRQ controller and the heartbeat driver
for now.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

IRL doesn't always define sense registers, so don't bother trying to
iterate through the table. This ended up causing an oops on SH-X3
when using IRL mode.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

There is no point in keeping around the now unused intc2 code.
Signed-off-by: NMagnus Damm <damm@igel.co.jp>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This patch converts the sh-specific voyagergx interrupt code to make use
of intc. A lot of "interesting" old cruft gets replaced with intc tables
and some simple demux code.

- All interrupt sources in the sm501 data sheet are now in the header.
- The number and order of IRQ values are disconnected from register bits.
- Interrupt sources now start from IRQ 200.
- set_irq_chained_handler() is now used to hook up the demux function.

In the future it would probably make sense to move the interrupt demuxer
into into the mfd driver, but this is probably a nice step in the right
direction until that happens.

Tested on a R2D-1 board using the serial port hooked up to the sm501.
Signed-off-by: NMagnus Damm <damm@igel.co.jp>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This patch adds single bitmap register support to intc. The current
code only handles 16 and 32 bit registers where a set bit means
interrupt enabled, but this is easy to extend in the future.

The INTC_IRQ() macro is also added to provide a way to hook in
interrupt controllers for FPGAs in boards or companion chips.
Signed-off-by: NMagnus Damm <damm@igel.co.jp>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This patch removes redundant interrupt code for the shmin board which
is using a sh770x processor and 4 IRQ lines as individual interrupts
(IRQ-mode).
Signed-off-by: NMagnus Damm <damm@igel.co.jp>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This patch removes redundant board specific interrupt code for boards
using sh775x processors and 4 IRQ lines in "Individual Interrupt Mode"
aka IRLM.

Three boards are affected: sh03, snapgear and titan.

The right way to do this is to use cpu specific code provided by intc.
A nice side effect is that sh03 now compiles, board not BROKEN any more.
Signed-off-by: NMagnus Damm <damm@igel.co.jp>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

All SH-4 parts have a 4-digit year, while the SH-3 parts typically
only use a 2-digit one. The SH7705, SH7710, and SH7712 SH-3 parts
however opted to extend it to 4-digit and still look and act like
an SH-3 RTC in all other ways.

This adds a capability flag (RTC_CAP_4_DIGIT_YEAR) that these
corner-case CPU subtypes can set in their platform data and cleans
up some of the ifdef mess in the driver as a result.
Reported-by: NMarkus Brunner <super.firetwister@gmail.com>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Wire up CPU#0 URAM as node 1 on SH-X3.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This patch converts the cpu specific interrupt setup code for x3 from
intc2 to intc. New vectors are also added to match the preliminary
information.

Use plat_irq_setup_pins() to select between IRQ and IRL mode for IRQ0-3.
Signed-off-by: NMagnus Damm <damm@igel.co.jp>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

The intc tables for sh3 currently contain a typo where the bit
fields in IPRD are mixed up for IRQ4 and IRQ5. This patch makes
sure the correct bit fields are used - all according to the
datasheets.
Signed-off-by: NMagnus Damm <damm@igel.co.jp>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

The cache disabling stuff screwed up some of the sh4 nommu
builds, fix it up again.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

The new intc code handles IRQ3 and IRQ7 in the cpu specific code
already, so there is no reason to duplicate that here.
Signed-off-by: NMagnus Damm <damm@igel.co.jp>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This patch converts the cpu specific interrupt setup code for sh7760
from ipr + intc2 to intc. New vectors are also added to match the
information provided by the datasheet.

Vectors for IRQ4-IRQ7 are enabled by default. Use plat_irq_setup_pins()
if pins IRL0-3 should be used in IRLM mode.

The patch also adds the SIM block to the serial port platform data.
Version two of this patch fixes MMCIF problems reported by Manuel Lauss.
Signed-off-by: NMagnus Damm <damm@igel.co.jp>
Acked-by: NManuel Lauss <mano@roarinelk.homelinux.net>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This patch converts the cpu specific interrupt setup code for sh7785
from intc2 to intc. New vectors are also added to match the information
provided by the datasheet.

No IRQ/IRL pin vectors are enabled by default. Use plat_irq_setup_pins()
to select between IRL and IRQ mode.
Signed-off-by: NMagnus Damm <damm@igel.co.jp>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This reworks the cache mode configuration in Kconfig, and allows for
explicit selection of write-back/write-through/off configurations.
All of the cache flushing routines are optimized away for the off
case.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This patch makes sure that the sh7710 specific ipsec vector is missing
if building for a sh7712. All according to the datasheet.
Signed-off-by: NMagnus Damm <damm@igel.co.jp>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This patch adds a few missing vectors for sh7707. The only interrupt
controller differences between sh7707 and sh7709 seem to be added
vectors for one LCD controller and two PCMCIA slots.
Signed-off-by: NMagnus Damm <damm@igel.co.jp>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This patch unifies the cpu specific interrupt setup code for
sh7706, sh7707, sh7708 and sh7709 and moves the code into a new
file called setup-sh770x.c.  It makes sense to share the setup code
between these processors because most hardware blocks are identical
from a software point of view. With this patch the sh770x processors
now have a complete set of vectors that match with the information
provided by the data sheets. This is a big improvement for sh7708.

Vectors for IRQ4 and IRQ5 are enabled by default. Use
plat_irq_setup_pins() if pins IRQ0-3 should be used in IRQ mode.

This patch also unifies the platform device setup code which means
that the rtc driver now has platform data for all sh770x processors.
Signed-off-by: NMagnus Damm <damm@igel.co.jp>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This patch converts the cpu specific interrupt setup code
for sh7710 from ipr to intc. While at it new vectors are added
to match the information provided by the datasheet. Version two
simplifies the Kconfig part.

Vectors for IRQ4 and IRQ5 are enabled by default. Use
plat_irq_setup_pins() if pins IRQ0-3 should be used in IRQ mode.

This patch also adds sh7710 specific platform data for the rtc
driver. The base address of SCIF1 is adjusted to match the
datasheet.
Signed-off-by: NMagnus Damm <damm@igel.co.jp>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This patch converts the cpu specific interrupt setup code for
sh7705 from ipr to intc. While at it new vectors are added to
match the information provided by the datasheet.

Vectors for IRQ4 and IRQ5 are enabled by default.

Use plat_irq_setup_pins() if pins IRQ0-3 should be used in IRQ mode.

This patch also adds sh7705 specific platform data for the rtc driver.
Signed-off-by: NMagnus Damm <damm@igel.co.jp>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

There's an obvious typo in arch/i386/boot/header.S (in your
linux-2.6-x86setup.git) that I noticed by just studying the code.
Signed-off-by: NPaul Bolle <pebolle@tiscali.nl>
Signed-off-by: NH. Peter Anvin <hpa@zytor.com>

wakeup.S looks at the video mode number from the setup header and
looks to see if it is a VESA mode.  Unfortunately, the decoding is
done incorrectly and it will attempt to frob the VESA BIOS for any
mode number 0x0200 or larger.  Correct this, and remove a bunch of #if
0'd code.

Massive thanks to Jeff Chua for reporting the bug, and suffering
though a large number of experiments in order to track this problem
down.

Cc: Pavel Machek <pavel@ucw.cz>
Signed-off-by: NH. Peter Anvin <hpa@zytor.com>

Canonicalize the video mode number as presented to the kernel.  The
video mode number may be user-entered (e.g. ASK_VGA), an alias
(e.g. NORMAL_VGA), or a size specification, and that confuses the
suspend wakeup code.
Signed-off-by: NH. Peter Anvin <hpa@zytor.com>

Randy Dunlap noticed an interesting "crashme" behaviour on his dual
Prescott Xeon setup, where he gets page faults with the error code
having a zero "user" bit, but the register state points back to user
mode.

This may be a CPU microcode buglet triggered by some strange instruction
pattern that crashme generates, and loading a microcode update seems to
possibly have fixed it.

Regardless, we really should trust the register state more than the
error code, since it's really the register state that determines whether
we can actually send a signal, or whether we're in kernel mode and need
to oops/kill the process in the case of a page fault.

Cc: Randy Dunlap <rdunlap@xenotime.net>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>