clk: sunxi: Add PLL3 clock
The A10 SoCs and relatives have a PLL controller to drive the PLL3 and PLL7, clocked from a 3MHz oscillator, that drives the display related clocks (GPU, display engine, TCON, etc.) Add a driver for it. Acked-by: NRob Herring <robh@kernel.org> Acked-by: NChen-Yu Tsai <wens@csie.org> Acked-by: NStephen Boyd <sboyd@codeaurora.org> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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