提交 f0064388 编写于 作者: F Felix Fietkau 提交者: John W. Linville

ath5k: fix reference clock usec duration setting restore

enabling the sleep clock alters the AR5K_USEC_32 field, but disabling
it didn't restore it.
Signed-off-by: NFelix Fietkau <nbd@openwrt.org>
Acked-by: NNick Kossifidis <mickflemm@gmail.com>
Signed-off-by: NJohn W. Linville <linville@tuxdriver.com>
上级 fe00deb3
...@@ -142,6 +142,7 @@ static void ath5k_hw_init_core_clock(struct ath5k_hw *ah) ...@@ -142,6 +142,7 @@ static void ath5k_hw_init_core_clock(struct ath5k_hw *ah)
/* Set 32MHz USEC counter */ /* Set 32MHz USEC counter */
if ((ah->ah_radio == AR5K_RF5112) || if ((ah->ah_radio == AR5K_RF5112) ||
(ah->ah_radio == AR5K_RF2413) ||
(ah->ah_radio == AR5K_RF5413) || (ah->ah_radio == AR5K_RF5413) ||
(ah->ah_radio == AR5K_RF2316) || (ah->ah_radio == AR5K_RF2316) ||
(ah->ah_radio == AR5K_RF2317)) (ah->ah_radio == AR5K_RF2317))
...@@ -233,7 +234,7 @@ static void ath5k_hw_init_core_clock(struct ath5k_hw *ah) ...@@ -233,7 +234,7 @@ static void ath5k_hw_init_core_clock(struct ath5k_hw *ah)
static void ath5k_hw_set_sleep_clock(struct ath5k_hw *ah, bool enable) static void ath5k_hw_set_sleep_clock(struct ath5k_hw *ah, bool enable)
{ {
struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
u32 scal, spending; u32 scal, spending, sclock;
/* Only set 32KHz settings if we have an external /* Only set 32KHz settings if we have an external
* 32KHz crystal present */ * 32KHz crystal present */
...@@ -317,6 +318,15 @@ static void ath5k_hw_set_sleep_clock(struct ath5k_hw *ah, bool enable) ...@@ -317,6 +318,15 @@ static void ath5k_hw_set_sleep_clock(struct ath5k_hw *ah, bool enable)
/* Set up tsf increment on each cycle */ /* Set up tsf increment on each cycle */
AR5K_REG_WRITE_BITS(ah, AR5K_TSF_PARM, AR5K_TSF_PARM_INC, 1); AR5K_REG_WRITE_BITS(ah, AR5K_TSF_PARM, AR5K_TSF_PARM_INC, 1);
if ((ah->ah_radio == AR5K_RF5112) ||
(ah->ah_radio == AR5K_RF5413) ||
(ah->ah_radio == AR5K_RF2316) ||
(ah->ah_radio == AR5K_RF2317))
sclock = 40 - 1;
else
sclock = 32 - 1;
AR5K_REG_WRITE_BITS(ah, AR5K_USEC_5211, AR5K_USEC_32, sclock);
} }
} }
......
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