提交 d5917ef3 编写于 作者: L Laurent Pinchart 提交者: Simon Horman

sh: Don't set plat_sci_port scbrr_algo_id field

The field will be removed from the sh-sci driver. Don't set it and let
the driver handle baud rate calculation internally.
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
上级 64c535e9
......@@ -63,7 +63,6 @@ static DECLARE_INTC_DESC(intc_desc, "sh7619", vectors, NULL,
static struct plat_sci_port scif0_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
};
......@@ -85,7 +84,6 @@ static struct platform_device scif0_device = {
static struct plat_sci_port scif1_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
};
......@@ -107,7 +105,6 @@ static struct platform_device scif1_device = {
static struct plat_sci_port scif2_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
};
......
......@@ -201,7 +201,6 @@ static struct platform_device mtu2_2_device = {
static struct plat_sci_port scif0_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
};
......
......@@ -180,7 +180,6 @@ static DECLARE_INTC_DESC(intc_desc, "sh7201", vectors, groups,
static struct plat_sci_port scif0_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
};
......@@ -202,7 +201,6 @@ static struct platform_device scif0_device = {
static struct plat_sci_port scif1_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
};
......@@ -224,7 +222,6 @@ static struct platform_device scif1_device = {
static struct plat_sci_port scif2_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
};
......@@ -246,7 +243,6 @@ static struct platform_device scif2_device = {
static struct plat_sci_port scif3_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
};
......@@ -268,7 +264,6 @@ static struct platform_device scif3_device = {
static struct plat_sci_port scif4_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
};
......@@ -290,7 +285,6 @@ static struct platform_device scif4_device = {
static struct plat_sci_port scif5_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
};
......@@ -312,7 +306,6 @@ static struct platform_device scif5_device = {
static struct plat_sci_port scif6_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
};
......@@ -334,7 +327,6 @@ static struct platform_device scif6_device = {
static struct plat_sci_port scif7_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
};
......
......@@ -177,7 +177,6 @@ static struct plat_sci_port scif0_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
SCSCR_REIE,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
.regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
};
......@@ -201,7 +200,6 @@ static struct plat_sci_port scif1_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
SCSCR_REIE,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
.regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
};
......@@ -225,7 +223,6 @@ static struct plat_sci_port scif2_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
SCSCR_REIE,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
.regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
};
......@@ -249,7 +246,6 @@ static struct plat_sci_port scif3_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
SCSCR_REIE,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
.regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
};
......
......@@ -136,7 +136,6 @@ static DECLARE_INTC_DESC(intc_desc, "sh7206", vectors, groups,
static struct plat_sci_port scif0_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
};
......@@ -158,7 +157,6 @@ static struct platform_device scif0_device = {
static struct plat_sci_port scif1_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
};
......@@ -180,7 +178,6 @@ static struct platform_device scif1_device = {
static struct plat_sci_port scif2_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
};
......@@ -202,7 +199,6 @@ static struct platform_device scif2_device = {
static struct plat_sci_port scif3_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
};
......
......@@ -229,7 +229,6 @@ static struct plat_sci_port scif0_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
SCSCR_REIE | SCSCR_TOIE,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
.regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
};
......@@ -256,7 +255,6 @@ static struct plat_sci_port scif1_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
SCSCR_REIE | SCSCR_TOIE,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
.regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
};
......@@ -283,7 +281,6 @@ static struct plat_sci_port scif2_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
SCSCR_REIE | SCSCR_TOIE,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
.regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
};
......@@ -310,7 +307,6 @@ static struct plat_sci_port scif3_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
SCSCR_REIE | SCSCR_TOIE,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
.regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
};
......@@ -337,7 +333,6 @@ static struct plat_sci_port scif4_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
SCSCR_REIE | SCSCR_TOIE,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
.regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
};
......@@ -364,7 +359,6 @@ static struct plat_sci_port scif5_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
SCSCR_REIE | SCSCR_TOIE,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
.regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
};
......@@ -391,7 +385,6 @@ static struct plat_sci_port scif6_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
SCSCR_REIE | SCSCR_TOIE,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
.regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
};
......@@ -418,7 +411,6 @@ static struct plat_sci_port scif7_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
SCSCR_REIE | SCSCR_TOIE,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
.regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
};
......
......@@ -251,7 +251,6 @@ static struct plat_sci_port scif0_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
SCSCR_REIE | SCSCR_TOIE,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
.regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
};
......@@ -278,7 +277,6 @@ static struct plat_sci_port scif1_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
SCSCR_REIE | SCSCR_TOIE,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
.regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
};
......@@ -305,7 +303,6 @@ static struct plat_sci_port scif2_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
SCSCR_REIE | SCSCR_TOIE,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
.regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
};
......@@ -332,7 +329,6 @@ static struct plat_sci_port scif3_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
SCSCR_REIE | SCSCR_TOIE,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
.regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
};
......@@ -359,7 +355,6 @@ static struct plat_sci_port scif4_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
SCSCR_REIE | SCSCR_TOIE,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
.regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
};
......@@ -386,7 +381,6 @@ static struct plat_sci_port scif5_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
SCSCR_REIE | SCSCR_TOIE,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
.regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
};
......@@ -413,7 +407,6 @@ static struct plat_sci_port scif6_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
SCSCR_REIE | SCSCR_TOIE,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
.regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
};
......@@ -440,7 +433,6 @@ static struct plat_sci_port scif7_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
SCSCR_REIE | SCSCR_TOIE,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
.regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
};
......
......@@ -73,7 +73,6 @@ static struct plat_sci_port scif0_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_TIE | SCSCR_RIE | SCSCR_TE |
SCSCR_RE | SCSCR_CKE1 | SCSCR_CKE0,
.scbrr_algo_id = SCBRR_ALGO_4,
.type = PORT_SCIF,
.ops = &sh770x_sci_port_ops,
.regtype = SCIx_SH7705_SCIF_REGTYPE,
......@@ -97,7 +96,6 @@ static struct platform_device scif0_device = {
static struct plat_sci_port scif1_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_TIE | SCSCR_RIE | SCSCR_TE | SCSCR_RE,
.scbrr_algo_id = SCBRR_ALGO_4,
.type = PORT_SCIF,
.ops = &sh770x_sci_port_ops,
.regtype = SCIx_SH7705_SCIF_REGTYPE,
......
......@@ -112,7 +112,6 @@ static struct plat_sci_port scif0_platform_data = {
.port_reg = 0xa4000136,
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_TE | SCSCR_RE,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCI,
.ops = &sh770x_sci_port_ops,
.regshift = 1,
......@@ -138,7 +137,6 @@ static struct platform_device scif0_device = {
static struct plat_sci_port scif1_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_TE | SCSCR_RE,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
.ops = &sh770x_sci_port_ops,
.regtype = SCIx_SH3_SCIF_REGTYPE,
......@@ -165,7 +163,6 @@ static struct plat_sci_port scif2_platform_data = {
.port_reg = SCIx_NOT_SUPPORTED,
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_TE | SCSCR_RE,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_IRDA,
.ops = &sh770x_sci_port_ops,
.regshift = 1,
......
......@@ -101,7 +101,6 @@ static struct plat_sci_port scif0_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_TE | SCSCR_RE | SCSCR_REIE |
SCSCR_CKE1 | SCSCR_CKE0,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
};
......@@ -124,7 +123,6 @@ static struct plat_sci_port scif1_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_TE | SCSCR_RE | SCSCR_REIE |
SCSCR_CKE1 | SCSCR_CKE0,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
};
......
......@@ -54,7 +54,6 @@ static struct platform_device rtc_device = {
static struct plat_sci_port scif0_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE,
.scbrr_algo_id = SCBRR_ALGO_4,
.type = PORT_SCIF,
.ops = &sh7720_sci_port_ops,
.regtype = SCIx_SH7705_SCIF_REGTYPE,
......@@ -78,7 +77,6 @@ static struct platform_device scif0_device = {
static struct plat_sci_port scif1_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE,
.scbrr_algo_id = SCBRR_ALGO_4,
.type = PORT_SCIF,
.ops = &sh7720_sci_port_ops,
.regtype = SCIx_SH7705_SCIF_REGTYPE,
......
......@@ -19,7 +19,6 @@
static struct plat_sci_port scif0_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
};
......
......@@ -41,7 +41,6 @@ static struct plat_sci_port sci_platform_data = {
.port_reg = 0xffe0001C,
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_TE | SCSCR_RE,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCI,
.regshift = 2,
};
......@@ -64,7 +63,6 @@ static struct platform_device sci_device = {
static struct plat_sci_port scif_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_TE | SCSCR_RE | SCSCR_REIE,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
};
......
......@@ -130,7 +130,6 @@ static DECLARE_INTC_DESC(intc_desc_irq, "sh7760-irq", vectors_irq, groups,
static struct plat_sci_port scif0_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
.regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
};
......@@ -157,7 +156,6 @@ static struct plat_sci_port scif1_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.type = PORT_SCIF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
.scbrr_algo_id = SCBRR_ALGO_2,
.regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
};
......@@ -182,7 +180,6 @@ static struct platform_device scif1_device = {
static struct plat_sci_port scif2_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
.regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
};
......@@ -208,7 +205,6 @@ static struct platform_device scif2_device = {
static struct plat_sci_port scif3_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCI,
.regshift = 2,
};
......
......@@ -20,7 +20,6 @@
static struct plat_sci_port scif0_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
};
......@@ -42,7 +41,6 @@ static struct platform_device scif0_device = {
static struct plat_sci_port scif1_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
};
......@@ -64,7 +62,6 @@ static struct platform_device scif1_device = {
static struct plat_sci_port scif2_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
};
......@@ -86,7 +83,6 @@ static struct platform_device scif2_device = {
static struct plat_sci_port scif3_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
};
......
......@@ -23,7 +23,6 @@ static struct plat_sci_port scif0_platform_data = {
.port_reg = 0xa405013e,
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
};
......
......@@ -181,7 +181,6 @@ struct platform_device dma_device = {
static struct plat_sci_port scif0_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
.ops = &sh7722_sci_port_ops,
.regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
......@@ -205,7 +204,6 @@ static struct platform_device scif0_device = {
static struct plat_sci_port scif1_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
.ops = &sh7722_sci_port_ops,
.regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
......@@ -229,7 +227,6 @@ static struct platform_device scif1_device = {
static struct plat_sci_port scif2_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
.ops = &sh7722_sci_port_ops,
.regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
......
......@@ -26,7 +26,6 @@ static struct plat_sci_port scif0_platform_data = {
.port_reg = 0xa4050160,
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
.regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
};
......@@ -50,7 +49,6 @@ static struct plat_sci_port scif1_platform_data = {
.port_reg = SCIx_NOT_SUPPORTED,
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
.regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
};
......@@ -74,7 +72,6 @@ static struct plat_sci_port scif2_platform_data = {
.port_reg = SCIx_NOT_SUPPORTED,
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
.regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
};
......
......@@ -293,7 +293,6 @@ static struct plat_sci_port scif0_platform_data = {
.port_reg = SCIx_NOT_SUPPORTED,
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
.regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
};
......@@ -317,7 +316,6 @@ static struct plat_sci_port scif1_platform_data = {
.port_reg = SCIx_NOT_SUPPORTED,
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
.regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
};
......@@ -341,7 +339,6 @@ static struct plat_sci_port scif2_platform_data = {
.port_reg = SCIx_NOT_SUPPORTED,
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
.regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
};
......
......@@ -27,7 +27,6 @@
static struct plat_sci_port scif0_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
.regtype = SCIx_SH4_SCIF_REGTYPE,
};
......@@ -50,7 +49,6 @@ static struct platform_device scif0_device = {
static struct plat_sci_port scif1_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
.regtype = SCIx_SH4_SCIF_REGTYPE,
};
......@@ -73,7 +71,6 @@ static struct platform_device scif1_device = {
static struct plat_sci_port scif2_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
.regtype = SCIx_SH4_SCIF_REGTYPE,
};
......@@ -96,7 +93,6 @@ static struct platform_device scif2_device = {
static struct plat_sci_port scif3_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
.regtype = SCIx_SH4_SCIF_REGTYPE,
};
......@@ -119,7 +115,6 @@ static struct platform_device scif3_device = {
static struct plat_sci_port scif4_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
.regtype = SCIx_SH4_SCIF_REGTYPE,
};
......@@ -142,7 +137,6 @@ static struct platform_device scif4_device = {
static struct plat_sci_port scif5_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
.regtype = SCIx_SH4_SCIF_REGTYPE,
};
......
......@@ -26,7 +26,6 @@
static struct plat_sci_port scif2_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
};
......@@ -48,7 +47,6 @@ static struct platform_device scif2_device = {
static struct plat_sci_port scif3_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
};
......@@ -70,7 +68,6 @@ static struct platform_device scif3_device = {
static struct plat_sci_port scif4_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
};
......
......@@ -21,7 +21,6 @@
static struct plat_sci_port scif0_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
.regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
};
......@@ -44,7 +43,6 @@ static struct platform_device scif0_device = {
static struct plat_sci_port scif1_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
.regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
};
......@@ -67,7 +65,6 @@ static struct platform_device scif1_device = {
static struct plat_sci_port scif2_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
.regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
};
......
......@@ -18,7 +18,6 @@
static struct plat_sci_port scif0_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
};
......@@ -40,7 +39,6 @@ static struct platform_device scif0_device = {
static struct plat_sci_port scif1_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
};
......@@ -62,7 +60,6 @@ static struct platform_device scif1_device = {
static struct plat_sci_port scif2_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
};
......@@ -84,7 +81,6 @@ static struct platform_device scif2_device = {
static struct plat_sci_port scif3_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
};
......@@ -106,7 +102,6 @@ static struct platform_device scif3_device = {
static struct plat_sci_port scif4_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
};
......@@ -128,7 +123,6 @@ static struct platform_device scif4_device = {
static struct plat_sci_port scif5_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
};
......@@ -150,7 +144,6 @@ static struct platform_device scif5_device = {
static struct plat_sci_port scif6_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
};
......@@ -172,7 +165,6 @@ static struct platform_device scif6_device = {
static struct plat_sci_port scif7_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
};
......@@ -194,7 +186,6 @@ static struct platform_device scif7_device = {
static struct plat_sci_port scif8_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
};
......@@ -216,7 +207,6 @@ static struct platform_device scif8_device = {
static struct plat_sci_port scif9_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
};
......
......@@ -20,7 +20,6 @@
static struct plat_sci_port scif0_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
.scbrr_algo_id = SCBRR_ALGO_1,
.type = PORT_SCIF,
.regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
};
......@@ -43,7 +42,6 @@ static struct platform_device scif0_device = {
static struct plat_sci_port scif1_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
.scbrr_algo_id = SCBRR_ALGO_1,
.type = PORT_SCIF,
.regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
};
......@@ -419,9 +417,7 @@ void __init plat_early_device_setup(void)
{
if (mach_is_sh2007()) {
scif0_platform_data.scscr &= ~SCSCR_CKE1;
scif0_platform_data.scbrr_algo_id = SCBRR_ALGO_2;
scif1_platform_data.scscr &= ~SCSCR_CKE1;
scif1_platform_data.scbrr_algo_id = SCBRR_ALGO_2;
}
early_platform_add_devices(sh7780_early_devices,
......
......@@ -22,7 +22,6 @@
static struct plat_sci_port scif0_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
.scbrr_algo_id = SCBRR_ALGO_1,
.type = PORT_SCIF,
.regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
};
......@@ -45,7 +44,6 @@ static struct platform_device scif0_device = {
static struct plat_sci_port scif1_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
.scbrr_algo_id = SCBRR_ALGO_1,
.type = PORT_SCIF,
.regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
};
......@@ -68,7 +66,6 @@ static struct platform_device scif1_device = {
static struct plat_sci_port scif2_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
.scbrr_algo_id = SCBRR_ALGO_1,
.type = PORT_SCIF,
.regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
};
......@@ -91,7 +88,6 @@ static struct platform_device scif2_device = {
static struct plat_sci_port scif3_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
.scbrr_algo_id = SCBRR_ALGO_1,
.type = PORT_SCIF,
.regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
};
......@@ -114,7 +110,6 @@ static struct platform_device scif3_device = {
static struct plat_sci_port scif4_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
.scbrr_algo_id = SCBRR_ALGO_1,
.type = PORT_SCIF,
.regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
};
......@@ -137,7 +132,6 @@ static struct platform_device scif4_device = {
static struct plat_sci_port scif5_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
.scbrr_algo_id = SCBRR_ALGO_1,
.type = PORT_SCIF,
.regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
};
......
......@@ -30,7 +30,6 @@
static struct plat_sci_port scif0_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
.scbrr_algo_id = SCBRR_ALGO_1,
.type = PORT_SCIF,
.regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
};
......@@ -59,7 +58,6 @@ static struct platform_device scif0_device = {
static struct plat_sci_port scif1_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
.scbrr_algo_id = SCBRR_ALGO_1,
.type = PORT_SCIF,
.regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
};
......@@ -91,7 +89,6 @@ static struct platform_device scif1_device = {
static struct plat_sci_port scif2_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
.scbrr_algo_id = SCBRR_ALGO_1,
.type = PORT_SCIF,
.regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
};
......@@ -114,7 +111,6 @@ static struct platform_device scif2_device = {
static struct plat_sci_port scif3_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
.scbrr_algo_id = SCBRR_ALGO_1,
.type = PORT_SCIF,
.regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
};
......@@ -137,7 +133,6 @@ static struct platform_device scif3_device = {
static struct plat_sci_port scif4_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
.scbrr_algo_id = SCBRR_ALGO_1,
.type = PORT_SCIF,
.regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
};
......@@ -160,7 +155,6 @@ static struct platform_device scif4_device = {
static struct plat_sci_port scif5_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
.scbrr_algo_id = SCBRR_ALGO_1,
.type = PORT_SCIF,
.regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
};
......
......@@ -30,7 +30,6 @@
static struct plat_sci_port scif0_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
};
......@@ -55,7 +54,6 @@ static struct platform_device scif0_device = {
static struct plat_sci_port scif1_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
};
......@@ -80,7 +78,6 @@ static struct platform_device scif1_device = {
static struct plat_sci_port scif2_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
};
......
......@@ -19,7 +19,6 @@
static struct plat_sci_port scif0_platform_data = {
.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
};
......
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