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cloud-kernel
cloud-kernel
提交 c68dba20 编写于 作者: H Heiko Carstens 提交者： Martin Schwidefsky
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s390/disassembler: add new instructions 

Signed-off-by: NHeiko Carstens <heiko.carstens@de.ibm.com>
上级 991c1505
隐藏空白更改
内联 并排
Showing with 370 addition and 193 deletion
arch/s390/kernel/dis.c
浏览文件 @ c68dba20
...@@ -83,22 +83,29 @@ enum { ...@@ -83,22 +83,29 @@ enum {
U4_12, /* 4 bit unsigned value starting at 12 */ U4_12, /* 4 bit unsigned value starting at 12 */
U4_16, /* 4 bit unsigned value starting at 16 */ U4_16, /* 4 bit unsigned value starting at 16 */
U4_20, /* 4 bit unsigned value starting at 20 */ U4_20, /* 4 bit unsigned value starting at 20 */
U4_24, /* 4 bit unsigned value starting at 24 */
U4_28, /* 4 bit unsigned value starting at 28 */
U4_32, /* 4 bit unsigned value starting at 32 */ U4_32, /* 4 bit unsigned value starting at 32 */
U4_36, /* 4 bit unsigned value starting at 36 */
U8_8, /* 8 bit unsigned value starting at 8 */ U8_8, /* 8 bit unsigned value starting at 8 */
U8_16, /* 8 bit unsigned value starting at 16 */ U8_16, /* 8 bit unsigned value starting at 16 */
U8_24, /* 8 bit unsigned value starting at 24 */ U8_24, /* 8 bit unsigned value starting at 24 */
U8_32, /* 8 bit unsigned value starting at 32 */ U8_32, /* 8 bit unsigned value starting at 32 */
I8_8, /* 8 bit signed value starting at 8 */ I8_8, /* 8 bit signed value starting at 8 */
I8_32, /* 8 bit signed value starting at 32 */ I8_32, /* 8 bit signed value starting at 32 */
J12_12, /* PC relative offset at 12 */
I16_16, /* 16 bit signed value starting at 16 */ I16_16, /* 16 bit signed value starting at 16 */
I16_32, /* 32 bit signed value starting at 16 */ I16_32, /* 32 bit signed value starting at 16 */
U16_16, /* 16 bit unsigned value starting at 16 */ U16_16, /* 16 bit unsigned value starting at 16 */
U16_32, /* 32 bit unsigned value starting at 16 */ U16_32, /* 32 bit unsigned value starting at 16 */
J16_16, /* PC relative jump offset at 16 */ J16_16, /* PC relative jump offset at 16 */
J16_32, /* PC relative offset at 16 */
I24_24, /* 24 bit signed value starting at 24 */
J32_16, /* PC relative long offset at 16 */ J32_16, /* PC relative long offset at 16 */
I32_16, /* 32 bit signed value starting at 16 */ I32_16, /* 32 bit signed value starting at 16 */
U32_16, /* 32 bit unsigned value starting at 16 */ U32_16, /* 32 bit unsigned value starting at 16 */
M_16, /* 4 bit optional mask starting at 16 */ M_16, /* 4 bit optional mask starting at 16 */
M_20, /* 4 bit optional mask starting at 20 */
RO_28, /* optional GPR starting at position 28 */ RO_28, /* optional GPR starting at position 28 */
}; };
...@@ -109,6 +116,8 @@ enum { ...@@ -109,6 +116,8 @@ enum {
enum { enum {
INSTR_INVALID, INSTR_INVALID,
INSTR_E, INSTR_E,
INSTR_IE_UU,
INSTR_MII_UPI,
INSTR_RIE_R0IU, INSTR_RIE_R0UU, INSTR_RIE_RRP, INSTR_RIE_RRPU, INSTR_RIE_R0IU, INSTR_RIE_R0UU, INSTR_RIE_RRP, INSTR_RIE_RRPU,
INSTR_RIE_RRUUU, INSTR_RIE_RUPI, INSTR_RIE_RUPU, INSTR_RIE_RRI0, INSTR_RIE_RRUUU, INSTR_RIE_RUPI, INSTR_RIE_RUPU, INSTR_RIE_RRI0,
INSTR_RIL_RI, INSTR_RIL_RP, INSTR_RIL_RU, INSTR_RIL_UP, INSTR_RIL_RI, INSTR_RIL_RP, INSTR_RIL_RU, INSTR_RIL_UP,
...@@ -118,13 +127,15 @@ enum { ...@@ -118,13 +127,15 @@ enum {
INSTR_RRE_FF, INSTR_RRE_FR, INSTR_RRE_R0, INSTR_RRE_RA, INSTR_RRE_RF, INSTR_RRE_FF, INSTR_RRE_FR, INSTR_RRE_R0, INSTR_RRE_RA, INSTR_RRE_RF,
INSTR_RRE_RR, INSTR_RRE_RR_OPT, INSTR_RRE_RR, INSTR_RRE_RR_OPT,
INSTR_RRF_0UFF, INSTR_RRF_F0FF, INSTR_RRF_F0FF2, INSTR_RRF_F0FR, INSTR_RRF_0UFF, INSTR_RRF_F0FF, INSTR_RRF_F0FF2, INSTR_RRF_F0FR,
INSTR_RRF_FFRU, INSTR_RRF_FUFF, INSTR_RRF_M0RR, INSTR_RRF_R0RR, INSTR_RRF_FFRU, INSTR_RRF_FUFF, INSTR_RRF_FUFF2, INSTR_RRF_M0RR,
INSTR_RRF_R0RR2, INSTR_RRF_RURR, INSTR_RRF_U0FF, INSTR_RRF_U0RF, INSTR_RRF_R0RR, INSTR_RRF_R0RR2, INSTR_RRF_RMRR, INSTR_RRF_RURR,
INSTR_RRF_U0RR, INSTR_RRF_UUFF, INSTR_RRR_F0FF, INSTR_RRS_RRRDU, INSTR_RRF_U0FF, INSTR_RRF_U0RF, INSTR_RRF_U0RR, INSTR_RRF_UUFF,
INSTR_RRF_UUFR, INSTR_RRF_UURF,
INSTR_RRR_F0FF, INSTR_RRS_RRRDU,
INSTR_RR_FF, INSTR_RR_R0, INSTR_RR_RR, INSTR_RR_U0, INSTR_RR_UR, INSTR_RR_FF, INSTR_RR_R0, INSTR_RR_RR, INSTR_RR_U0, INSTR_RR_UR,
INSTR_RSE_CCRD, INSTR_RSE_RRRD, INSTR_RSE_RURD, INSTR_RSE_CCRD, INSTR_RSE_RRRD, INSTR_RSE_RURD,
INSTR_RSI_RRP, INSTR_RSI_RRP,
INSTR_RSL_R0RD, INSTR_RSL_LRDFU, INSTR_RSL_R0RD,
INSTR_RSY_AARD, INSTR_RSY_CCRD, INSTR_RSY_RRRD, INSTR_RSY_RURD, INSTR_RSY_AARD, INSTR_RSY_CCRD, INSTR_RSY_RRRD, INSTR_RSY_RURD,
INSTR_RSY_RDRM, INSTR_RSY_RDRM,
INSTR_RS_AARD, INSTR_RS_CCRD, INSTR_RS_R0RD, INSTR_RS_RRRD, INSTR_RS_AARD, INSTR_RS_CCRD, INSTR_RS_R0RD, INSTR_RS_RRRD,
...@@ -136,6 +147,7 @@ enum { ...@@ -136,6 +147,7 @@ enum {
INSTR_SIL_RDI, INSTR_SIL_RDU, INSTR_SIL_RDI, INSTR_SIL_RDU,
INSTR_SIY_IRD, INSTR_SIY_URD, INSTR_SIY_IRD, INSTR_SIY_URD,
INSTR_SI_URD, INSTR_SI_URD,
INSTR_SMI_U0RDP,
INSTR_SSE_RDRD, INSTR_SSE_RDRD,
INSTR_SSF_RRDRD, INSTR_SSF_RRDRD2, INSTR_SSF_RRDRD, INSTR_SSF_RRDRD2,
INSTR_SS_L0RDRD, INSTR_SS_LIRDRD, INSTR_SS_LLRDRD, INSTR_SS_RRRDRD, INSTR_SS_L0RDRD, INSTR_SS_LIRDRD, INSTR_SS_LLRDRD, INSTR_SS_RRRDRD,
...@@ -191,31 +203,42 @@ static const struct operand operands[] = ...@@ -191,31 +203,42 @@ static const struct operand operands[] =
[U4_12] = { 4, 12, 0 }, [U4_12] = { 4, 12, 0 },
[U4_16] = { 4, 16, 0 }, [U4_16] = { 4, 16, 0 },
[U4_20] = { 4, 20, 0 }, [U4_20] = { 4, 20, 0 },
[U4_24] = { 4, 24, 0 },
[U4_28] = { 4, 28, 0 },
[U4_32] = { 4, 32, 0 }, [U4_32] = { 4, 32, 0 },
[U4_36] = { 4, 36, 0 },
[U8_8] = { 8, 8, 0 }, [U8_8] = { 8, 8, 0 },
[U8_16] = { 8, 16, 0 }, [U8_16] = { 8, 16, 0 },
[U8_24] = { 8, 24, 0 }, [U8_24] = { 8, 24, 0 },
[U8_32] = { 8, 32, 0 }, [U8_32] = { 8, 32, 0 },
[J12_12] = { 12, 12, OPERAND_PCREL },
[I16_16] = { 16, 16, OPERAND_SIGNED }, [I16_16] = { 16, 16, OPERAND_SIGNED },
[U16_16] = { 16, 16, 0 }, [U16_16] = { 16, 16, 0 },
[U16_32] = { 16, 32, 0 }, [U16_32] = { 16, 32, 0 },
[J16_16] = { 16, 16, OPERAND_PCREL }, [J16_16] = { 16, 16, OPERAND_PCREL },
[J16_32] = { 16, 32, OPERAND_PCREL },
[I16_32] = { 16, 32, OPERAND_SIGNED }, [I16_32] = { 16, 32, OPERAND_SIGNED },
[I24_24] = { 24, 24, OPERAND_SIGNED },
[J32_16] = { 32, 16, OPERAND_PCREL }, [J32_16] = { 32, 16, OPERAND_PCREL },
[I32_16] = { 32, 16, OPERAND_SIGNED }, [I32_16] = { 32, 16, OPERAND_SIGNED },
[U32_16] = { 32, 16, 0 }, [U32_16] = { 32, 16, 0 },
[M_16] = { 4, 16, 0 }, [M_16] = { 4, 16, 0 },
[M_20] = { 4, 20, 0 },
[RO_28] = { 4, 28, OPERAND_GPR } [RO_28] = { 4, 28, OPERAND_GPR }
}; };
static const unsigned char formats[][7] = { static const unsigned char formats[][7] = {
[INSTR_E] = { 0xff, 0,0,0,0,0,0 }, [INSTR_E] = { 0xff, 0,0,0,0,0,0 },
[INSTR_IE_UU] = { 0xff, U4_24,U4_28,0,0,0,0 },
[INSTR_MII_UPI] = { 0xff, U4_8,J12_12,I24_24 },
[INSTR_RIE_R0IU] = { 0xff, R_8,I16_16,U4_32,0,0,0 },
[INSTR_RIE_R0UU] = { 0xff, R_8,U16_16,U4_32,0,0,0 }, [INSTR_RIE_R0UU] = { 0xff, R_8,U16_16,U4_32,0,0,0 },
[INSTR_RIE_RRI0] = { 0xff, R_8,R_12,I16_16,0,0,0 },
[INSTR_RIE_RRPU] = { 0xff, R_8,R_12,U4_32,J16_16,0,0 }, [INSTR_RIE_RRPU] = { 0xff, R_8,R_12,U4_32,J16_16,0,0 },
[INSTR_RIE_RRP] = { 0xff, R_8,R_12,J16_16,0,0,0 }, [INSTR_RIE_RRP] = { 0xff, R_8,R_12,J16_16,0,0,0 },
[INSTR_RIE_RRUUU] = { 0xff, R_8,R_12,U8_16,U8_24,U8_32,0 }, [INSTR_RIE_RRUUU] = { 0xff, R_8,R_12,U8_16,U8_24,U8_32,0 },
[INSTR_RIE_RUPI] = { 0xff, R_8,I8_32,U4_12,J16_16,0,0 }, [INSTR_RIE_RUPI] = { 0xff, R_8,I8_32,U4_12,J16_16,0,0 },
[INSTR_RIE_RRI0] = { 0xff, R_8,R_12,I16_16,0,0,0 }, [INSTR_RIE_RUPU] = { 0xff, R_8,U8_32,U4_12,J16_16,0,0 },
[INSTR_RIL_RI] = { 0x0f, R_8,I32_16,0,0,0,0 }, [INSTR_RIL_RI] = { 0x0f, R_8,I32_16,0,0,0,0 },
[INSTR_RIL_RP] = { 0x0f, R_8,J32_16,0,0,0,0 }, [INSTR_RIL_RP] = { 0x0f, R_8,J32_16,0,0,0,0 },
[INSTR_RIL_RU] = { 0x0f, R_8,U32_16,0,0,0,0 }, [INSTR_RIL_RU] = { 0x0f, R_8,U32_16,0,0,0,0 },
...@@ -245,14 +268,18 @@ static const unsigned char formats[][7] = { ...@@ -245,14 +268,18 @@ static const unsigned char formats[][7] = {
[INSTR_RRF_F0FR] = { 0xff, F_24,F_16,R_28,0,0,0 }, [INSTR_RRF_F0FR] = { 0xff, F_24,F_16,R_28,0,0,0 },
[INSTR_RRF_FFRU] = { 0xff, F_24,F_16,R_28,U4_20,0,0 }, [INSTR_RRF_FFRU] = { 0xff, F_24,F_16,R_28,U4_20,0,0 },
[INSTR_RRF_FUFF] = { 0xff, F_24,F_16,F_28,U4_20,0,0 }, [INSTR_RRF_FUFF] = { 0xff, F_24,F_16,F_28,U4_20,0,0 },
[INSTR_RRF_FUFF2] = { 0xff, F_24,F_28,F_16,U4_20,0,0 },
[INSTR_RRF_M0RR] = { 0xff, R_24,R_28,M_16,0,0,0 }, [INSTR_RRF_M0RR] = { 0xff, R_24,R_28,M_16,0,0,0 },
[INSTR_RRF_R0RR] = { 0xff, R_24,R_16,R_28,0,0,0 }, [INSTR_RRF_R0RR] = { 0xff, R_24,R_16,R_28,0,0,0 },
[INSTR_RRF_R0RR2] = { 0xff, R_24,R_28,R_16,0,0,0 }, [INSTR_RRF_R0RR2] = { 0xff, R_24,R_28,R_16,0,0,0 },
[INSTR_RRF_RMRR] = { 0xff, R_24,R_16,R_28,M_20,0,0 },
[INSTR_RRF_RURR] = { 0xff, R_24,R_28,R_16,U4_20,0,0 }, [INSTR_RRF_RURR] = { 0xff, R_24,R_28,R_16,U4_20,0,0 },
[INSTR_RRF_U0FF] = { 0xff, F_24,U4_16,F_28,0,0,0 }, [INSTR_RRF_U0FF] = { 0xff, F_24,U4_16,F_28,0,0,0 },
[INSTR_RRF_U0RF] = { 0xff, R_24,U4_16,F_28,0,0,0 }, [INSTR_RRF_U0RF] = { 0xff, R_24,U4_16,F_28,0,0,0 },
[INSTR_RRF_U0RR] = { 0xff, R_24,R_28,U4_16,0,0,0 }, [INSTR_RRF_U0RR] = { 0xff, R_24,R_28,U4_16,0,0,0 },
[INSTR_RRF_UUFF] = { 0xff, F_24,U4_16,F_28,U4_20,0,0 }, [INSTR_RRF_UUFF] = { 0xff, F_24,U4_16,F_28,U4_20,0,0 },
[INSTR_RRF_UUFR] = { 0xff, F_24,U4_16,R_28,U4_20,0,0 },
[INSTR_RRF_UURF] = { 0xff, R_24,U4_16,F_28,U4_20,0,0 },
[INSTR_RRR_F0FF] = { 0xff, F_24,F_28,F_16,0,0,0 }, [INSTR_RRR_F0FF] = { 0xff, F_24,F_28,F_16,0,0,0 },
[INSTR_RRS_RRRDU] = { 0xff, R_8,R_12,U4_32,D_20,B_16,0 }, [INSTR_RRS_RRRDU] = { 0xff, R_8,R_12,U4_32,D_20,B_16,0 },
[INSTR_RR_FF] = { 0xff, F_8,F_12,0,0,0,0 }, [INSTR_RR_FF] = { 0xff, F_8,F_12,0,0,0,0 },
...@@ -264,12 +291,13 @@ static const unsigned char formats[][7] = { ...@@ -264,12 +291,13 @@ static const unsigned char formats[][7] = {
[INSTR_RSE_RRRD] = { 0xff, R_8,R_12,D_20,B_16,0,0 }, [INSTR_RSE_RRRD] = { 0xff, R_8,R_12,D_20,B_16,0,0 },
[INSTR_RSE_RURD] = { 0xff, R_8,U4_12,D_20,B_16,0,0 }, [INSTR_RSE_RURD] = { 0xff, R_8,U4_12,D_20,B_16,0,0 },
[INSTR_RSI_RRP] = { 0xff, R_8,R_12,J16_16,0,0,0 }, [INSTR_RSI_RRP] = { 0xff, R_8,R_12,J16_16,0,0,0 },
[INSTR_RSL_LRDFU] = { 0xff, F_32,D_20,L4_8,B_16,U4_36,0 },
[INSTR_RSL_R0RD] = { 0xff, D_20,L4_8,B_16,0,0,0 }, [INSTR_RSL_R0RD] = { 0xff, D_20,L4_8,B_16,0,0,0 },
[INSTR_RSY_AARD] = { 0xff, A_8,A_12,D20_20,B_16,0,0 }, [INSTR_RSY_AARD] = { 0xff, A_8,A_12,D20_20,B_16,0,0 },
[INSTR_RSY_CCRD] = { 0xff, C_8,C_12,D20_20,B_16,0,0 }, [INSTR_RSY_CCRD] = { 0xff, C_8,C_12,D20_20,B_16,0,0 },
[INSTR_RSY_RDRM] = { 0xff, R_8,D20_20,B_16,U4_12,0,0 },
[INSTR_RSY_RRRD] = { 0xff, R_8,R_12,D20_20,B_16,0,0 }, [INSTR_RSY_RRRD] = { 0xff, R_8,R_12,D20_20,B_16,0,0 },
[INSTR_RSY_RURD] = { 0xff, R_8,U4_12,D20_20,B_16,0,0 }, [INSTR_RSY_RURD] = { 0xff, R_8,U4_12,D20_20,B_16,0,0 },
[INSTR_RSY_RDRM] = { 0xff, R_8,D20_20,B_16,U4_12,0,0 },
[INSTR_RS_AARD] = { 0xff, A_8,A_12,D_20,B_16,0,0 }, [INSTR_RS_AARD] = { 0xff, A_8,A_12,D_20,B_16,0,0 },
[INSTR_RS_CCRD] = { 0xff, C_8,C_12,D_20,B_16,0,0 }, [INSTR_RS_CCRD] = { 0xff, C_8,C_12,D_20,B_16,0,0 },
[INSTR_RS_R0RD] = { 0xff, R_8,D_20,B_16,0,0,0 }, [INSTR_RS_R0RD] = { 0xff, R_8,D_20,B_16,0,0,0 },
...@@ -289,9 +317,10 @@ static const unsigned char formats[][7] = { ...@@ -289,9 +317,10 @@ static const unsigned char formats[][7] = {
[INSTR_SIY_IRD] = { 0xff, D20_20,B_16,I8_8,0,0,0 }, [INSTR_SIY_IRD] = { 0xff, D20_20,B_16,I8_8,0,0,0 },
[INSTR_SIY_URD] = { 0xff, D20_20,B_16,U8_8,0,0,0 }, [INSTR_SIY_URD] = { 0xff, D20_20,B_16,U8_8,0,0,0 },
[INSTR_SI_URD] = { 0xff, D_20,B_16,U8_8,0,0,0 }, [INSTR_SI_URD] = { 0xff, D_20,B_16,U8_8,0,0,0 },
[INSTR_SMI_U0RDP] = { 0xff, U4_8,J16_32,D_20,B_16,0,0 },
[INSTR_SSE_RDRD] = { 0xff, D_20,B_16,D_36,B_32,0,0 }, [INSTR_SSE_RDRD] = { 0xff, D_20,B_16,D_36,B_32,0,0 },
[INSTR_SSF_RRDRD] = { 0x00, D_20,B_16,D_36,B_32,R_8,0 }, [INSTR_SSF_RRDRD] = { 0x0f, D_20,B_16,D_36,B_32,R_8,0 },
[INSTR_SSF_RRDRD2]= { 0x00, R_8,D_20,B_16,D_36,B_32,0 }, [INSTR_SSF_RRDRD2]= { 0x0f, R_8,D_20,B_16,D_36,B_32,0 },
[INSTR_SS_L0RDRD] = { 0xff, D_20,L8_8,B_16,D_36,B_32,0 }, [INSTR_SS_L0RDRD] = { 0xff, D_20,L8_8,B_16,D_36,B_32,0 },
[INSTR_SS_LIRDRD] = { 0xff, D_20,L4_8,B_16,D_36,B_32,U4_12 }, [INSTR_SS_LIRDRD] = { 0xff, D_20,L4_8,B_16,D_36,B_32,U4_12 },
[INSTR_SS_LLRDRD] = { 0xff, D_20,L4_8,B_16,D_36,L4_12,B_32 }, [INSTR_SS_LLRDRD] = { 0xff, D_20,L4_8,B_16,D_36,L4_12,B_32 },
...@@ -304,19 +333,69 @@ static const unsigned char formats[][7] = { ...@@ -304,19 +333,69 @@ static const unsigned char formats[][7] = {
enum { enum {
LONG_INSN_ALGHSIK, LONG_INSN_ALGHSIK,
LONG_INSN_ALHHHR,
LONG_INSN_ALHHLR,
LONG_INSN_ALHSIK, LONG_INSN_ALHSIK,
LONG_INSN_ALSIHN,
LONG_INSN_CDFBRA,
LONG_INSN_CDGBRA,
LONG_INSN_CDGTRA,
LONG_INSN_CDLFBR,
LONG_INSN_CDLFTR,
LONG_INSN_CDLGBR,
LONG_INSN_CDLGTR,
LONG_INSN_CEFBRA,
LONG_INSN_CEGBRA,
LONG_INSN_CELFBR,
LONG_INSN_CELGBR,
LONG_INSN_CFDBRA,
LONG_INSN_CFEBRA,
LONG_INSN_CFXBRA,
LONG_INSN_CGDBRA,
LONG_INSN_CGDTRA,
LONG_INSN_CGEBRA,
LONG_INSN_CGXBRA,
LONG_INSN_CGXTRA,
LONG_INSN_CLFDBR,
LONG_INSN_CLFDTR,
LONG_INSN_CLFEBR,
LONG_INSN_CLFHSI, LONG_INSN_CLFHSI,
LONG_INSN_CLFXBR,
LONG_INSN_CLFXTR,
LONG_INSN_CLGDBR,
LONG_INSN_CLGDTR,
LONG_INSN_CLGEBR,
LONG_INSN_CLGFRL, LONG_INSN_CLGFRL,
LONG_INSN_CLGHRL, LONG_INSN_CLGHRL,
LONG_INSN_CLGHSI, LONG_INSN_CLGHSI,
LONG_INSN_CLGXBR,
LONG_INSN_CLGXTR,
LONG_INSN_CLHHSI, LONG_INSN_CLHHSI,
LONG_INSN_CXFBRA,
LONG_INSN_CXGBRA,
LONG_INSN_CXGTRA,
LONG_INSN_CXLFBR,
LONG_INSN_CXLFTR,
LONG_INSN_CXLGBR,
LONG_INSN_CXLGTR,
LONG_INSN_FIDBRA,
LONG_INSN_FIEBRA,
LONG_INSN_FIXBRA,
LONG_INSN_LDXBRA,
LONG_INSN_LEDBRA,
LONG_INSN_LEXBRA,
LONG_INSN_LLGFAT,
LONG_INSN_LLGFRL, LONG_INSN_LLGFRL,
LONG_INSN_LLGHRL, LONG_INSN_LLGHRL,
LONG_INSN_LLGTAT,
LONG_INSN_POPCNT, LONG_INSN_POPCNT,
LONG_INSN_RIEMIT,
LONG_INSN_RINEXT,
LONG_INSN_RISBGN,
LONG_INSN_RISBHG, LONG_INSN_RISBHG,
LONG_INSN_RISBLG, LONG_INSN_RISBLG,
LONG_INSN_RINEXT, LONG_INSN_SLHHHR,
LONG_INSN_RIEMIT, LONG_INSN_SLHHLR,
LONG_INSN_TABORT, LONG_INSN_TABORT,
LONG_INSN_TBEGIN, LONG_INSN_TBEGIN,
LONG_INSN_TBEGINC, LONG_INSN_TBEGINC,
...@@ -324,19 +403,69 @@ enum { ...@@ -324,19 +403,69 @@ enum {
static char *long_insn_name[] = { static char *long_insn_name[] = {
[LONG_INSN_ALGHSIK] = "alghsik", [LONG_INSN_ALGHSIK] = "alghsik",
[LONG_INSN_ALHHHR] = "alhhhr",
[LONG_INSN_ALHHLR] = "alhhlr",
[LONG_INSN_ALHSIK] = "alhsik", [LONG_INSN_ALHSIK] = "alhsik",
[LONG_INSN_ALSIHN] = "alsihn",
[LONG_INSN_CDFBRA] = "cdfbra",
[LONG_INSN_CDGBRA] = "cdgbra",
[LONG_INSN_CDGTRA] = "cdgtra",
[LONG_INSN_CDLFBR] = "cdlfbr",
[LONG_INSN_CDLFTR] = "cdlftr",
[LONG_INSN_CDLGBR] = "cdlgbr",
[LONG_INSN_CDLGTR] = "cdlgtr",
[LONG_INSN_CEFBRA] = "cefbra",
[LONG_INSN_CEGBRA] = "cegbra",
[LONG_INSN_CELFBR] = "celfbr",
[LONG_INSN_CELGBR] = "celgbr",
[LONG_INSN_CFDBRA] = "cfdbra",
[LONG_INSN_CFEBRA] = "cfebra",
[LONG_INSN_CFXBRA] = "cfxbra",
[LONG_INSN_CGDBRA] = "cgdbra",
[LONG_INSN_CGDTRA] = "cgdtra",
[LONG_INSN_CGEBRA] = "cgebra",
[LONG_INSN_CGXBRA] = "cgxbra",
[LONG_INSN_CGXTRA] = "cgxtra",
[LONG_INSN_CLFDBR] = "clfdbr",
[LONG_INSN_CLFDTR] = "clfdtr",
[LONG_INSN_CLFEBR] = "clfebr",
[LONG_INSN_CLFHSI] = "clfhsi", [LONG_INSN_CLFHSI] = "clfhsi",
[LONG_INSN_CLFXBR] = "clfxbr",
[LONG_INSN_CLFXTR] = "clfxtr",
[LONG_INSN_CLGDBR] = "clgdbr",
[LONG_INSN_CLGDTR] = "clgdtr",
[LONG_INSN_CLGEBR] = "clgebr",
[LONG_INSN_CLGFRL] = "clgfrl", [LONG_INSN_CLGFRL] = "clgfrl",
[LONG_INSN_CLGHRL] = "clghrl", [LONG_INSN_CLGHRL] = "clghrl",
[LONG_INSN_CLGHSI] = "clghsi", [LONG_INSN_CLGHSI] = "clghsi",
[LONG_INSN_CLGXBR] = "clgxbr",
[LONG_INSN_CLGXTR] = "clgxtr",
[LONG_INSN_CLHHSI] = "clhhsi", [LONG_INSN_CLHHSI] = "clhhsi",
[LONG_INSN_CXFBRA] = "cxfbra",
[LONG_INSN_CXGBRA] = "cxgbra",
[LONG_INSN_CXGTRA] = "cxgtra",
[LONG_INSN_CXLFBR] = "cxlfbr",
[LONG_INSN_CXLFTR] = "cxlftr",
[LONG_INSN_CXLGBR] = "cxlgbr",
[LONG_INSN_CXLGTR] = "cxlgtr",
[LONG_INSN_FIDBRA] = "fidbra",
[LONG_INSN_FIEBRA] = "fiebra",
[LONG_INSN_FIXBRA] = "fixbra",
[LONG_INSN_LDXBRA] = "ldxbra",
[LONG_INSN_LEDBRA] = "ledbra",
[LONG_INSN_LEXBRA] = "lexbra",
[LONG_INSN_LLGFAT] = "llgfat",
[LONG_INSN_LLGFRL] = "llgfrl", [LONG_INSN_LLGFRL] = "llgfrl",
[LONG_INSN_LLGHRL] = "llghrl", [LONG_INSN_LLGHRL] = "llghrl",
[LONG_INSN_LLGTAT] = "llgtat",
[LONG_INSN_POPCNT] = "popcnt", [LONG_INSN_POPCNT] = "popcnt",
[LONG_INSN_RIEMIT] = "riemit",
[LONG_INSN_RINEXT] = "rinext",
[LONG_INSN_RISBGN] = "risbgn",
[LONG_INSN_RISBHG] = "risbhg", [LONG_INSN_RISBHG] = "risbhg",
[LONG_INSN_RISBLG] = "risblg", [LONG_INSN_RISBLG] = "risblg",
[LONG_INSN_RINEXT] = "rinext", [LONG_INSN_SLHHHR] = "slhhhr",
[LONG_INSN_RIEMIT] = "riemit", [LONG_INSN_SLHHLR] = "slhhlr",
[LONG_INSN_TABORT] = "tabort", [LONG_INSN_TABORT] = "tabort",
[LONG_INSN_TBEGIN] = "tbegin", [LONG_INSN_TBEGIN] = "tbegin",
[LONG_INSN_TBEGINC] = "tbeginc", [LONG_INSN_TBEGINC] = "tbeginc",
...@@ -344,6 +473,9 @@ static char *long_insn_name[] = { ...@@ -344,6 +473,9 @@ static char *long_insn_name[] = {
static struct insn opcode[] = { static struct insn opcode[] = {
#ifdef CONFIG_64BIT #ifdef CONFIG_64BIT
{ "bprp", 0xc5, INSTR_MII_UPI },
{ "bpp", 0xc7, INSTR_SMI_U0RDP },
{ "trtr", 0xd0, INSTR_SS_L0RDRD },
{ "lmd", 0xef, INSTR_SS_RRRDRD3 }, { "lmd", 0xef, INSTR_SS_RRRDRD3 },
#endif #endif
{ "spm", 0x04, INSTR_RR_R0 }, { "spm", 0x04, INSTR_RR_R0 },
...@@ -378,7 +510,6 @@ static struct insn opcode[] = { ...@@ -378,7 +510,6 @@ static struct insn opcode[] = {
{ "lcdr", 0x23, INSTR_RR_FF }, { "lcdr", 0x23, INSTR_RR_FF },
{ "hdr", 0x24, INSTR_RR_FF }, { "hdr", 0x24, INSTR_RR_FF },
{ "ldxr", 0x25, INSTR_RR_FF }, { "ldxr", 0x25, INSTR_RR_FF },
{ "lrdr", 0x25, INSTR_RR_FF },
{ "mxr", 0x26, INSTR_RR_FF }, { "mxr", 0x26, INSTR_RR_FF },
{ "mxdr", 0x27, INSTR_RR_FF }, { "mxdr", 0x27, INSTR_RR_FF },
{ "ldr", 0x28, INSTR_RR_FF }, { "ldr", 0x28, INSTR_RR_FF },
...@@ -395,7 +526,6 @@ static struct insn opcode[] = { ...@@ -395,7 +526,6 @@ static struct insn opcode[] = {
{ "lcer", 0x33, INSTR_RR_FF }, { "lcer", 0x33, INSTR_RR_FF },
{ "her", 0x34, INSTR_RR_FF }, { "her", 0x34, INSTR_RR_FF },
{ "ledr", 0x35, INSTR_RR_FF }, { "ledr", 0x35, INSTR_RR_FF },
{ "lrer", 0x35, INSTR_RR_FF },
{ "axr", 0x36, INSTR_RR_FF }, { "axr", 0x36, INSTR_RR_FF },
{ "sxr", 0x37, INSTR_RR_FF }, { "sxr", 0x37, INSTR_RR_FF },
{ "ler", 0x38, INSTR_RR_FF }, { "ler", 0x38, INSTR_RR_FF },
...@@ -403,7 +533,6 @@ static struct insn opcode[] = { ...@@ -403,7 +533,6 @@ static struct insn opcode[] = {
{ "aer", 0x3a, INSTR_RR_FF }, { "aer", 0x3a, INSTR_RR_FF },
{ "ser", 0x3b, INSTR_RR_FF }, { "ser", 0x3b, INSTR_RR_FF },
{ "mder", 0x3c, INSTR_RR_FF }, { "mder", 0x3c, INSTR_RR_FF },
{ "mer", 0x3c, INSTR_RR_FF },
{ "der", 0x3d, INSTR_RR_FF }, { "der", 0x3d, INSTR_RR_FF },
{ "aur", 0x3e, INSTR_RR_FF }, { "aur", 0x3e, INSTR_RR_FF },
{ "sur", 0x3f, INSTR_RR_FF }, { "sur", 0x3f, INSTR_RR_FF },
...@@ -454,7 +583,6 @@ static struct insn opcode[] = { ...@@ -454,7 +583,6 @@ static struct insn opcode[] = {
{ "ae", 0x7a, INSTR_RX_FRRD }, { "ae", 0x7a, INSTR_RX_FRRD },
{ "se", 0x7b, INSTR_RX_FRRD }, { "se", 0x7b, INSTR_RX_FRRD },
{ "mde", 0x7c, INSTR_RX_FRRD }, { "mde", 0x7c, INSTR_RX_FRRD },
{ "me", 0x7c, INSTR_RX_FRRD },
{ "de", 0x7d, INSTR_RX_FRRD }, { "de", 0x7d, INSTR_RX_FRRD },
{ "au", 0x7e, INSTR_RX_FRRD }, { "au", 0x7e, INSTR_RX_FRRD },
{ "su", 0x7f, INSTR_RX_FRRD }, { "su", 0x7f, INSTR_RX_FRRD },
...@@ -534,9 +662,9 @@ static struct insn opcode[] = { ...@@ -534,9 +662,9 @@ static struct insn opcode[] = {
static struct insn opcode_01[] = { static struct insn opcode_01[] = {
#ifdef CONFIG_64BIT #ifdef CONFIG_64BIT
{ "sam64", 0x0e, INSTR_E },
{ "pfpo", 0x0a, INSTR_E },
{ "ptff", 0x04, INSTR_E }, { "ptff", 0x04, INSTR_E },
{ "pfpo", 0x0a, INSTR_E },
{ "sam64", 0x0e, INSTR_E },
#endif #endif
{ "pr", 0x01, INSTR_E }, { "pr", 0x01, INSTR_E },
{ "upt", 0x02, INSTR_E }, { "upt", 0x02, INSTR_E },
...@@ -605,19 +733,28 @@ static struct insn opcode_aa[] = { ...@@ -605,19 +733,28 @@ static struct insn opcode_aa[] = {
static struct insn opcode_b2[] = { static struct insn opcode_b2[] = {
#ifdef CONFIG_64BIT #ifdef CONFIG_64BIT
{ "sske", 0x2b, INSTR_RRF_M0RR },
{ "stckf", 0x7c, INSTR_S_RD }, { "stckf", 0x7c, INSTR_S_RD },
{ "cu21", 0xa6, INSTR_RRF_M0RR }, { "lpp", 0x80, INSTR_S_RD },
{ "cuutf", 0xa6, INSTR_RRF_M0RR }, { "lcctl", 0x84, INSTR_S_RD },
{ "cu12", 0xa7, INSTR_RRF_M0RR }, { "lpctl", 0x85, INSTR_S_RD },
{ "cutfu", 0xa7, INSTR_RRF_M0RR }, { "qsi", 0x86, INSTR_S_RD },
{ "lsctl", 0x87, INSTR_S_RD },
{ "qctri", 0x8e, INSTR_S_RD },
{ "stfle", 0xb0, INSTR_S_RD }, { "stfle", 0xb0, INSTR_S_RD },
{ "lpswe", 0xb2, INSTR_S_RD }, { "lpswe", 0xb2, INSTR_S_RD },
{ "srnmb", 0xb8, INSTR_S_RD },
{ "srnmt", 0xb9, INSTR_S_RD }, { "srnmt", 0xb9, INSTR_S_RD },
{ "lfas", 0xbd, INSTR_S_RD }, { "lfas", 0xbd, INSTR_S_RD },
{ "etndg", 0xec, INSTR_RRE_R0 }, { "scctr", 0xe0, INSTR_RRE_RR },
{ "spctr", 0xe1, INSTR_RRE_RR },
{ "ecctr", 0xe4, INSTR_RRE_RR },
{ "epctr", 0xe5, INSTR_RRE_RR },
{ "ppa", 0xe8, INSTR_RRF_U0RR },
{ "etnd", 0xec, INSTR_RRE_R0 },
{ "ecpga", 0xed, INSTR_RRE_RR },
{ "tend", 0xf8, INSTR_S_00 },
{ "niai", 0xfa, INSTR_IE_UU },
{ { 0, LONG_INSN_TABORT }, 0xfc, INSTR_S_RD }, { { 0, LONG_INSN_TABORT }, 0xfc, INSTR_S_RD },
{ "tend", 0xf8, INSTR_S_RD },
#endif #endif
{ "stidp", 0x02, INSTR_S_RD }, { "stidp", 0x02, INSTR_S_RD },
{ "sck", 0x04, INSTR_S_RD }, { "sck", 0x04, INSTR_S_RD },
...@@ -635,8 +772,8 @@ static struct insn opcode_b2[] = { ...@@ -635,8 +772,8 @@ static struct insn opcode_b2[] = {
{ "sie", 0x14, INSTR_S_RD }, { "sie", 0x14, INSTR_S_RD },
{ "pc", 0x18, INSTR_S_RD }, { "pc", 0x18, INSTR_S_RD },
{ "sac", 0x19, INSTR_S_RD }, { "sac", 0x19, INSTR_S_RD },
{ "servc", 0x20, INSTR_RRE_RR },
{ "cfc", 0x1a, INSTR_S_RD }, { "cfc", 0x1a, INSTR_S_RD },
{ "servc", 0x20, INSTR_RRE_RR },
{ "ipte", 0x21, INSTR_RRE_RR }, { "ipte", 0x21, INSTR_RRE_RR },
{ "ipm", 0x22, INSTR_RRE_R0 }, { "ipm", 0x22, INSTR_RRE_R0 },
{ "ivsk", 0x23, INSTR_RRE_RR }, { "ivsk", 0x23, INSTR_RRE_RR },
...@@ -647,9 +784,9 @@ static struct insn opcode_b2[] = { ...@@ -647,9 +784,9 @@ static struct insn opcode_b2[] = {
{ "pt", 0x28, INSTR_RRE_RR }, { "pt", 0x28, INSTR_RRE_RR },
{ "iske", 0x29, INSTR_RRE_RR }, { "iske", 0x29, INSTR_RRE_RR },
{ "rrbe", 0x2a, INSTR_RRE_RR }, { "rrbe", 0x2a, INSTR_RRE_RR },
{ "sske", 0x2b, INSTR_RRE_RR }, { "sske", 0x2b, INSTR_RRF_M0RR },
{ "tb", 0x2c, INSTR_RRE_0R }, { "tb", 0x2c, INSTR_RRE_0R },
{ "dxr", 0x2d, INSTR_RRE_F0 }, { "dxr", 0x2d, INSTR_RRE_FF },
{ "pgin", 0x2e, INSTR_RRE_RR }, { "pgin", 0x2e, INSTR_RRE_RR },
{ "pgout", 0x2f, INSTR_RRE_RR }, { "pgout", 0x2f, INSTR_RRE_RR },
{ "csch", 0x30, INSTR_S_00 }, { "csch", 0x30, INSTR_S_00 },
...@@ -667,8 +804,8 @@ static struct insn opcode_b2[] = { ...@@ -667,8 +804,8 @@ static struct insn opcode_b2[] = {
{ "schm", 0x3c, INSTR_S_00 }, { "schm", 0x3c, INSTR_S_00 },
{ "bakr", 0x40, INSTR_RRE_RR }, { "bakr", 0x40, INSTR_RRE_RR },
{ "cksm", 0x41, INSTR_RRE_RR }, { "cksm", 0x41, INSTR_RRE_RR },
{ "sqdr", 0x44, INSTR_RRE_F0 }, { "sqdr", 0x44, INSTR_RRE_FF },
{ "sqer", 0x45, INSTR_RRE_F0 }, { "sqer", 0x45, INSTR_RRE_FF },
{ "stura", 0x46, INSTR_RRE_RR }, { "stura", 0x46, INSTR_RRE_RR },
{ "msta", 0x47, INSTR_RRE_R0 }, { "msta", 0x47, INSTR_RRE_R0 },
{ "palb", 0x48, INSTR_RRE_00 }, { "palb", 0x48, INSTR_RRE_00 },
...@@ -694,14 +831,14 @@ static struct insn opcode_b2[] = { ...@@ -694,14 +831,14 @@ static struct insn opcode_b2[] = {
{ "rp", 0x77, INSTR_S_RD }, { "rp", 0x77, INSTR_S_RD },
{ "stcke", 0x78, INSTR_S_RD }, { "stcke", 0x78, INSTR_S_RD },
{ "sacf", 0x79, INSTR_S_RD }, { "sacf", 0x79, INSTR_S_RD },
{ "spp", 0x80, INSTR_S_RD },
{ "stsi", 0x7d, INSTR_S_RD }, { "stsi", 0x7d, INSTR_S_RD },
{ "spp", 0x80, INSTR_S_RD },
{ "srnm", 0x99, INSTR_S_RD }, { "srnm", 0x99, INSTR_S_RD },
{ "stfpc", 0x9c, INSTR_S_RD }, { "stfpc", 0x9c, INSTR_S_RD },
{ "lfpc", 0x9d, INSTR_S_RD }, { "lfpc", 0x9d, INSTR_S_RD },
{ "tre", 0xa5, INSTR_RRE_RR }, { "tre", 0xa5, INSTR_RRE_RR },
{ "cuutf", 0xa6, INSTR_RRE_RR }, { "cuutf", 0xa6, INSTR_RRF_M0RR },
{ "cutfu", 0xa7, INSTR_RRE_RR }, { "cutfu", 0xa7, INSTR_RRF_M0RR },
{ "stfl", 0xb1, INSTR_S_RD }, { "stfl", 0xb1, INSTR_S_RD },
{ "trap4", 0xff, INSTR_S_RD }, { "trap4", 0xff, INSTR_S_RD },
{ "", 0, INSTR_INVALID } { "", 0, INSTR_INVALID }
...@@ -715,72 +852,87 @@ static struct insn opcode_b3[] = { ...@@ -715,72 +852,87 @@ static struct insn opcode_b3[] = {
{ "myr", 0x3b, INSTR_RRF_F0FF }, { "myr", 0x3b, INSTR_RRF_F0FF },
{ "mayhr", 0x3c, INSTR_RRF_F0FF }, { "mayhr", 0x3c, INSTR_RRF_F0FF },
{ "myhr", 0x3d, INSTR_RRF_F0FF }, { "myhr", 0x3d, INSTR_RRF_F0FF },
{ "cegbr", 0xa4, INSTR_RRE_RR },
{ "cdgbr", 0xa5, INSTR_RRE_RR },
{ "cxgbr", 0xa6, INSTR_RRE_RR },
{ "cgebr", 0xa8, INSTR_RRF_U0RF },
{ "cgdbr", 0xa9, INSTR_RRF_U0RF },
{ "cgxbr", 0xaa, INSTR_RRF_U0RF },
{ "cfer", 0xb8, INSTR_RRF_U0RF },
{ "cfdr", 0xb9, INSTR_RRF_U0RF },
{ "cfxr", 0xba, INSTR_RRF_U0RF },
{ "cegr", 0xc4, INSTR_RRE_RR },
{ "cdgr", 0xc5, INSTR_RRE_RR },
{ "cxgr", 0xc6, INSTR_RRE_RR },
{ "cger", 0xc8, INSTR_RRF_U0RF },
{ "cgdr", 0xc9, INSTR_RRF_U0RF },
{ "cgxr", 0xca, INSTR_RRF_U0RF },
{ "lpdfr", 0x70, INSTR_RRE_FF }, { "lpdfr", 0x70, INSTR_RRE_FF },
{ "lndfr", 0x71, INSTR_RRE_FF }, { "lndfr", 0x71, INSTR_RRE_FF },
{ "cpsdr", 0x72, INSTR_RRF_F0FF2 }, { "cpsdr", 0x72, INSTR_RRF_F0FF2 },
{ "lcdfr", 0x73, INSTR_RRE_FF }, { "lcdfr", 0x73, INSTR_RRE_FF },
{ "sfasr", 0x85, INSTR_RRE_R0 },
{ { 0, LONG_INSN_CELFBR }, 0x90, INSTR_RRF_UUFR },
{ { 0, LONG_INSN_CDLFBR }, 0x91, INSTR_RRF_UUFR },
{ { 0, LONG_INSN_CXLFBR }, 0x92, INSTR_RRF_UURF },
{ { 0, LONG_INSN_CEFBRA }, 0x94, INSTR_RRF_UUFR },
{ { 0, LONG_INSN_CDFBRA }, 0x95, INSTR_RRF_UUFR },
{ { 0, LONG_INSN_CXFBRA }, 0x96, INSTR_RRF_UURF },
{ { 0, LONG_INSN_CFEBRA }, 0x98, INSTR_RRF_UURF },
{ { 0, LONG_INSN_CFDBRA }, 0x99, INSTR_RRF_UURF },
{ { 0, LONG_INSN_CFXBRA }, 0x9a, INSTR_RRF_UUFR },
{ { 0, LONG_INSN_CLFEBR }, 0x9c, INSTR_RRF_UURF },
{ { 0, LONG_INSN_CLFDBR }, 0x9d, INSTR_RRF_UURF },
{ { 0, LONG_INSN_CLFXBR }, 0x9e, INSTR_RRF_UUFR },
{ { 0, LONG_INSN_CELGBR }, 0xa0, INSTR_RRF_UUFR },
{ { 0, LONG_INSN_CDLGBR }, 0xa1, INSTR_RRF_UUFR },
{ { 0, LONG_INSN_CXLGBR }, 0xa2, INSTR_RRF_UURF },
{ { 0, LONG_INSN_CEGBRA }, 0xa4, INSTR_RRF_UUFR },
{ { 0, LONG_INSN_CDGBRA }, 0xa5, INSTR_RRF_UUFR },
{ { 0, LONG_INSN_CXGBRA }, 0xa6, INSTR_RRF_UURF },
{ { 0, LONG_INSN_CGEBRA }, 0xa8, INSTR_RRF_UURF },
{ { 0, LONG_INSN_CGDBRA }, 0xa9, INSTR_RRF_UURF },
{ { 0, LONG_INSN_CGXBRA }, 0xaa, INSTR_RRF_UUFR },
{ { 0, LONG_INSN_CLGEBR }, 0xac, INSTR_RRF_UURF },
{ { 0, LONG_INSN_CLGDBR }, 0xad, INSTR_RRF_UURF },
{ { 0, LONG_INSN_CLGXBR }, 0xae, INSTR_RRF_UUFR },
{ "ldgr", 0xc1, INSTR_RRE_FR }, { "ldgr", 0xc1, INSTR_RRE_FR },
{ "cegr", 0xc4, INSTR_RRE_FR },
{ "cdgr", 0xc5, INSTR_RRE_FR },
{ "cxgr", 0xc6, INSTR_RRE_FR },
{ "cger", 0xc8, INSTR_RRF_U0RF },
{ "cgdr", 0xc9, INSTR_RRF_U0RF },
{ "cgxr", 0xca, INSTR_RRF_U0RF },
{ "lgdr", 0xcd, INSTR_RRE_RF }, { "lgdr", 0xcd, INSTR_RRE_RF },
{ "adtr", 0xd2, INSTR_RRR_F0FF }, { "mdtra", 0xd0, INSTR_RRF_FUFF2 },
{ "axtr", 0xda, INSTR_RRR_F0FF }, { "ddtra", 0xd1, INSTR_RRF_FUFF2 },
{ "cdtr", 0xe4, INSTR_RRE_FF }, { "adtra", 0xd2, INSTR_RRF_FUFF2 },
{ "cxtr", 0xec, INSTR_RRE_FF }, { "sdtra", 0xd3, INSTR_RRF_FUFF2 },
{ "ldetr", 0xd4, INSTR_RRF_0UFF },
{ "ledtr", 0xd5, INSTR_RRF_UUFF },
{ "ltdtr", 0xd6, INSTR_RRE_FF },
{ "fidtr", 0xd7, INSTR_RRF_UUFF },
{ "mxtra", 0xd8, INSTR_RRF_FUFF2 },
{ "dxtra", 0xd9, INSTR_RRF_FUFF2 },
{ "axtra", 0xda, INSTR_RRF_FUFF2 },
{ "sxtra", 0xdb, INSTR_RRF_FUFF2 },
{ "lxdtr", 0xdc, INSTR_RRF_0UFF },
{ "ldxtr", 0xdd, INSTR_RRF_UUFF },
{ "ltxtr", 0xde, INSTR_RRE_FF },
{ "fixtr", 0xdf, INSTR_RRF_UUFF },
{ "kdtr", 0xe0, INSTR_RRE_FF }, { "kdtr", 0xe0, INSTR_RRE_FF },
{ "kxtr", 0xe8, INSTR_RRE_FF }, { { 0, LONG_INSN_CGDTRA }, 0xe1, INSTR_RRF_UURF },
{ "cedtr", 0xf4, INSTR_RRE_FF },
{ "cextr", 0xfc, INSTR_RRE_FF },
{ "cdgtr", 0xf1, INSTR_RRE_FR },
{ "cxgtr", 0xf9, INSTR_RRE_FR },
{ "cdstr", 0xf3, INSTR_RRE_FR },
{ "cxstr", 0xfb, INSTR_RRE_FR },
{ "cdutr", 0xf2, INSTR_RRE_FR },
{ "cxutr", 0xfa, INSTR_RRE_FR },
{ "cgdtr", 0xe1, INSTR_RRF_U0RF },
{ "cgxtr", 0xe9, INSTR_RRF_U0RF },
{ "csdtr", 0xe3, INSTR_RRE_RF },
{ "csxtr", 0xeb, INSTR_RRE_RF },
{ "cudtr", 0xe2, INSTR_RRE_RF }, { "cudtr", 0xe2, INSTR_RRE_RF },
{ "cuxtr", 0xea, INSTR_RRE_RF }, { "csdtr", 0xe3, INSTR_RRE_RF },
{ "ddtr", 0xd1, INSTR_RRR_F0FF }, { "cdtr", 0xe4, INSTR_RRE_FF },
{ "dxtr", 0xd9, INSTR_RRR_F0FF },
{ "eedtr", 0xe5, INSTR_RRE_RF }, { "eedtr", 0xe5, INSTR_RRE_RF },
{ "eextr", 0xed, INSTR_RRE_RF },
{ "esdtr", 0xe7, INSTR_RRE_RF }, { "esdtr", 0xe7, INSTR_RRE_RF },
{ "kxtr", 0xe8, INSTR_RRE_FF },
{ { 0, LONG_INSN_CGXTRA }, 0xe9, INSTR_RRF_UUFR },
{ "cuxtr", 0xea, INSTR_RRE_RF },
{ "csxtr", 0xeb, INSTR_RRE_RF },
{ "cxtr", 0xec, INSTR_RRE_FF },
{ "eextr", 0xed, INSTR_RRE_RF },
{ "esxtr", 0xef, INSTR_RRE_RF }, { "esxtr", 0xef, INSTR_RRE_RF },
{ "iedtr", 0xf6, INSTR_RRF_F0FR }, { { 0, LONG_INSN_CDGTRA }, 0xf1, INSTR_RRF_UUFR },
{ "iextr", 0xfe, INSTR_RRF_F0FR }, { "cdutr", 0xf2, INSTR_RRE_FR },
{ "ltdtr", 0xd6, INSTR_RRE_FF }, { "cdstr", 0xf3, INSTR_RRE_FR },
{ "ltxtr", 0xde, INSTR_RRE_FF }, { "cedtr", 0xf4, INSTR_RRE_FF },
{ "fidtr", 0xd7, INSTR_RRF_UUFF },
{ "fixtr", 0xdf, INSTR_RRF_UUFF },
{ "ldetr", 0xd4, INSTR_RRF_0UFF },
{ "lxdtr", 0xdc, INSTR_RRF_0UFF },
{ "ledtr", 0xd5, INSTR_RRF_UUFF },
{ "ldxtr", 0xdd, INSTR_RRF_UUFF },
{ "mdtr", 0xd0, INSTR_RRR_F0FF },
{ "mxtr", 0xd8, INSTR_RRR_F0FF },
{ "qadtr", 0xf5, INSTR_RRF_FUFF }, { "qadtr", 0xf5, INSTR_RRF_FUFF },
{ "qaxtr", 0xfd, INSTR_RRF_FUFF }, { "iedtr", 0xf6, INSTR_RRF_F0FR },
{ "rrdtr", 0xf7, INSTR_RRF_FFRU }, { "rrdtr", 0xf7, INSTR_RRF_FFRU },
{ { 0, LONG_INSN_CXGTRA }, 0xf9, INSTR_RRF_UURF },
{ "cxutr", 0xfa, INSTR_RRE_FR },
{ "cxstr", 0xfb, INSTR_RRE_FR },
{ "cextr", 0xfc, INSTR_RRE_FF },
{ "qaxtr", 0xfd, INSTR_RRF_FUFF },
{ "iextr", 0xfe, INSTR_RRF_F0FR },
{ "rrxtr", 0xff, INSTR_RRF_FFRU }, { "rrxtr", 0xff, INSTR_RRF_FFRU },
{ "sfasr", 0x85, INSTR_RRE_R0 },
{ "sdtr", 0xd3, INSTR_RRR_F0FF },
{ "sxtr", 0xdb, INSTR_RRR_F0FF },
#endif #endif
{ "lpebr", 0x00, INSTR_RRE_FF }, { "lpebr", 0x00, INSTR_RRE_FF },
{ "lnebr", 0x01, INSTR_RRE_FF }, { "lnebr", 0x01, INSTR_RRE_FF },
...@@ -827,10 +979,10 @@ static struct insn opcode_b3[] = { ...@@ -827,10 +979,10 @@ static struct insn opcode_b3[] = {
{ "lnxbr", 0x41, INSTR_RRE_FF }, { "lnxbr", 0x41, INSTR_RRE_FF },
{ "ltxbr", 0x42, INSTR_RRE_FF }, { "ltxbr", 0x42, INSTR_RRE_FF },
{ "lcxbr", 0x43, INSTR_RRE_FF }, { "lcxbr", 0x43, INSTR_RRE_FF },
{ "ledbr", 0x44, INSTR_RRE_FF }, { { 0, LONG_INSN_LEDBRA }, 0x44, INSTR_RRF_UUFF },
{ "ldxbr", 0x45, INSTR_RRE_FF }, { { 0, LONG_INSN_LDXBRA }, 0x45, INSTR_RRF_UUFF },
{ "lexbr", 0x46, INSTR_RRE_FF }, { { 0, LONG_INSN_LEXBRA }, 0x46, INSTR_RRF_UUFF },
{ "fixbr", 0x47, INSTR_RRF_U0FF }, { { 0, LONG_INSN_FIXBRA }, 0x47, INSTR_RRF_UUFF },
{ "kxbr", 0x48, INSTR_RRE_FF }, { "kxbr", 0x48, INSTR_RRE_FF },
{ "cxbr", 0x49, INSTR_RRE_FF }, { "cxbr", 0x49, INSTR_RRE_FF },
{ "axbr", 0x4a, INSTR_RRE_FF }, { "axbr", 0x4a, INSTR_RRE_FF },
...@@ -840,24 +992,24 @@ static struct insn opcode_b3[] = { ...@@ -840,24 +992,24 @@ static struct insn opcode_b3[] = {
{ "tbedr", 0x50, INSTR_RRF_U0FF }, { "tbedr", 0x50, INSTR_RRF_U0FF },
{ "tbdr", 0x51, INSTR_RRF_U0FF }, { "tbdr", 0x51, INSTR_RRF_U0FF },
{ "diebr", 0x53, INSTR_RRF_FUFF }, { "diebr", 0x53, INSTR_RRF_FUFF },
{ "fiebr", 0x57, INSTR_RRF_U0FF }, { { 0, LONG_INSN_FIEBRA }, 0x57, INSTR_RRF_UUFF },
{ "thder", 0x58, INSTR_RRE_RR }, { "thder", 0x58, INSTR_RRE_FF },
{ "thdr", 0x59, INSTR_RRE_RR }, { "thdr", 0x59, INSTR_RRE_FF },
{ "didbr", 0x5b, INSTR_RRF_FUFF }, { "didbr", 0x5b, INSTR_RRF_FUFF },
{ "fidbr", 0x5f, INSTR_RRF_U0FF }, { { 0, LONG_INSN_FIDBRA }, 0x5f, INSTR_RRF_UUFF },
{ "lpxr", 0x60, INSTR_RRE_FF }, { "lpxr", 0x60, INSTR_RRE_FF },
{ "lnxr", 0x61, INSTR_RRE_FF }, { "lnxr", 0x61, INSTR_RRE_FF },
{ "ltxr", 0x62, INSTR_RRE_FF }, { "ltxr", 0x62, INSTR_RRE_FF },
{ "lcxr", 0x63, INSTR_RRE_FF }, { "lcxr", 0x63, INSTR_RRE_FF },
{ "lxr", 0x65, INSTR_RRE_RR }, { "lxr", 0x65, INSTR_RRE_FF },
{ "lexr", 0x66, INSTR_RRE_FF }, { "lexr", 0x66, INSTR_RRE_FF },
{ "fixr", 0x67, INSTR_RRF_U0FF }, { "fixr", 0x67, INSTR_RRE_FF },
{ "cxr", 0x69, INSTR_RRE_FF }, { "cxr", 0x69, INSTR_RRE_FF },
{ "lzer", 0x74, INSTR_RRE_R0 }, { "lzer", 0x74, INSTR_RRE_F0 },
{ "lzdr", 0x75, INSTR_RRE_R0 }, { "lzdr", 0x75, INSTR_RRE_F0 },
{ "lzxr", 0x76, INSTR_RRE_R0 }, { "lzxr", 0x76, INSTR_RRE_F0 },
{ "fier", 0x77, INSTR_RRF_U0FF }, { "fier", 0x77, INSTR_RRE_FF },
{ "fidr", 0x7f, INSTR_RRF_U0FF }, { "fidr", 0x7f, INSTR_RRE_FF },
{ "sfpc", 0x84, INSTR_RRE_RR_OPT }, { "sfpc", 0x84, INSTR_RRE_RR_OPT },
{ "efpc", 0x8c, INSTR_RRE_RR_OPT }, { "efpc", 0x8c, INSTR_RRE_RR_OPT },
{ "cefbr", 0x94, INSTR_RRE_RF }, { "cefbr", 0x94, INSTR_RRE_RF },
...@@ -866,9 +1018,12 @@ static struct insn opcode_b3[] = { ...@@ -866,9 +1018,12 @@ static struct insn opcode_b3[] = {
{ "cfebr", 0x98, INSTR_RRF_U0RF }, { "cfebr", 0x98, INSTR_RRF_U0RF },
{ "cfdbr", 0x99, INSTR_RRF_U0RF }, { "cfdbr", 0x99, INSTR_RRF_U0RF },
{ "cfxbr", 0x9a, INSTR_RRF_U0RF }, { "cfxbr", 0x9a, INSTR_RRF_U0RF },
{ "cefr", 0xb4, INSTR_RRE_RF }, { "cefr", 0xb4, INSTR_RRE_FR },
{ "cdfr", 0xb5, INSTR_RRE_RF }, { "cdfr", 0xb5, INSTR_RRE_FR },
{ "cxfr", 0xb6, INSTR_RRE_RF }, { "cxfr", 0xb6, INSTR_RRE_FR },
{ "cfer", 0xb8, INSTR_RRF_U0RF },
{ "cfdr", 0xb9, INSTR_RRF_U0RF },
{ "cfxr", 0xba, INSTR_RRF_U0RF },
{ "", 0, INSTR_INVALID } { "", 0, INSTR_INVALID }
}; };
...@@ -910,7 +1065,23 @@ static struct insn opcode_b9[] = { ...@@ -910,7 +1065,23 @@ static struct insn opcode_b9[] = {
{ "lhr", 0x27, INSTR_RRE_RR }, { "lhr", 0x27, INSTR_RRE_RR },
{ "cgfr", 0x30, INSTR_RRE_RR }, { "cgfr", 0x30, INSTR_RRE_RR },
{ "clgfr", 0x31, INSTR_RRE_RR }, { "clgfr", 0x31, INSTR_RRE_RR },
{ "cfdtr", 0x41, INSTR_RRF_UURF },
{ { 0, LONG_INSN_CLGDTR }, 0x42, INSTR_RRF_UURF },
{ { 0, LONG_INSN_CLFDTR }, 0x43, INSTR_RRF_UURF },
{ "bctgr", 0x46, INSTR_RRE_RR }, { "bctgr", 0x46, INSTR_RRE_RR },
{ "cfxtr", 0x49, INSTR_RRF_UURF },
{ { 0, LONG_INSN_CLGXTR }, 0x4a, INSTR_RRF_UUFR },
{ { 0, LONG_INSN_CLFXTR }, 0x4b, INSTR_RRF_UUFR },
{ "cdftr", 0x51, INSTR_RRF_UUFR },
{ { 0, LONG_INSN_CDLGTR }, 0x52, INSTR_RRF_UUFR },
{ { 0, LONG_INSN_CDLFTR }, 0x53, INSTR_RRF_UUFR },
{ "cxftr", 0x59, INSTR_RRF_UURF },
{ { 0, LONG_INSN_CXLGTR }, 0x5a, INSTR_RRF_UURF },
{ { 0, LONG_INSN_CXLFTR }, 0x5b, INSTR_RRF_UUFR },
{ "cgrt", 0x60, INSTR_RRF_U0RR },
{ "clgrt", 0x61, INSTR_RRF_U0RR },
{ "crt", 0x72, INSTR_RRF_U0RR },
{ "clrt", 0x73, INSTR_RRF_U0RR },
{ "ngr", 0x80, INSTR_RRE_RR }, { "ngr", 0x80, INSTR_RRE_RR },
{ "ogr", 0x81, INSTR_RRE_RR }, { "ogr", 0x81, INSTR_RRE_RR },
{ "xgr", 0x82, INSTR_RRE_RR }, { "xgr", 0x82, INSTR_RRE_RR },
...@@ -923,32 +1094,31 @@ static struct insn opcode_b9[] = { ...@@ -923,32 +1094,31 @@ static struct insn opcode_b9[] = {
{ "slbgr", 0x89, INSTR_RRE_RR }, { "slbgr", 0x89, INSTR_RRE_RR },
{ "cspg", 0x8a, INSTR_RRE_RR }, { "cspg", 0x8a, INSTR_RRE_RR },
{ "idte", 0x8e, INSTR_RRF_R0RR }, { "idte", 0x8e, INSTR_RRF_R0RR },
{ "crdte", 0x8f, INSTR_RRF_RMRR },
{ "llcr", 0x94, INSTR_RRE_RR }, { "llcr", 0x94, INSTR_RRE_RR },
{ "llhr", 0x95, INSTR_RRE_RR }, { "llhr", 0x95, INSTR_RRE_RR },
{ "esea", 0x9d, INSTR_RRE_R0 }, { "esea", 0x9d, INSTR_RRE_R0 },
{ "ptf", 0xa2, INSTR_RRE_R0 },
{ "lptea", 0xaa, INSTR_RRF_RURR }, { "lptea", 0xaa, INSTR_RRF_RURR },
{ "rrbm", 0xae, INSTR_RRE_RR },
{ "pfmf", 0xaf, INSTR_RRE_RR },
{ "cu14", 0xb0, INSTR_RRF_M0RR }, { "cu14", 0xb0, INSTR_RRF_M0RR },
{ "cu24", 0xb1, INSTR_RRF_M0RR }, { "cu24", 0xb1, INSTR_RRF_M0RR },
{ "cu41", 0xb2, INSTR_RRF_M0RR }, { "cu41", 0xb2, INSTR_RRE_RR },
{ "cu42", 0xb3, INSTR_RRF_M0RR }, { "cu42", 0xb3, INSTR_RRE_RR },
{ "crt", 0x72, INSTR_RRF_U0RR },
{ "cgrt", 0x60, INSTR_RRF_U0RR },
{ "clrt", 0x73, INSTR_RRF_U0RR },
{ "clgrt", 0x61, INSTR_RRF_U0RR },
{ "ptf", 0xa2, INSTR_RRE_R0 },
{ "pfmf", 0xaf, INSTR_RRE_RR },
{ "trte", 0xbf, INSTR_RRF_M0RR },
{ "trtre", 0xbd, INSTR_RRF_M0RR }, { "trtre", 0xbd, INSTR_RRF_M0RR },
{ "srstu", 0xbe, INSTR_RRE_RR },
{ "trte", 0xbf, INSTR_RRF_M0RR },
{ "ahhhr", 0xc8, INSTR_RRF_R0RR2 }, { "ahhhr", 0xc8, INSTR_RRF_R0RR2 },
{ "shhhr", 0xc9, INSTR_RRF_R0RR2 }, { "shhhr", 0xc9, INSTR_RRF_R0RR2 },
{ "alhhh", 0xca, INSTR_RRF_R0RR2 }, { { 0, LONG_INSN_ALHHHR }, 0xca, INSTR_RRF_R0RR2 },
{ "alhhl", 0xca, INSTR_RRF_R0RR2 }, { { 0, LONG_INSN_SLHHHR }, 0xcb, INSTR_RRF_R0RR2 },
{ "slhhh", 0xcb, INSTR_RRF_R0RR2 }, { "chhr", 0xcd, INSTR_RRE_RR },
{ "chhr ", 0xcd, INSTR_RRE_RR },
{ "clhhr", 0xcf, INSTR_RRE_RR }, { "clhhr", 0xcf, INSTR_RRE_RR },
{ "ahhlr", 0xd8, INSTR_RRF_R0RR2 }, { "ahhlr", 0xd8, INSTR_RRF_R0RR2 },
{ "shhlr", 0xd9, INSTR_RRF_R0RR2 }, { "shhlr", 0xd9, INSTR_RRF_R0RR2 },
{ "slhhl", 0xdb, INSTR_RRF_R0RR2 }, { { 0, LONG_INSN_ALHHLR }, 0xda, INSTR_RRF_R0RR2 },
{ { 0, LONG_INSN_SLHHLR }, 0xdb, INSTR_RRF_R0RR2 },
{ "chlr", 0xdd, INSTR_RRE_RR }, { "chlr", 0xdd, INSTR_RRE_RR },
{ "clhlr", 0xdf, INSTR_RRE_RR }, { "clhlr", 0xdf, INSTR_RRE_RR },
{ { 0, LONG_INSN_POPCNT }, 0xe1, INSTR_RRE_RR }, { { 0, LONG_INSN_POPCNT }, 0xe1, INSTR_RRE_RR },
...@@ -976,13 +1146,9 @@ static struct insn opcode_b9[] = { ...@@ -976,13 +1146,9 @@ static struct insn opcode_b9[] = {
{ "kimd", 0x3e, INSTR_RRE_RR }, { "kimd", 0x3e, INSTR_RRE_RR },
{ "klmd", 0x3f, INSTR_RRE_RR }, { "klmd", 0x3f, INSTR_RRE_RR },
{ "epsw", 0x8d, INSTR_RRE_RR }, { "epsw", 0x8d, INSTR_RRE_RR },
{ "trtt", 0x90, INSTR_RRE_RR },
{ "trtt", 0x90, INSTR_RRF_M0RR }, { "trtt", 0x90, INSTR_RRF_M0RR },
{ "trto", 0x91, INSTR_RRE_RR },
{ "trto", 0x91, INSTR_RRF_M0RR }, { "trto", 0x91, INSTR_RRF_M0RR },
{ "trot", 0x92, INSTR_RRE_RR },
{ "trot", 0x92, INSTR_RRF_M0RR }, { "trot", 0x92, INSTR_RRF_M0RR },
{ "troo", 0x93, INSTR_RRE_RR },
{ "troo", 0x93, INSTR_RRF_M0RR }, { "troo", 0x93, INSTR_RRF_M0RR },
{ "mlr", 0x96, INSTR_RRE_RR }, { "mlr", 0x96, INSTR_RRE_RR },
{ "dlr", 0x97, INSTR_RRE_RR }, { "dlr", 0x97, INSTR_RRE_RR },
...@@ -1013,6 +1179,8 @@ static struct insn opcode_c0[] = { ...@@ -1013,6 +1179,8 @@ static struct insn opcode_c0[] = {
static struct insn opcode_c2[] = { static struct insn opcode_c2[] = {
#ifdef CONFIG_64BIT #ifdef CONFIG_64BIT
{ "msgfi", 0x00, INSTR_RIL_RI },
{ "msfi", 0x01, INSTR_RIL_RI },
{ "slgfi", 0x04, INSTR_RIL_RU }, { "slgfi", 0x04, INSTR_RIL_RU },
{ "slfi", 0x05, INSTR_RIL_RU }, { "slfi", 0x05, INSTR_RIL_RU },
{ "agfi", 0x08, INSTR_RIL_RI }, { "agfi", 0x08, INSTR_RIL_RI },
...@@ -1023,43 +1191,41 @@ static struct insn opcode_c2[] = { ...@@ -1023,43 +1191,41 @@ static struct insn opcode_c2[] = {
{ "cfi", 0x0d, INSTR_RIL_RI }, { "cfi", 0x0d, INSTR_RIL_RI },
{ "clgfi", 0x0e, INSTR_RIL_RU }, { "clgfi", 0x0e, INSTR_RIL_RU },
{ "clfi", 0x0f, INSTR_RIL_RU }, { "clfi", 0x0f, INSTR_RIL_RU },
{ "msfi", 0x01, INSTR_RIL_RI },
{ "msgfi", 0x00, INSTR_RIL_RI },
#endif #endif
{ "", 0, INSTR_INVALID } { "", 0, INSTR_INVALID }
}; };
static struct insn opcode_c4[] = { static struct insn opcode_c4[] = {
#ifdef CONFIG_64BIT #ifdef CONFIG_64BIT
{ "lrl", 0x0d, INSTR_RIL_RP }, { "llhrl", 0x02, INSTR_RIL_RP },
{ "lghrl", 0x04, INSTR_RIL_RP },
{ "lhrl", 0x05, INSTR_RIL_RP },
{ { 0, LONG_INSN_LLGHRL }, 0x06, INSTR_RIL_RP },
{ "sthrl", 0x07, INSTR_RIL_RP },
{ "lgrl", 0x08, INSTR_RIL_RP }, { "lgrl", 0x08, INSTR_RIL_RP },
{ "stgrl", 0x0b, INSTR_RIL_RP },
{ "lgfrl", 0x0c, INSTR_RIL_RP }, { "lgfrl", 0x0c, INSTR_RIL_RP },
{ "lhrl", 0x05, INSTR_RIL_RP }, { "lrl", 0x0d, INSTR_RIL_RP },
{ "lghrl", 0x04, INSTR_RIL_RP },
{ { 0, LONG_INSN_LLGFRL }, 0x0e, INSTR_RIL_RP }, { { 0, LONG_INSN_LLGFRL }, 0x0e, INSTR_RIL_RP },
{ "llhrl", 0x02, INSTR_RIL_RP },
{ { 0, LONG_INSN_LLGHRL }, 0x06, INSTR_RIL_RP },
{ "strl", 0x0f, INSTR_RIL_RP }, { "strl", 0x0f, INSTR_RIL_RP },
{ "stgrl", 0x0b, INSTR_RIL_RP },
{ "sthrl", 0x07, INSTR_RIL_RP },
#endif #endif
{ "", 0, INSTR_INVALID } { "", 0, INSTR_INVALID }
}; };
static struct insn opcode_c6[] = { static struct insn opcode_c6[] = {
#ifdef CONFIG_64BIT #ifdef CONFIG_64BIT
{ "crl", 0x0d, INSTR_RIL_RP }, { "exrl", 0x00, INSTR_RIL_RP },
{ "cgrl", 0x08, INSTR_RIL_RP }, { "pfdrl", 0x02, INSTR_RIL_UP },
{ "cgfrl", 0x0c, INSTR_RIL_RP },
{ "chrl", 0x05, INSTR_RIL_RP },
{ "cghrl", 0x04, INSTR_RIL_RP }, { "cghrl", 0x04, INSTR_RIL_RP },
{ "clrl", 0x0f, INSTR_RIL_RP }, { "chrl", 0x05, INSTR_RIL_RP },
{ { 0, LONG_INSN_CLGHRL }, 0x06, INSTR_RIL_RP },
{ "clhrl", 0x07, INSTR_RIL_RP },
{ "cgrl", 0x08, INSTR_RIL_RP },
{ "clgrl", 0x0a, INSTR_RIL_RP }, { "clgrl", 0x0a, INSTR_RIL_RP },
{ "cgfrl", 0x0c, INSTR_RIL_RP },
{ "crl", 0x0d, INSTR_RIL_RP },
{ { 0, LONG_INSN_CLGFRL }, 0x0e, INSTR_RIL_RP }, { { 0, LONG_INSN_CLGFRL }, 0x0e, INSTR_RIL_RP },
{ "clhrl", 0x07, INSTR_RIL_RP }, { "clrl", 0x0f, INSTR_RIL_RP },
{ { 0, LONG_INSN_CLGHRL }, 0x06, INSTR_RIL_RP },
{ "pfdrl", 0x02, INSTR_RIL_UP },
{ "exrl", 0x00, INSTR_RIL_RP },
#endif #endif
{ "", 0, INSTR_INVALID } { "", 0, INSTR_INVALID }
}; };
...@@ -1070,7 +1236,7 @@ static struct insn opcode_c8[] = { ...@@ -1070,7 +1236,7 @@ static struct insn opcode_c8[] = {
{ "ectg", 0x01, INSTR_SSF_RRDRD }, { "ectg", 0x01, INSTR_SSF_RRDRD },
{ "csst", 0x02, INSTR_SSF_RRDRD }, { "csst", 0x02, INSTR_SSF_RRDRD },
{ "lpd", 0x04, INSTR_SSF_RRDRD2 }, { "lpd", 0x04, INSTR_SSF_RRDRD2 },
{ "lpdg ", 0x05, INSTR_SSF_RRDRD2 }, { "lpdg", 0x05, INSTR_SSF_RRDRD2 },
#endif #endif
{ "", 0, INSTR_INVALID } { "", 0, INSTR_INVALID }
}; };
...@@ -1080,9 +1246,9 @@ static struct insn opcode_cc[] = { ...@@ -1080,9 +1246,9 @@ static struct insn opcode_cc[] = {
{ "brcth", 0x06, INSTR_RIL_RP }, { "brcth", 0x06, INSTR_RIL_RP },
{ "aih", 0x08, INSTR_RIL_RI }, { "aih", 0x08, INSTR_RIL_RI },
{ "alsih", 0x0a, INSTR_RIL_RI }, { "alsih", 0x0a, INSTR_RIL_RI },
{ "alsih", 0x0b, INSTR_RIL_RI }, { { 0, LONG_INSN_ALSIHN }, 0x0b, INSTR_RIL_RI },
{ "cih", 0x0d, INSTR_RIL_RI }, { "cih", 0x0d, INSTR_RIL_RI },
{ "clih ", 0x0f, INSTR_RIL_RI }, { "clih", 0x0f, INSTR_RIL_RI },
#endif #endif
{ "", 0, INSTR_INVALID } { "", 0, INSTR_INVALID }
}; };
...@@ -1116,11 +1282,15 @@ static struct insn opcode_e3[] = { ...@@ -1116,11 +1282,15 @@ static struct insn opcode_e3[] = {
{ "cg", 0x20, INSTR_RXY_RRRD }, { "cg", 0x20, INSTR_RXY_RRRD },
{ "clg", 0x21, INSTR_RXY_RRRD }, { "clg", 0x21, INSTR_RXY_RRRD },
{ "stg", 0x24, INSTR_RXY_RRRD }, { "stg", 0x24, INSTR_RXY_RRRD },
{ "ntstg", 0x25, INSTR_RXY_RRRD },
{ "cvdy", 0x26, INSTR_RXY_RRRD }, { "cvdy", 0x26, INSTR_RXY_RRRD },
{ "cvdg", 0x2e, INSTR_RXY_RRRD }, { "cvdg", 0x2e, INSTR_RXY_RRRD },
{ "strvg", 0x2f, INSTR_RXY_RRRD }, { "strvg", 0x2f, INSTR_RXY_RRRD },
{ "cgf", 0x30, INSTR_RXY_RRRD }, { "cgf", 0x30, INSTR_RXY_RRRD },
{ "clgf", 0x31, INSTR_RXY_RRRD }, { "clgf", 0x31, INSTR_RXY_RRRD },
{ "ltgf", 0x32, INSTR_RXY_RRRD },
{ "cgh", 0x34, INSTR_RXY_RRRD },
{ "pfd", 0x36, INSTR_RXY_URRD },
{ "strvh", 0x3f, INSTR_RXY_RRRD }, { "strvh", 0x3f, INSTR_RXY_RRRD },
{ "bctg", 0x46, INSTR_RXY_RRRD }, { "bctg", 0x46, INSTR_RXY_RRRD },
{ "sty", 0x50, INSTR_RXY_RRRD }, { "sty", 0x50, INSTR_RXY_RRRD },
...@@ -1133,21 +1303,25 @@ static struct insn opcode_e3[] = { ...@@ -1133,21 +1303,25 @@ static struct insn opcode_e3[] = {
{ "cy", 0x59, INSTR_RXY_RRRD }, { "cy", 0x59, INSTR_RXY_RRRD },
{ "ay", 0x5a, INSTR_RXY_RRRD }, { "ay", 0x5a, INSTR_RXY_RRRD },
{ "sy", 0x5b, INSTR_RXY_RRRD }, { "sy", 0x5b, INSTR_RXY_RRRD },
{ "mfy", 0x5c, INSTR_RXY_RRRD },
{ "aly", 0x5e, INSTR_RXY_RRRD }, { "aly", 0x5e, INSTR_RXY_RRRD },
{ "sly", 0x5f, INSTR_RXY_RRRD }, { "sly", 0x5f, INSTR_RXY_RRRD },
{ "sthy", 0x70, INSTR_RXY_RRRD }, { "sthy", 0x70, INSTR_RXY_RRRD },
{ "lay", 0x71, INSTR_RXY_RRRD }, { "lay", 0x71, INSTR_RXY_RRRD },
{ "stcy", 0x72, INSTR_RXY_RRRD }, { "stcy", 0x72, INSTR_RXY_RRRD },
{ "icy", 0x73, INSTR_RXY_RRRD }, { "icy", 0x73, INSTR_RXY_RRRD },
{ "laey", 0x75, INSTR_RXY_RRRD },
{ "lb", 0x76, INSTR_RXY_RRRD }, { "lb", 0x76, INSTR_RXY_RRRD },
{ "lgb", 0x77, INSTR_RXY_RRRD }, { "lgb", 0x77, INSTR_RXY_RRRD },
{ "lhy", 0x78, INSTR_RXY_RRRD }, { "lhy", 0x78, INSTR_RXY_RRRD },
{ "chy", 0x79, INSTR_RXY_RRRD }, { "chy", 0x79, INSTR_RXY_RRRD },
{ "ahy", 0x7a, INSTR_RXY_RRRD }, { "ahy", 0x7a, INSTR_RXY_RRRD },
{ "shy", 0x7b, INSTR_RXY_RRRD }, { "shy", 0x7b, INSTR_RXY_RRRD },
{ "mhy", 0x7c, INSTR_RXY_RRRD },
{ "ng", 0x80, INSTR_RXY_RRRD }, { "ng", 0x80, INSTR_RXY_RRRD },
{ "og", 0x81, INSTR_RXY_RRRD }, { "og", 0x81, INSTR_RXY_RRRD },
{ "xg", 0x82, INSTR_RXY_RRRD }, { "xg", 0x82, INSTR_RXY_RRRD },
{ "lgat", 0x85, INSTR_RXY_RRRD },
{ "mlg", 0x86, INSTR_RXY_RRRD }, { "mlg", 0x86, INSTR_RXY_RRRD },
{ "dlg", 0x87, INSTR_RXY_RRRD }, { "dlg", 0x87, INSTR_RXY_RRRD },
{ "alcg", 0x88, INSTR_RXY_RRRD }, { "alcg", 0x88, INSTR_RXY_RRRD },
...@@ -1158,23 +1332,20 @@ static struct insn opcode_e3[] = { ...@@ -1158,23 +1332,20 @@ static struct insn opcode_e3[] = {
{ "llgh", 0x91, INSTR_RXY_RRRD }, { "llgh", 0x91, INSTR_RXY_RRRD },
{ "llc", 0x94, INSTR_RXY_RRRD }, { "llc", 0x94, INSTR_RXY_RRRD },
{ "llh", 0x95, INSTR_RXY_RRRD }, { "llh", 0x95, INSTR_RXY_RRRD },
{ "cgh", 0x34, INSTR_RXY_RRRD }, { { 0, LONG_INSN_LLGTAT }, 0x9c, INSTR_RXY_RRRD },
{ "laey", 0x75, INSTR_RXY_RRRD }, { { 0, LONG_INSN_LLGFAT }, 0x9d, INSTR_RXY_RRRD },
{ "ltgf", 0x32, INSTR_RXY_RRRD }, { "lat", 0x9f, INSTR_RXY_RRRD },
{ "mfy", 0x5c, INSTR_RXY_RRRD },
{ "mhy", 0x7c, INSTR_RXY_RRRD },
{ "pfd", 0x36, INSTR_RXY_URRD },
{ "lbh", 0xc0, INSTR_RXY_RRRD }, { "lbh", 0xc0, INSTR_RXY_RRRD },
{ "llch", 0xc2, INSTR_RXY_RRRD }, { "llch", 0xc2, INSTR_RXY_RRRD },
{ "stch", 0xc3, INSTR_RXY_RRRD }, { "stch", 0xc3, INSTR_RXY_RRRD },
{ "lhh", 0xc4, INSTR_RXY_RRRD }, { "lhh", 0xc4, INSTR_RXY_RRRD },
{ "llhh", 0xc6, INSTR_RXY_RRRD }, { "llhh", 0xc6, INSTR_RXY_RRRD },
{ "sthh", 0xc7, INSTR_RXY_RRRD }, { "sthh", 0xc7, INSTR_RXY_RRRD },
{ "lfhat", 0xc8, INSTR_RXY_RRRD },
{ "lfh", 0xca, INSTR_RXY_RRRD }, { "lfh", 0xca, INSTR_RXY_RRRD },
{ "stfh", 0xcb, INSTR_RXY_RRRD }, { "stfh", 0xcb, INSTR_RXY_RRRD },
{ "chf", 0xcd, INSTR_RXY_RRRD }, { "chf", 0xcd, INSTR_RXY_RRRD },
{ "clhf", 0xcf, INSTR_RXY_RRRD }, { "clhf", 0xcf, INSTR_RXY_RRRD },
{ "ntstg", 0x25, INSTR_RXY_RRRD },
#endif #endif
{ "lrv", 0x1e, INSTR_RXY_RRRD }, { "lrv", 0x1e, INSTR_RXY_RRRD },
{ "lrvh", 0x1f, INSTR_RXY_RRRD }, { "lrvh", 0x1f, INSTR_RXY_RRRD },
...@@ -1189,15 +1360,15 @@ static struct insn opcode_e3[] = { ...@@ -1189,15 +1360,15 @@ static struct insn opcode_e3[] = {
static struct insn opcode_e5[] = { static struct insn opcode_e5[] = {
#ifdef CONFIG_64BIT #ifdef CONFIG_64BIT
{ "strag", 0x02, INSTR_SSE_RDRD }, { "strag", 0x02, INSTR_SSE_RDRD },
{ "mvhhi", 0x44, INSTR_SIL_RDI },
{ "mvghi", 0x48, INSTR_SIL_RDI },
{ "mvhi", 0x4c, INSTR_SIL_RDI },
{ "chhsi", 0x54, INSTR_SIL_RDI }, { "chhsi", 0x54, INSTR_SIL_RDI },
{ "chsi", 0x5c, INSTR_SIL_RDI },
{ "cghsi", 0x58, INSTR_SIL_RDI },
{ { 0, LONG_INSN_CLHHSI }, 0x55, INSTR_SIL_RDU }, { { 0, LONG_INSN_CLHHSI }, 0x55, INSTR_SIL_RDU },
{ { 0, LONG_INSN_CLFHSI }, 0x5d, INSTR_SIL_RDU }, { "cghsi", 0x58, INSTR_SIL_RDI },
{ { 0, LONG_INSN_CLGHSI }, 0x59, INSTR_SIL_RDU }, { { 0, LONG_INSN_CLGHSI }, 0x59, INSTR_SIL_RDU },
{ "mvhhi", 0x44, INSTR_SIL_RDI }, { "chsi", 0x5c, INSTR_SIL_RDI },
{ "mvhi", 0x4c, INSTR_SIL_RDI }, { { 0, LONG_INSN_CLFHSI }, 0x5d, INSTR_SIL_RDU },
{ "mvghi", 0x48, INSTR_SIL_RDI },
{ { 0, LONG_INSN_TBEGIN }, 0x60, INSTR_SIL_RDU }, { { 0, LONG_INSN_TBEGIN }, 0x60, INSTR_SIL_RDU },
{ { 0, LONG_INSN_TBEGINC }, 0x61, INSTR_SIL_RDU }, { { 0, LONG_INSN_TBEGINC }, 0x61, INSTR_SIL_RDU },
#endif #endif
...@@ -1220,9 +1391,11 @@ static struct insn opcode_eb[] = { ...@@ -1220,9 +1391,11 @@ static struct insn opcode_eb[] = {
{ "rllg", 0x1c, INSTR_RSY_RRRD }, { "rllg", 0x1c, INSTR_RSY_RRRD },
{ "clmh", 0x20, INSTR_RSY_RURD }, { "clmh", 0x20, INSTR_RSY_RURD },
{ "clmy", 0x21, INSTR_RSY_RURD }, { "clmy", 0x21, INSTR_RSY_RURD },
{ "clt", 0x23, INSTR_RSY_RURD },
{ "stmg", 0x24, INSTR_RSY_RRRD }, { "stmg", 0x24, INSTR_RSY_RRRD },
{ "stctg", 0x25, INSTR_RSY_CCRD }, { "stctg", 0x25, INSTR_RSY_CCRD },
{ "stmh", 0x26, INSTR_RSY_RRRD }, { "stmh", 0x26, INSTR_RSY_RRRD },
{ "clgt", 0x2b, INSTR_RSY_RURD },
{ "stcmh", 0x2c, INSTR_RSY_RURD }, { "stcmh", 0x2c, INSTR_RSY_RURD },
{ "stcmy", 0x2d, INSTR_RSY_RURD }, { "stcmy", 0x2d, INSTR_RSY_RURD },
{ "lctlg", 0x2f, INSTR_RSY_CCRD }, { "lctlg", 0x2f, INSTR_RSY_CCRD },
...@@ -1231,16 +1404,17 @@ static struct insn opcode_eb[] = { ...@@ -1231,16 +1404,17 @@ static struct insn opcode_eb[] = {
{ "cdsg", 0x3e, INSTR_RSY_RRRD }, { "cdsg", 0x3e, INSTR_RSY_RRRD },
{ "bxhg", 0x44, INSTR_RSY_RRRD }, { "bxhg", 0x44, INSTR_RSY_RRRD },
{ "bxleg", 0x45, INSTR_RSY_RRRD }, { "bxleg", 0x45, INSTR_RSY_RRRD },
{ "ecag", 0x4c, INSTR_RSY_RRRD },
{ "tmy", 0x51, INSTR_SIY_URD }, { "tmy", 0x51, INSTR_SIY_URD },
{ "mviy", 0x52, INSTR_SIY_URD }, { "mviy", 0x52, INSTR_SIY_URD },
{ "niy", 0x54, INSTR_SIY_URD }, { "niy", 0x54, INSTR_SIY_URD },
{ "cliy", 0x55, INSTR_SIY_URD }, { "cliy", 0x55, INSTR_SIY_URD },
{ "oiy", 0x56, INSTR_SIY_URD }, { "oiy", 0x56, INSTR_SIY_URD },
{ "xiy", 0x57, INSTR_SIY_URD }, { "xiy", 0x57, INSTR_SIY_URD },
{ "lric", 0x60, INSTR_RSY_RDRM }, { "asi", 0x6a, INSTR_SIY_IRD },
{ "stric", 0x61, INSTR_RSY_RDRM }, { "alsi", 0x6e, INSTR_SIY_IRD },
{ "mric", 0x62, INSTR_RSY_RDRM }, { "agsi", 0x7a, INSTR_SIY_IRD },
{ "icmh", 0x80, INSTR_RSE_RURD }, { "algsi", 0x7e, INSTR_SIY_IRD },
{ "icmh", 0x80, INSTR_RSY_RURD }, { "icmh", 0x80, INSTR_RSY_RURD },
{ "icmy", 0x81, INSTR_RSY_RURD }, { "icmy", 0x81, INSTR_RSY_RURD },
{ "clclu", 0x8f, INSTR_RSY_RRRD }, { "clclu", 0x8f, INSTR_RSY_RRRD },
...@@ -1249,11 +1423,6 @@ static struct insn opcode_eb[] = { ...@@ -1249,11 +1423,6 @@ static struct insn opcode_eb[] = {
{ "lmy", 0x98, INSTR_RSY_RRRD }, { "lmy", 0x98, INSTR_RSY_RRRD },
{ "lamy", 0x9a, INSTR_RSY_AARD }, { "lamy", 0x9a, INSTR_RSY_AARD },
{ "stamy", 0x9b, INSTR_RSY_AARD }, { "stamy", 0x9b, INSTR_RSY_AARD },
{ "asi", 0x6a, INSTR_SIY_IRD },
{ "agsi", 0x7a, INSTR_SIY_IRD },
{ "alsi", 0x6e, INSTR_SIY_IRD },
{ "algsi", 0x7e, INSTR_SIY_IRD },
{ "ecag", 0x4c, INSTR_RSY_RRRD },
{ "srak", 0xdc, INSTR_RSY_RRRD }, { "srak", 0xdc, INSTR_RSY_RRRD },
{ "slak", 0xdd, INSTR_RSY_RRRD }, { "slak", 0xdd, INSTR_RSY_RRRD },
{ "srlk", 0xde, INSTR_RSY_RRRD }, { "srlk", 0xde, INSTR_RSY_RRRD },
...@@ -1272,6 +1441,9 @@ static struct insn opcode_eb[] = { ...@@ -1272,6 +1441,9 @@ static struct insn opcode_eb[] = {
{ "lax", 0xf7, INSTR_RSY_RRRD }, { "lax", 0xf7, INSTR_RSY_RRRD },
{ "laa", 0xf8, INSTR_RSY_RRRD }, { "laa", 0xf8, INSTR_RSY_RRRD },
{ "laal", 0xfa, INSTR_RSY_RRRD }, { "laal", 0xfa, INSTR_RSY_RRRD },
{ "lric", 0x60, INSTR_RSY_RDRM },
{ "stric", 0x61, INSTR_RSY_RDRM },
{ "mric", 0x62, INSTR_RSY_RDRM },
#endif #endif
{ "rll", 0x1d, INSTR_RSY_RRRD }, { "rll", 0x1d, INSTR_RSY_RRRD },
{ "mvclu", 0x8e, INSTR_RSY_RRRD }, { "mvclu", 0x8e, INSTR_RSY_RRRD },
...@@ -1283,36 +1455,37 @@ static struct insn opcode_ec[] = { ...@@ -1283,36 +1455,37 @@ static struct insn opcode_ec[] = {
#ifdef CONFIG_64BIT #ifdef CONFIG_64BIT
{ "brxhg", 0x44, INSTR_RIE_RRP }, { "brxhg", 0x44, INSTR_RIE_RRP },
{ "brxlg", 0x45, INSTR_RIE_RRP }, { "brxlg", 0x45, INSTR_RIE_RRP },
{ "crb", 0xf6, INSTR_RRS_RRRDU }, { { 0, LONG_INSN_RISBLG }, 0x51, INSTR_RIE_RRUUU },
{ "cgrb", 0xe4, INSTR_RRS_RRRDU }, { "rnsbg", 0x54, INSTR_RIE_RRUUU },
{ "crj", 0x76, INSTR_RIE_RRPU }, { "risbg", 0x55, INSTR_RIE_RRUUU },
{ "rosbg", 0x56, INSTR_RIE_RRUUU },
{ "rxsbg", 0x57, INSTR_RIE_RRUUU },
{ { 0, LONG_INSN_RISBGN }, 0x59, INSTR_RIE_RRUUU },
{ { 0, LONG_INSN_RISBHG }, 0x5D, INSTR_RIE_RRUUU },
{ "cgrj", 0x64, INSTR_RIE_RRPU }, { "cgrj", 0x64, INSTR_RIE_RRPU },
{ "cib", 0xfe, INSTR_RIS_RURDI }, { "clgrj", 0x65, INSTR_RIE_RRPU },
{ "cgib", 0xfc, INSTR_RIS_RURDI },
{ "cij", 0x7e, INSTR_RIE_RUPI },
{ "cgij", 0x7c, INSTR_RIE_RUPI },
{ "cit", 0x72, INSTR_RIE_R0IU },
{ "cgit", 0x70, INSTR_RIE_R0IU }, { "cgit", 0x70, INSTR_RIE_R0IU },
{ "clrb", 0xf7, INSTR_RRS_RRRDU }, { "clgit", 0x71, INSTR_RIE_R0UU },
{ "clgrb", 0xe5, INSTR_RRS_RRRDU }, { "cit", 0x72, INSTR_RIE_R0IU },
{ "clfit", 0x73, INSTR_RIE_R0UU },
{ "crj", 0x76, INSTR_RIE_RRPU },
{ "clrj", 0x77, INSTR_RIE_RRPU }, { "clrj", 0x77, INSTR_RIE_RRPU },
{ "clgrj", 0x65, INSTR_RIE_RRPU }, { "cgij", 0x7c, INSTR_RIE_RUPI },
{ "clib", 0xff, INSTR_RIS_RURDU },
{ "clgib", 0xfd, INSTR_RIS_RURDU },
{ "clij", 0x7f, INSTR_RIE_RUPU },
{ "clgij", 0x7d, INSTR_RIE_RUPU }, { "clgij", 0x7d, INSTR_RIE_RUPU },
{ "clfit", 0x73, INSTR_RIE_R0UU }, { "cij", 0x7e, INSTR_RIE_RUPI },
{ "clgit", 0x71, INSTR_RIE_R0UU }, { "clij", 0x7f, INSTR_RIE_RUPU },
{ "rnsbg", 0x54, INSTR_RIE_RRUUU },
{ "rxsbg", 0x57, INSTR_RIE_RRUUU },
{ "rosbg", 0x56, INSTR_RIE_RRUUU },
{ "risbg", 0x55, INSTR_RIE_RRUUU },
{ { 0, LONG_INSN_RISBLG }, 0x51, INSTR_RIE_RRUUU },
{ { 0, LONG_INSN_RISBHG }, 0x5D, INSTR_RIE_RRUUU },
{ "ahik", 0xd8, INSTR_RIE_RRI0 }, { "ahik", 0xd8, INSTR_RIE_RRI0 },
{ "aghik", 0xd9, INSTR_RIE_RRI0 }, { "aghik", 0xd9, INSTR_RIE_RRI0 },
{ { 0, LONG_INSN_ALHSIK }, 0xda, INSTR_RIE_RRI0 }, { { 0, LONG_INSN_ALHSIK }, 0xda, INSTR_RIE_RRI0 },
{ { 0, LONG_INSN_ALGHSIK }, 0xdb, INSTR_RIE_RRI0 }, { { 0, LONG_INSN_ALGHSIK }, 0xdb, INSTR_RIE_RRI0 },
{ "cgrb", 0xe4, INSTR_RRS_RRRDU },
{ "clgrb", 0xe5, INSTR_RRS_RRRDU },
{ "crb", 0xf6, INSTR_RRS_RRRDU },
{ "clrb", 0xf7, INSTR_RRS_RRRDU },
{ "cgib", 0xfc, INSTR_RIS_RURDI },
{ "clgib", 0xfd, INSTR_RIS_RURDU },
{ "cib", 0xfe, INSTR_RIS_RURDI },
{ "clib", 0xff, INSTR_RIS_RURDU },
#endif #endif
{ "", 0, INSTR_INVALID } { "", 0, INSTR_INVALID }
}; };
...@@ -1325,20 +1498,24 @@ static struct insn opcode_ed[] = { ...@@ -1325,20 +1498,24 @@ static struct insn opcode_ed[] = {
{ "my", 0x3b, INSTR_RXF_FRRDF }, { "my", 0x3b, INSTR_RXF_FRRDF },
{ "mayh", 0x3c, INSTR_RXF_FRRDF }, { "mayh", 0x3c, INSTR_RXF_FRRDF },
{ "myh", 0x3d, INSTR_RXF_FRRDF }, { "myh", 0x3d, INSTR_RXF_FRRDF },
{ "ley", 0x64, INSTR_RXY_FRRD },
{ "ldy", 0x65, INSTR_RXY_FRRD },
{ "stey", 0x66, INSTR_RXY_FRRD },
{ "stdy", 0x67, INSTR_RXY_FRRD },
{ "sldt", 0x40, INSTR_RXF_FRRDF }, { "sldt", 0x40, INSTR_RXF_FRRDF },
{ "slxt", 0x48, INSTR_RXF_FRRDF },
{ "srdt", 0x41, INSTR_RXF_FRRDF }, { "srdt", 0x41, INSTR_RXF_FRRDF },
{ "slxt", 0x48, INSTR_RXF_FRRDF },
{ "srxt", 0x49, INSTR_RXF_FRRDF }, { "srxt", 0x49, INSTR_RXF_FRRDF },
{ "tdcet", 0x50, INSTR_RXE_FRRD }, { "tdcet", 0x50, INSTR_RXE_FRRD },
{ "tdcdt", 0x54, INSTR_RXE_FRRD },
{ "tdcxt", 0x58, INSTR_RXE_FRRD },
{ "tdget", 0x51, INSTR_RXE_FRRD }, { "tdget", 0x51, INSTR_RXE_FRRD },
{ "tdcdt", 0x54, INSTR_RXE_FRRD },
{ "tdgdt", 0x55, INSTR_RXE_FRRD }, { "tdgdt", 0x55, INSTR_RXE_FRRD },
{ "tdcxt", 0x58, INSTR_RXE_FRRD },
{ "tdgxt", 0x59, INSTR_RXE_FRRD }, { "tdgxt", 0x59, INSTR_RXE_FRRD },
{ "ley", 0x64, INSTR_RXY_FRRD },
{ "ldy", 0x65, INSTR_RXY_FRRD },
{ "stey", 0x66, INSTR_RXY_FRRD },
{ "stdy", 0x67, INSTR_RXY_FRRD },
{ "czdt", 0xa8, INSTR_RSL_LRDFU },
{ "czxt", 0xa9, INSTR_RSL_LRDFU },
{ "cdzt", 0xaa, INSTR_RSL_LRDFU },
{ "cxzt", 0xab, INSTR_RSL_LRDFU },
#endif #endif
{ "ldeb", 0x04, INSTR_RXE_FRRD }, { "ldeb", 0x04, INSTR_RXE_FRRD },
{ "lxdb", 0x05, INSTR_RXE_FRRD }, { "lxdb", 0x05, INSTR_RXE_FRRD },
......
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