diff --git a/arch/ia64/sn/include/xtalk/hubdev.h b/arch/ia64/sn/include/xtalk/hubdev.h index 868e7ecae84b7494628c241a26954dcd83fabd48..580a1c0403a73c373c60cf34cc59f985bb5a16f0 100644 --- a/arch/ia64/sn/include/xtalk/hubdev.h +++ b/arch/ia64/sn/include/xtalk/hubdev.h @@ -8,6 +8,8 @@ #ifndef _ASM_IA64_SN_XTALK_HUBDEV_H #define _ASM_IA64_SN_XTALK_HUBDEV_H +#include "xtalk/xwidgetdev.h" + #define HUB_WIDGET_ID_MAX 0xf #define DEV_PER_WIDGET (2*2*8) #define IIO_ITTE_WIDGET_BITS 4 /* size of widget field */ diff --git a/arch/ia64/sn/kernel/io_init.c b/arch/ia64/sn/kernel/io_init.c index 2f03e3f52b63774df9e55b6ec6cb6c72cb5d8d1f..041c4be02b2ac46b35b006466c80648f83a254ff 100644 --- a/arch/ia64/sn/kernel/io_init.c +++ b/arch/ia64/sn/kernel/io_init.c @@ -9,17 +9,17 @@ #include #include #include -#include #include -#include -#include -#include "pci/pcibr_provider.h" -#include "xtalk/xwidgetdev.h" #include -#include "xtalk/hubdev.h" #include +#include +#include +#include #include +#include #include +#include "xtalk/hubdev.h" +#include "xtalk/xwidgetdev.h" nasid_t master_nasid = INVALID_NASID; /* Partition Master */ @@ -226,7 +226,7 @@ static void sn_fixup_ionodes(void) * from our PCI provider include PIO maps to BAR space and interrupt * objects. */ -static void sn_pci_fixup_slot(struct pci_dev *dev) +void sn_pci_fixup_slot(struct pci_dev *dev) { int idx; int segment = 0; diff --git a/arch/ia64/sn/kernel/irq.c b/arch/ia64/sn/kernel/irq.c index e6f7551edfda49e8d22e9378a7d09a63ff009d0d..cf4dbf9645f1d1999d00639f3f9b07872123caa8 100644 --- a/arch/ia64/sn/kernel/irq.c +++ b/arch/ia64/sn/kernel/irq.c @@ -10,13 +10,12 @@ #include #include -#include #include #include -#include "xtalk/xwidgetdev.h" +#include +#include #include #include -#include "pci/pcibr_provider.h" #include #include diff --git a/arch/ia64/sn/pci/pci_dma.c b/arch/ia64/sn/pci/pci_dma.c index 5da9bdbde7cb829dbef14774cf5bf2c9d568f8d5..a2f7a88aefbb0bd925647668acc641438ac73b5c 100644 --- a/arch/ia64/sn/pci/pci_dma.c +++ b/arch/ia64/sn/pci/pci_dma.c @@ -11,9 +11,10 @@ #include #include -#include +#include #include #include +#include #define SG_ENT_VIRT_ADDRESS(sg) (page_address((sg)->page) + (sg)->offset) #define SG_ENT_PHYS_ADDRESS(SG) virt_to_phys(SG_ENT_VIRT_ADDRESS(SG)) diff --git a/arch/ia64/sn/pci/pcibr/pcibr_ate.c b/arch/ia64/sn/pci/pcibr/pcibr_ate.c index 0e47bce85f2da0e1494ff5f705c8fa91b59ae161..d1647b863e6106a3d17219c4b9748633dc165630 100644 --- a/arch/ia64/sn/pci/pcibr/pcibr_ate.c +++ b/arch/ia64/sn/pci/pcibr/pcibr_ate.c @@ -8,9 +8,9 @@ #include #include +#include #include #include -#include "pci/pcibr_provider.h" int pcibr_invalidate_ate = 0; /* by default don't invalidate ATE on free */ diff --git a/arch/ia64/sn/pci/pcibr/pcibr_dma.c b/arch/ia64/sn/pci/pcibr/pcibr_dma.c index 64af2b2c17879181e0610cdaa7fb10dfdb8bf26e..b058dc2a0b9d3dfb7a17fe73f2ae35f72266ebd3 100644 --- a/arch/ia64/sn/pci/pcibr/pcibr_dma.c +++ b/arch/ia64/sn/pci/pcibr/pcibr_dma.c @@ -8,18 +8,17 @@ #include #include -#include +#include #include -#include "xtalk/xwidgetdev.h" -#include "xtalk/hubdev.h" +#include #include #include -#include "pci/tiocp.h" -#include "pci/pic.h" -#include "pci/pcibr_provider.h" -#include "pci/tiocp.h" +#include +#include +#include #include "tio.h" -#include +#include "xtalk/xwidgetdev.h" +#include "xtalk/hubdev.h" extern int sn_ioif_inited; diff --git a/arch/ia64/sn/pci/pcibr/pcibr_provider.c b/arch/ia64/sn/pci/pcibr/pcibr_provider.c index 3893999d23d8871a7f5f6bf4315b24d713391411..9bc4de4a3ec0778aa4724e75457bd253a6b1e45e 100644 --- a/arch/ia64/sn/pci/pcibr/pcibr_provider.c +++ b/arch/ia64/sn/pci/pcibr/pcibr_provider.c @@ -6,18 +6,17 @@ * Copyright (C) 2001-2004 Silicon Graphics, Inc. All rights reserved. */ -#include #include +#include #include -#include -#include "xtalk/xwidgetdev.h" +#include #include -#include "xtalk/hubdev.h" +#include #include #include -#include "pci/pcibr_provider.h" -#include - +#include +#include "xtalk/xwidgetdev.h" +#include "xtalk/hubdev.h" static int sal_pcibr_error_interrupt(struct pcibus_info *soft) { diff --git a/arch/ia64/sn/pci/pcibr/pcibr_reg.c b/arch/ia64/sn/pci/pcibr/pcibr_reg.c index 865c11c3b50a06cbcd31d39b1bf152bfe12e8606..21426d02fbe6a84fa818535600d145ea850e8c1c 100644 --- a/arch/ia64/sn/pci/pcibr/pcibr_reg.c +++ b/arch/ia64/sn/pci/pcibr/pcibr_reg.c @@ -6,13 +6,13 @@ * Copyright (C) 2004 Silicon Graphics, Inc. All rights reserved. */ -#include #include +#include +#include #include #include -#include "pci/tiocp.h" -#include "pci/pic.h" -#include "pci/pcibr_provider.h" +#include +#include union br_ptr { struct tiocp tio; diff --git a/arch/ia64/sn/include/pci/pcibr_provider.h b/include/asm-ia64/sn/pcibr_provider.h similarity index 98% rename from arch/ia64/sn/include/pci/pcibr_provider.h rename to include/asm-ia64/sn/pcibr_provider.h index 1cd291d8badd05299c4dc4114bd1e768ddd46f61..cbb4604c934902fc7f69f022a4f3ccc4922df270 100644 --- a/arch/ia64/sn/include/pci/pcibr_provider.h +++ b/include/asm-ia64/sn/pcibr_provider.h @@ -8,6 +8,9 @@ #ifndef _ASM_IA64_SN_PCI_PCIBR_PROVIDER_H #define _ASM_IA64_SN_PCI_PCIBR_PROVIDER_H +#include +#include + /* Workarounds */ #define PV907516 (1 << 1) /* TIOCP: Don't write the write buffer flush reg */ @@ -20,7 +23,7 @@ #define IS_PIC_SOFT(ps) (ps->pbi_bridge_type == PCIBR_BRIDGETYPE_PIC) -/* +/* * The different PCI Bridge types supported on the SGI Altix platforms */ #define PCIBR_BRIDGETYPE_UNKNOWN -1 @@ -100,7 +103,7 @@ struct pcibus_info { struct ate_resource pbi_int_ate_resource; uint64_t pbi_int_ate_size; - + uint64_t pbi_dir_xbase; char pbi_hub_xid; diff --git a/include/asm-ia64/sn/pcidev.h b/include/asm-ia64/sn/pcidev.h index 42aea21ee18710b060cd2d3be8df0defb830468f..9610fcc635450e57bf9be693fb8fa5e22eb60be1 100644 --- a/include/asm-ia64/sn/pcidev.h +++ b/include/asm-ia64/sn/pcidev.h @@ -13,6 +13,8 @@ #define SN_PCIDEV_INFO(pci_dev) \ ((struct pcidev_info *)(pci_dev)->sysdata) +#define SN_PCIBUS_BUSSOFT_INFO(pci_bus) \ + (struct pcibus_info *)((struct pcibus_bussoft *)(PCI_CONTROLLER((pci_bus))->platform_data)) /* * Given a pci_bus, return the sn pcibus_bussoft struct. Note that * this only works for root busses, not for busses represented by PPB's. @@ -53,6 +55,8 @@ struct pcidev_info { extern void sn_irq_fixup(struct pci_dev *pci_dev, struct sn_irq_info *sn_irq_info); - +extern void sn_irq_unfixup(struct pci_dev *pci_dev); +extern void sn_pci_fixup_slot(struct pci_dev *dev); +extern void sn_pci_unfixup_slot(struct pci_dev *dev); extern void sn_irq_lh_init(void); #endif /* _ASM_IA64_SN_PCI_PCIDEV_H */ diff --git a/arch/ia64/sn/include/pci/pic.h b/include/asm-ia64/sn/pic.h similarity index 98% rename from arch/ia64/sn/include/pci/pic.h rename to include/asm-ia64/sn/pic.h index fd18acecb1e67e783c4085f27eb7e6390af0a47d..0de82e6b08936a33f64f9f5b7b518b89d6ddecdb 100644 --- a/arch/ia64/sn/include/pci/pic.h +++ b/include/asm-ia64/sn/pic.h @@ -15,7 +15,7 @@ * PIC handles PCI/X busses. PCI/X requires that the 'bridge' (i.e. PIC) * be designated as 'device 0'. That is a departure from earlier SGI * PCI bridges. Because of that we use config space 1 to access the - * config space of the first actual PCI device on the bus. + * config space of the first actual PCI device on the bus. * Here's what the PIC manual says: * * The current PCI-X bus specification now defines that the parent @@ -29,14 +29,14 @@ * correlated Configs pace and our device space 0 <-> 0, 1 <-> 1, etc. * PCI-X requires we start a 1, not 0 and currently the PX brick * does associate our: - * + * * device 0 with configuration space window 1, - * device 1 with configuration space window 2, + * device 1 with configuration space window 2, * device 2 with configuration space window 3, * device 3 with configuration space window 4. * - * The net effect is that all config space access are off-by-one with - * relation to other per-slot accesses on the PIC. + * The net effect is that all config space access are off-by-one with + * relation to other per-slot accesses on the PIC. * Here is a table that shows some of that: * * Internal Slot# @@ -65,7 +65,7 @@ *****************************************************************************/ /* NOTE: PIC WAR. PV#854697. PIC does not allow writes just to [31:0] - * of a 64-bit register. When writing PIC registers, always write the + * of a 64-bit register. When writing PIC registers, always write the * entire 64 bits. */ @@ -164,7 +164,7 @@ struct pic { uint64_t clear_all; /* 0x000{438,,,5F8} */ } p_buf_count[8]; - + /* 0x000600-0x0009FF -- PCI/X registers */ uint64_t p_pcix_bus_err_addr; /* 0x000600 */ uint64_t p_pcix_bus_err_attr; /* 0x000608 */ diff --git a/arch/ia64/sn/include/pci/tiocp.h b/include/asm-ia64/sn/tiocp.h similarity index 99% rename from arch/ia64/sn/include/pci/tiocp.h rename to include/asm-ia64/sn/tiocp.h index f07c83b2bf6ebb8e9c907c2f9948a1169554601a..5f2489c9d2ddd668f0bfc4b6c9f59dca6cc5b8e0 100644 --- a/arch/ia64/sn/include/pci/tiocp.h +++ b/include/asm-ia64/sn/tiocp.h @@ -111,7 +111,7 @@ struct tiocp{ uint64_t clear_all; /* 0x000{438,,,5F8} */ } cp_buf_count[8]; - + /* 0x000600-0x0009FF -- PCI/X registers */ uint64_t cp_pcix_bus_err_addr; /* 0x000600 */ uint64_t cp_pcix_bus_err_attr; /* 0x000608 */