提交 bded6c03 编写于 作者: A Akshu Agrawal 提交者: Stephen Boyd

clk: x86: Set default parent to 48Mhz

System clk provided in ST soc can be set to:
48Mhz, non-spread
25Mhz, spread
To get accurate rate, we need it to set it at non-spread
option which is 48Mhz.
Signed-off-by: NAkshu Agrawal <akshu.agrawal@amd.com>
Reviewed-by: NDaniel Kurtz <djkurtz@chromium.org>
Fixes: 421bf6a1 ("clk: x86: Add ST oscout platform clock")
Signed-off-by: NStephen Boyd <sboyd@kernel.org>
上级 450b6b9b
...@@ -46,7 +46,7 @@ static int st_clk_probe(struct platform_device *pdev) ...@@ -46,7 +46,7 @@ static int st_clk_probe(struct platform_device *pdev)
clk_oscout1_parents, ARRAY_SIZE(clk_oscout1_parents), clk_oscout1_parents, ARRAY_SIZE(clk_oscout1_parents),
0, st_data->base + CLKDRVSTR2, OSCOUT1CLK25MHZ, 3, 0, NULL); 0, st_data->base + CLKDRVSTR2, OSCOUT1CLK25MHZ, 3, 0, NULL);
clk_set_parent(hws[ST_CLK_MUX]->clk, hws[ST_CLK_25M]->clk); clk_set_parent(hws[ST_CLK_MUX]->clk, hws[ST_CLK_48M]->clk);
hws[ST_CLK_GATE] = clk_hw_register_gate(NULL, "oscout1", "oscout1_mux", hws[ST_CLK_GATE] = clk_hw_register_gate(NULL, "oscout1", "oscout1_mux",
0, st_data->base + MISCCLKCNTL1, OSCCLKENB, 0, st_data->base + MISCCLKCNTL1, OSCCLKENB,
......
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