drm/nouveau/clk: switch to subdev printk macros

Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c

@@ -76,8 +76,10 @@ nvkm_clk_adjust(struct nvkm_clk *clk, bool adjust,
 static int
 nvkm_cstate_prog(struct nvkm_clk *clk, struct nvkm_pstate *pstate, int cstatei)
 {
-	struct nvkm_therm *therm = nvkm_therm(clk);
-	struct nvkm_volt *volt = nvkm_volt(clk);
+	struct nvkm_subdev *subdev = &clk->subdev;
+	struct nvkm_device *device = subdev->device;
+	struct nvkm_therm *therm = device->therm;
+	struct nvkm_volt *volt = device->volt;
 	struct nvkm_cstate *cstate;
 	int ret;
 
@@ -90,7 +92,7 @@ nvkm_cstate_prog(struct nvkm_clk *clk, struct nvkm_pstate *pstate, int cstatei)
 	if (therm) {
 		ret = nvkm_therm_cstate(therm, pstate->fanspeed, +1);
 		if (ret && ret != -ENODEV) {
-			nv_error(clk, "failed to raise fan speed: %d\n", ret);
+			nvkm_error(subdev, "failed to raise fan speed: %d\n", ret);
 			return ret;
 		}
 	}
@@ -98,7 +100,7 @@ nvkm_cstate_prog(struct nvkm_clk *clk, struct nvkm_pstate *pstate, int cstatei)
 	if (volt) {
 		ret = volt->set_id(volt, cstate->voltage, +1);
 		if (ret && ret != -ENODEV) {
-			nv_error(clk, "failed to raise voltage: %d\n", ret);
+			nvkm_error(subdev, "failed to raise voltage: %d\n", ret);
 			return ret;
 		}
 	}
@@ -112,13 +114,13 @@ nvkm_cstate_prog(struct nvkm_clk *clk, struct nvkm_pstate *pstate, int cstatei)
 	if (volt) {
 		ret = volt->set_id(volt, cstate->voltage, -1);
 		if (ret && ret != -ENODEV)
-			nv_error(clk, "failed to lower voltage: %d\n", ret);
+			nvkm_error(subdev, "failed to lower voltage: %d\n", ret);
 	}
 
 	if (therm) {
 		ret = nvkm_therm_cstate(therm, pstate->fanspeed, -1);
 		if (ret && ret != -ENODEV)
-			nv_error(clk, "failed to lower fan speed: %d\n", ret);
+			nvkm_error(subdev, "failed to lower fan speed: %d\n", ret);
 	}
 
 	return ret;
@@ -171,7 +173,8 @@ nvkm_cstate_new(struct nvkm_clk *clk, int idx, struct nvkm_pstate *pstate)
 static int
 nvkm_pstate_prog(struct nvkm_clk *clk, int pstatei)
 {
-	struct nvkm_fb *fb = nvkm_fb(clk);
+	struct nvkm_subdev *subdev = &clk->subdev;
+	struct nvkm_fb *fb = subdev->device->fb;
 	struct nvkm_pstate *pstate;
 	int ret, idx = 0;
 
@@ -180,7 +183,7 @@ nvkm_pstate_prog(struct nvkm_clk *clk, int pstatei)
 			break;
 	}
 
-	nv_debug(clk, "setting performance state %d\n", pstatei);
+	nvkm_debug(subdev, "setting performance state %d\n", pstatei);
 	clk->pstate = pstatei;
 
 	if (fb->ram && fb->ram->calc) {
@@ -200,13 +203,14 @@ static void
 nvkm_pstate_work(struct work_struct *work)
 {
 	struct nvkm_clk *clk = container_of(work, typeof(*clk), work);
+	struct nvkm_subdev *subdev = &clk->subdev;
 	int pstate;
 
 	if (!atomic_xchg(&clk->waiting, 0))
 		return;
 	clk->pwrsrc = power_supply_is_system_supplied();
 
-	nv_trace(clk, "P %d PWR %d U(AC) %d U(DC) %d A %d T %d D %d\n",
+	nvkm_trace(subdev, "P %d PWR %d U(AC) %d U(DC) %d A %d T %d D %d\n",
 		   clk->pstate, clk->pwrsrc, clk->ustate_ac, clk->ustate_dc,
 		   clk->astate, clk->tstate, clk->dstate);
 
@@ -219,11 +223,11 @@ nvkm_pstate_work(struct work_struct *work)
 		pstate = clk->pstate = -1;
 	}
 
-	nv_trace(clk, "-> %d\n", pstate);
+	nvkm_trace(subdev, "-> %d\n", pstate);
 	if (pstate != clk->pstate) {
 		int ret = nvkm_pstate_prog(clk, pstate);
 		if (ret) {
-			nv_error(clk, "error setting pstate %d: %d\n",
+			nvkm_error(subdev, "error setting pstate %d: %d\n",
 				   pstate, ret);
 		}
 	}
@@ -247,6 +251,7 @@ nvkm_pstate_info(struct nvkm_clk *clk, struct nvkm_pstate *pstate)
 {
 	struct nvkm_domain *clock = clk->domains - 1;
 	struct nvkm_cstate *cstate;
+	struct nvkm_subdev *subdev = &clk->subdev;
 	char info[3][32] = { "", "", "" };
 	char name[4] = "--";
 	int i = -1;
@@ -260,12 +265,12 @@ nvkm_pstate_info(struct nvkm_clk *clk, struct nvkm_pstate *pstate)
 		if (hi == 0)
 			continue;
 
-		nv_debug(clk, "%02x: %10d KHz\n", clock->name, lo);
+		nvkm_debug(subdev, "%02x: %10d KHz\n", clock->name, lo);
 		list_for_each_entry(cstate, &pstate->list, head) {
 			u32 freq = cstate->domain[clock->name];
 			lo = min(lo, freq);
 			hi = max(hi, freq);
-			nv_debug(clk, "%10d KHz\n", freq);
+			nvkm_debug(subdev, "%10d KHz\n", freq);
 		}
 
 		if (clock->mname && ++i < ARRAY_SIZE(info)) {
@@ -281,7 +286,7 @@ nvkm_pstate_info(struct nvkm_clk *clk, struct nvkm_pstate *pstate)
 		}
 	}
 
-	nv_info(clk, "%s: %s %s %s\n", name, info[0], info[1], info[2]);
+	nvkm_debug(subdev, "%s: %s %s %s\n", name, info[0], info[1], info[2]);
 }
 
 static void
@@ -481,6 +486,7 @@ int
 _nvkm_clk_init(struct nvkm_object *object)
 {
 	struct nvkm_clk *clk = (void *)object;
+	struct nvkm_subdev *subdev = &clk->subdev;
 	struct nvkm_domain *clock = clk->domains;
 	int ret;
 
@@ -495,7 +501,7 @@ _nvkm_clk_init(struct nvkm_object *object)
 	while (clock->name != nv_clk_src_max) {
 		ret = clk->read(clk, clock->name);
 		if (ret < 0) {
-			nv_error(clk, "%02x freq unknown\n", clock->name);
+			nvkm_error(subdev, "%02x freq unknown\n", clock->name);
 			return ret;
 		}
 		clk->bstate.base.domain[clock->name] = ret;

drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c

@@ -149,7 +149,8 @@ static int
 gf100_clk_read(struct nvkm_clk *obj, enum nv_clk_src src)
 {
 	struct gf100_clk *clk = container_of(obj, typeof(*clk), base);
-	struct nvkm_device *device = clk->base.subdev.device;
+	struct nvkm_subdev *subdev = &clk->base.subdev;
+	struct nvkm_device *device = subdev->device;
 
 	switch (src) {
 	case nv_clk_src_crystal:
@@ -191,7 +192,7 @@ gf100_clk_read(struct nvkm_clk *obj, enum nv_clk_src src)
 	case nv_clk_src_vdec:
 		return read_clk(clk, 0x0e);
 	default:
-		nv_error(clk, "invalid clock source %d\n", src);
+		nvkm_error(subdev, "invalid clock source %d\n", src);
 		return -EINVAL;
 	}
 }

drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c

@@ -188,7 +188,8 @@ static int
 gk104_clk_read(struct nvkm_clk *obj, enum nv_clk_src src)
 {
 	struct gk104_clk *clk = container_of(obj, typeof(*clk), base);
-	struct nvkm_device *device = clk->base.subdev.device;
+	struct nvkm_subdev *subdev = &clk->base.subdev;
+	struct nvkm_device *device = subdev->device;
 
 	switch (src) {
 	case nv_clk_src_crystal:
@@ -212,7 +213,7 @@ gk104_clk_read(struct nvkm_clk *obj, enum nv_clk_src src)
 	case nv_clk_src_vdec:
 		return read_clk(clk, 0x0e);
 	default:
-		nv_error(clk, "invalid clock source %d\n", src);
+		nvkm_error(subdev, "invalid clock source %d\n", src);
 		return -EINVAL;
 	}
 }

drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c

@@ -151,6 +151,7 @@ gk20a_pllg_calc_rate(struct gk20a_clk *clk)
 static int
 gk20a_pllg_calc_mnp(struct gk20a_clk *clk, unsigned long rate)
 {
+	struct nvkm_subdev *subdev = &clk->base.subdev;
 	u32 target_clk_f, ref_clk_f, target_freq;
 	u32 min_vco_f, max_vco_f;
 	u32 low_pl, high_pl, best_pl;
@@ -198,7 +199,7 @@ gk20a_pllg_calc_mnp(struct gk20a_clk *clk, unsigned long rate)
 		}
 	}
 
-	nv_debug(clk, "low_PL %d(div%d), high_PL %d(div%d)", low_pl,
+	nvkm_debug(subdev, "low_PL %d(div%d), high_PL %d(div%d)", low_pl,
 		   pl_to_div[low_pl], high_pl, pl_to_div[high_pl]);
 
 	/* Select lowest possible VCO */
@@ -249,7 +250,8 @@ gk20a_pllg_calc_mnp(struct gk20a_clk *clk, unsigned long rate)
 	WARN_ON(best_delta == ~0);
 
 	if (best_delta != 0)
-		nv_debug(clk, "no best match for target @ %dMHz on gpc_pll",
+		nvkm_debug(subdev,
+			   "no best match for target @ %dMHz on gpc_pll",
 			   target_clk_f);
 
 	clk->m = best_m;
@@ -258,7 +260,8 @@ gk20a_pllg_calc_mnp(struct gk20a_clk *clk, unsigned long rate)
 
 	target_freq = gk20a_pllg_calc_rate(clk) / MHZ;
 
-	nv_debug(clk, "actual target freq %d MHz, M %d, N %d, PL %d(div%d)\n",
+	nvkm_debug(subdev,
+		   "actual target freq %d MHz, M %d, N %d, PL %d(div%d)\n",
 		   target_freq, clk->m, clk->n, clk->pl, pl_to_div[clk->pl]);
 	return 0;
 }
@@ -266,7 +269,8 @@ gk20a_pllg_calc_mnp(struct gk20a_clk *clk, unsigned long rate)
 static int
 gk20a_pllg_slide(struct gk20a_clk *clk, u32 n)
 {
-	struct nvkm_device *device = clk->base.subdev.device;
+	struct nvkm_subdev *subdev = &clk->base.subdev;
+	struct nvkm_device *device = subdev->device;
 	u32 val;
 	int ramp_timeout;
 
@@ -314,7 +318,7 @@ gk20a_pllg_slide(struct gk20a_clk *clk, u32 n)
 	nvkm_rd32(device, GPCPLL_NDIV_SLOWDOWN);
 
 	if (ramp_timeout <= 0) {
-		nv_error(clk, "gpcpll dynamic ramp timeout\n");
+		nvkm_error(subdev, "gpcpll dynamic ramp timeout\n");
 		return -ETIMEDOUT;
 	}
 
@@ -340,7 +344,8 @@ _gk20a_pllg_disable(struct gk20a_clk *clk)
 static int
 _gk20a_pllg_program_mnp(struct gk20a_clk *clk, bool allow_slide)
 {
-	struct nvkm_device *device = clk->base.subdev.device;
+	struct nvkm_subdev *subdev = &clk->base.subdev;
+	struct nvkm_device *device = subdev->device;
 	u32 val, cfg;
 	u32 m_old, pl_old, n_lo;
 
@@ -387,8 +392,8 @@ _gk20a_pllg_program_mnp(struct gk20a_clk *clk, bool allow_slide)
 
 	_gk20a_pllg_disable(clk);
 
-	nv_debug(clk, "%s: m=%d n=%d pl=%d\n", __func__, clk->m, clk->n,
-		 clk->pl);
+	nvkm_debug(subdev, "%s: m=%d n=%d pl=%d\n", __func__,
+		   clk->m, clk->n, clk->pl);
 
 	n_lo = DIV_ROUND_UP(clk->m * clk->params->min_vco,
 			    clk->parent_rate / MHZ);
@@ -567,7 +572,8 @@ static int
 gk20a_clk_read(struct nvkm_clk *obj, enum nv_clk_src src)
 {
 	struct gk20a_clk *clk = container_of(obj, typeof(*clk), base);
-	struct nvkm_device *device = clk->base.subdev.device;
+	struct nvkm_subdev *subdev = &clk->base.subdev;
+	struct nvkm_device *device = subdev->device;
 
 	switch (src) {
 	case nv_clk_src_crystal:
@@ -576,7 +582,7 @@ gk20a_clk_read(struct nvkm_clk *obj, enum nv_clk_src src)
 		gk20a_pllg_read_mnp(clk);
 		return gk20a_pllg_calc_rate(clk) / GK20A_CLK_GPC_MDIV;
 	default:
-		nv_error(clk, "invalid clock source %d\n", src);
+		nvkm_error(subdev, "invalid clock source %d\n", src);
 		return -EINVAL;
 	}
 }
@@ -620,7 +626,8 @@ static int
 gk20a_clk_init(struct nvkm_object *object)
 {
 	struct gk20a_clk *clk = (void *)object;
-	struct nvkm_device *device = clk->base.subdev.device;
+	struct nvkm_subdev *subdev = &clk->base.subdev;
+	struct nvkm_device *device = subdev->device;
 	int ret;
 
 	nvkm_mask(device, GPC2CLK_OUT, GPC2CLK_OUT_INIT_MASK, GPC2CLK_OUT_INIT_VAL);
@@ -631,7 +638,7 @@ gk20a_clk_init(struct nvkm_object *object)
 
 	ret = gk20a_clk_prog(&clk->base);
 	if (ret) {
-		nv_error(clk, "cannot initialize clock\n");
+		nvkm_error(subdev, "cannot initialize clock\n");
 		return ret;
 	}
 
@@ -665,7 +672,8 @@ gk20a_clk_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
 
 	plat = nv_device_to_platform(nv_device(parent));
 	clk->parent_rate = clk_get_rate(plat->gpu->clk);
-	nv_info(clk, "parent clock rate: %d Mhz\n", clk->parent_rate / MHZ);
+	nvkm_info(&clk->base.subdev, "parent clock rate: %d Mhz\n",
+		  clk->parent_rate / MHZ);
 
 	clk->base.read = gk20a_clk_read;
 	clk->base.calc = gk20a_clk_calc;

drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c

@@ -139,7 +139,8 @@ static int
 gt215_clk_read(struct nvkm_clk *obj, enum nv_clk_src src)
 {
 	struct gt215_clk *clk = container_of(obj, typeof(*clk), base);
-	struct nvkm_device *device = clk->base.subdev.device;
+	struct nvkm_subdev *subdev = &clk->base.subdev;
+	struct nvkm_device *device = subdev->device;
 	u32 hsrc;
 
 	switch (src) {
@@ -167,11 +168,11 @@ gt215_clk_read(struct nvkm_clk *obj, enum nv_clk_src src)
 		case 3:
 			return 277000;
 		default:
-			nv_error(clk, "unknown HOST clock source %d\n", hsrc);
+			nvkm_error(subdev, "unknown HOST clock source %d\n", hsrc);
 			return -EINVAL;
 		}
 	default:
-		nv_error(clk, "invalid clock source %d\n", src);
+		nvkm_error(subdev, "invalid clock source %d\n", src);
 		return -EINVAL;
 	}
 

drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c

@@ -80,7 +80,8 @@ static int
 mcp77_clk_read(struct nvkm_clk *obj, enum nv_clk_src src)
 {
 	struct mcp77_clk *clk = container_of(obj, typeof(*clk), base);
-	struct nvkm_device *device = clk->base.subdev.device;
+	struct nvkm_subdev *subdev = &clk->base.subdev;
+	struct nvkm_device *device = subdev->device;
 	u32 mast = nvkm_rd32(device, 0x00c054);
 	u32 P = 0;
 
@@ -155,7 +156,7 @@ mcp77_clk_read(struct nvkm_clk *obj, enum nv_clk_src src)
 		break;
 	}
 
-	nv_debug(clk, "unknown clock source %d 0x%08x\n", src, mast);
+	nvkm_debug(subdev, "unknown clock source %d %08x\n", src, mast);
 	return 0;
 }
 
@@ -204,6 +205,7 @@ mcp77_clk_calc(struct nvkm_clk *obj, struct nvkm_cstate *cstate)
 	const int shader = cstate->domain[nv_clk_src_shader];
 	const int core = cstate->domain[nv_clk_src_core];
 	const int vdec = cstate->domain[nv_clk_src_vdec];
+	struct nvkm_subdev *subdev = &clk->base.subdev;
 	u32 out = 0, clock = 0;
 	int N, M, P1, P2 = 0;
 	int divs = 0;
@@ -267,27 +269,27 @@ mcp77_clk_calc(struct nvkm_clk *obj, struct nvkm_cstate *cstate)
 	}
 
 	/* Print strategy! */
-	nv_debug(clk, "nvpll: %08x %08x %08x\n",
+	nvkm_debug(subdev, "nvpll: %08x %08x %08x\n",
 		   clk->ccoef, clk->cpost, clk->cctrl);
-	nv_debug(clk, " spll: %08x %08x %08x\n",
+	nvkm_debug(subdev, " spll: %08x %08x %08x\n",
 		   clk->scoef, clk->spost, clk->sctrl);
-	nv_debug(clk, " vdiv: %08x\n", clk->vdiv);
+	nvkm_debug(subdev, " vdiv: %08x\n", clk->vdiv);
 	if (clk->csrc == nv_clk_src_hclkm4)
-		nv_debug(clk, "core: hrefm4\n");
+		nvkm_debug(subdev, "core: hrefm4\n");
 	else
-		nv_debug(clk, "core: nvpll\n");
+		nvkm_debug(subdev, "core: nvpll\n");
 
 	if (clk->ssrc == nv_clk_src_hclkm4)
-		nv_debug(clk, "shader: hrefm4\n");
+		nvkm_debug(subdev, "shader: hrefm4\n");
 	else if (clk->ssrc == nv_clk_src_core)
-		nv_debug(clk, "shader: nvpll\n");
+		nvkm_debug(subdev, "shader: nvpll\n");
 	else
-		nv_debug(clk, "shader: spll\n");
+		nvkm_debug(subdev, "shader: spll\n");
 
 	if (clk->vsrc == nv_clk_src_hclkm4)
-		nv_debug(clk, "vdec: 500MHz\n");
+		nvkm_debug(subdev, "vdec: 500MHz\n");
 	else
-		nv_debug(clk, "vdec: core\n");
+		nvkm_debug(subdev, "vdec: core\n");
 
 	return 0;
 }
@@ -296,7 +298,8 @@ static int
 mcp77_clk_prog(struct nvkm_clk *obj)
 {
 	struct mcp77_clk *clk = container_of(obj, typeof(*clk), base);
-	struct nvkm_device *device = clk->base.subdev.device;
+	struct nvkm_subdev *subdev = &clk->base.subdev;
+	struct nvkm_device *device = subdev->device;
 	u32 pllmask = 0, mast;
 	unsigned long flags;
 	unsigned long *f = &flags;
@@ -324,7 +327,7 @@ mcp77_clk_prog(struct nvkm_clk *obj)
 		mast |= 0x00000003;
 		break;
 	default:
-		nv_warn(clk,"Reclocking failed: unknown core clock\n");
+		nvkm_warn(subdev, "Reclocking failed: unknown core clock\n");
 		goto resume;
 	}
 
@@ -345,7 +348,7 @@ mcp77_clk_prog(struct nvkm_clk *obj)
 		mast |= 0x00000030;
 		break;
 	default:
-		nv_warn(clk,"Reclocking failed: unknown sclk clock\n");
+		nvkm_warn(subdev, "Reclocking failed: unknown sclk clock\n");
 		goto resume;
 	}
 

drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c

@@ -106,7 +106,8 @@ static int
 nv40_clk_read(struct nvkm_clk *obj, enum nv_clk_src src)
 {
 	struct nv40_clk *clk = container_of(obj, typeof(*clk), base);
-	struct nvkm_device *device = clk->base.subdev.device;
+	struct nvkm_subdev *subdev = &clk->base.subdev;
+	struct nvkm_device *device = subdev->device;
 	u32 mast = nvkm_rd32(device, 0x00c040);
 
 	switch (src) {
@@ -124,7 +125,7 @@ nv40_clk_read(struct nvkm_clk *obj, enum nv_clk_src src)
 		break;
 	}
 
-	nv_debug(clk, "unknown clock source %d 0x%08x\n", src, mast);
+	nvkm_debug(subdev, "unknown clock source %d %08x\n", src, mast);
 	return -EINVAL;
 }
 

drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c

@@ -51,7 +51,8 @@ read_div(struct nv50_clk *clk)
 static u32
 read_pll_src(struct nv50_clk *clk, u32 base)
 {
-	struct nvkm_device *device = clk->base.subdev.device;
+	struct nvkm_subdev *subdev = &clk->base.subdev;
+	struct nvkm_device *device = subdev->device;
 	u32 coef, ref = clk->base.read(&clk->base, nv_clk_src_crystal);
 	u32 rsel = nvkm_rd32(device, 0x00e18c);
 	int P, N, M, id;
@@ -65,7 +66,7 @@ read_pll_src(struct nv50_clk *clk, u32 base)
 		case 0x4008: id = !!(rsel & 0x00000008); break;
 		case 0x4030: id = 0; break;
 		default:
-			nv_error(clk, "ref: bad pll 0x%06x\n", base);
+			nvkm_error(subdev, "ref: bad pll %06x\n", base);
 			return 0;
 		}
 
@@ -93,7 +94,7 @@ read_pll_src(struct nv50_clk *clk, u32 base)
 		case 0x4028: rsel = (rsel & 0x00001800) >> 11; break;
 		case 0x4030: rsel = 3; break;
 		default:
-			nv_error(clk, "ref: bad pll 0x%06x\n", base);
+			nvkm_error(subdev, "ref: bad pll %06x\n", base);
 			return 0;
 		}
 
@@ -123,7 +124,8 @@ read_pll_src(struct nv50_clk *clk, u32 base)
 static u32
 read_pll_ref(struct nv50_clk *clk, u32 base)
 {
-	struct nvkm_device *device = clk->base.subdev.device;
+	struct nvkm_subdev *subdev = &clk->base.subdev;
+	struct nvkm_device *device = subdev->device;
 	u32 src, mast = nvkm_rd32(device, 0x00c040);
 
 	switch (base) {
@@ -142,7 +144,7 @@ read_pll_ref(struct nv50_clk *clk, u32 base)
 	case 0x00e810:
 		return clk->base.read(&clk->base, nv_clk_src_crystal);
 	default:
-		nv_error(clk, "bad pll 0x%06x\n", base);
+		nvkm_error(subdev, "bad pll %06x\n", base);
 		return 0;
 	}
 
@@ -190,7 +192,8 @@ static int
 nv50_clk_read(struct nvkm_clk *obj, enum nv_clk_src src)
 {
 	struct nv50_clk *clk = container_of(obj, typeof(*clk), base);
-	struct nvkm_device *device = clk->base.subdev.device;
+	struct nvkm_subdev *subdev = &clk->base.subdev;
+	struct nvkm_device *device = subdev->device;
 	u32 mast = nvkm_rd32(device, 0x00c040);
 	u32 P = 0;
 
@@ -314,7 +317,7 @@ nv50_clk_read(struct nvkm_clk *obj, enum nv_clk_src src)
 		break;
 	}
 
-	nv_debug(clk, "unknown clock source %d 0x%08x\n", src, mast);
+	nvkm_debug(subdev, "unknown clock source %d %08x\n", src, mast);
 	return -EINVAL;
 }
 

drivers/gpu/drm/nouveau/nvkm/subdev/clk/pllgt215.c

@@ -79,7 +79,7 @@ gt215_pll_calc(struct nvkm_subdev *subdev, struct nvbios_pll *info,
 	}
 
 	if (unlikely(best_err == ~0)) {
-		nv_error(subdev, "unable to find matching pll values\n");
+		nvkm_error(subdev, "unable to find matching pll values\n");
 		return -EINVAL;
 	}
 

drivers/gpu/drm/nouveau/nvkm/subdev/clk/pllnv04.c

@@ -240,6 +240,6 @@ nv04_pll_calc(struct nvkm_subdev *subdev, struct nvbios_pll *info, u32 freq,
 	}
 
 	if (!ret)
-		nv_error(subdev, "unable to compute acceptable pll values\n");
+		nvkm_error(subdev, "unable to compute acceptable pll values\n");
 	return ret;
 }