clk: sunxi: mod1 clock support
The module 1 type of clocks consist of a gate and a mux and are used on the audio blocks to mux and gate the PLL2 outputs for AC97, IIS or SPDIF. This commit adds support for them on the sunxi clock driver. Signed-off-by: NEmilio López <emilio@elopez.com.ar> Signed-off-by: NHans de Goede <hdegoede@redhat.com> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: NChen-Yu Tsai <wens@csie.org>
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drivers/clk/sunxi/clk-a10-mod1.c
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