提交 7ae52890 编写于 作者: M Michael Chan 提交者: David S. Miller

tg3: Fix RSS ring refill race condition

The RSS feature in tg3 hardware has only one rx producer ring for all
RSS rings.  NAPI vector 1 is special and handles the refilling of the
rx producer ring on behalf of all RSS rings.  There is a race condition
between these RSS NAPIs and the NAPI[1].  If NAPI[1] finishes checking
for refill and then another RSS ring empties the rx producer ring
before NAPI[1] exits NAPI, the chip will be completely out of SKBs in
the rx producer ring.

We fix this by adding a flag tp->rx_refill and rely on napi_schedule()/
napi_complete() to help synchronize it to close the race condition.

Update driver version to 3.123.
Signed-off-by: NMichael Chan <mchan@broadcom.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>
上级 5676cc7b
...@@ -89,10 +89,10 @@ static inline void _tg3_flag_clear(enum TG3_FLAGS flag, unsigned long *bits) ...@@ -89,10 +89,10 @@ static inline void _tg3_flag_clear(enum TG3_FLAGS flag, unsigned long *bits)
#define DRV_MODULE_NAME "tg3" #define DRV_MODULE_NAME "tg3"
#define TG3_MAJ_NUM 3 #define TG3_MAJ_NUM 3
#define TG3_MIN_NUM 122 #define TG3_MIN_NUM 123
#define DRV_MODULE_VERSION \ #define DRV_MODULE_VERSION \
__stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM) __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
#define DRV_MODULE_RELDATE "December 7, 2011" #define DRV_MODULE_RELDATE "March 21, 2012"
#define RESET_KIND_SHUTDOWN 0 #define RESET_KIND_SHUTDOWN 0
#define RESET_KIND_INIT 1 #define RESET_KIND_INIT 1
...@@ -5953,9 +5953,11 @@ static int tg3_rx(struct tg3_napi *tnapi, int budget) ...@@ -5953,9 +5953,11 @@ static int tg3_rx(struct tg3_napi *tnapi, int budget)
tpr->rx_std_prod_idx = std_prod_idx & tp->rx_std_ring_mask; tpr->rx_std_prod_idx = std_prod_idx & tp->rx_std_ring_mask;
tpr->rx_jmb_prod_idx = jmb_prod_idx & tp->rx_jmb_ring_mask; tpr->rx_jmb_prod_idx = jmb_prod_idx & tp->rx_jmb_ring_mask;
if (tnapi != &tp->napi[1]) if (tnapi != &tp->napi[1]) {
tp->rx_refill = true;
napi_schedule(&tp->napi[1].napi); napi_schedule(&tp->napi[1].napi);
} }
}
return received; return received;
} }
...@@ -6134,6 +6136,7 @@ static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget) ...@@ -6134,6 +6136,7 @@ static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
u32 std_prod_idx = dpr->rx_std_prod_idx; u32 std_prod_idx = dpr->rx_std_prod_idx;
u32 jmb_prod_idx = dpr->rx_jmb_prod_idx; u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
tp->rx_refill = false;
for (i = 1; i < tp->irq_cnt; i++) for (i = 1; i < tp->irq_cnt; i++)
err |= tg3_rx_prodring_xfer(tp, dpr, err |= tg3_rx_prodring_xfer(tp, dpr,
&tp->napi[i].prodring); &tp->napi[i].prodring);
...@@ -6197,9 +6200,25 @@ static int tg3_poll_msix(struct napi_struct *napi, int budget) ...@@ -6197,9 +6200,25 @@ static int tg3_poll_msix(struct napi_struct *napi, int budget)
/* check for RX/TX work to do */ /* check for RX/TX work to do */
if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons && if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons &&
*(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) { *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) {
/* This test here is not race free, but will reduce
* the number of interrupts by looping again.
*/
if (tnapi == &tp->napi[1] && tp->rx_refill)
continue;
napi_complete(napi); napi_complete(napi);
/* Reenable interrupts. */ /* Reenable interrupts. */
tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24); tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
/* This test here is synchronized by napi_schedule()
* and napi_complete() to close the race condition.
*/
if (unlikely(tnapi == &tp->napi[1] && tp->rx_refill)) {
tw32(HOSTCC_MODE, tp->coalesce_mode |
HOSTCC_MODE_ENABLE |
tnapi->coal_now);
}
mmiowb(); mmiowb();
break; break;
} }
......
...@@ -3007,6 +3007,7 @@ struct tg3 { ...@@ -3007,6 +3007,7 @@ struct tg3 {
u32 rx_std_max_post; u32 rx_std_max_post;
u32 rx_offset; u32 rx_offset;
u32 rx_pkt_map_sz; u32 rx_pkt_map_sz;
bool rx_refill;
/* begin "everything else" cacheline(s) section */ /* begin "everything else" cacheline(s) section */
......
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