提交 77ac32ad 编写于 作者: H Huang Shijie 提交者: Shawn Guo

ARM: imx6q: add clocks for gpmi-nand

Add clocks for gpmi-nand.
Signed-off-by: NHuang Shijie <shijie8@gmail.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
上级 610578a3
...@@ -147,7 +147,7 @@ enum mx6q_clks { ...@@ -147,7 +147,7 @@ enum mx6q_clks {
esai, gpt_ipg, gpt_ipg_per, gpu2d_core, gpu3d_core, hdmi_iahb, esai, gpt_ipg, gpt_ipg_per, gpu2d_core, gpu3d_core, hdmi_iahb,
hdmi_isfr, i2c1, i2c2, i2c3, iim, enfc, ipu1, ipu1_di0, ipu1_di1, ipu2, hdmi_isfr, i2c1, i2c2, i2c3, iim, enfc, ipu1, ipu1_di0, ipu1_di1, ipu2,
ipu2_di0, ldb_di0, ldb_di1, ipu2_di1, hsi_tx, mlb, mmdc_ch0_axi, ipu2_di0, ldb_di0, ldb_di1, ipu2_di1, hsi_tx, mlb, mmdc_ch0_axi,
mmdc_ch1_axi, ocram, openvg_axi, pcie_axi, pwm1, pwm2, pwm3, pwm4, mmdc_ch1_axi, ocram, openvg_axi, pcie_axi, pwm1, pwm2, pwm3, pwm4, per1_bch,
gpmi_bch_apb, gpmi_bch, gpmi_io, gpmi_apb, sata, sdma, spba, ssi1, gpmi_bch_apb, gpmi_bch, gpmi_io, gpmi_apb, sata, sdma, spba, ssi1,
ssi2, ssi3, uart_ipg, uart_serial, usboh3, usdhc1, usdhc2, usdhc3, ssi2, ssi3, uart_ipg, uart_serial, usboh3, usdhc1, usdhc2, usdhc3,
usdhc4, vdo_axi, vpu_axi, cko1, pll1_sys, pll2_bus, pll3_usb_otg, usdhc4, vdo_axi, vpu_axi, cko1, pll1_sys, pll2_bus, pll3_usb_otg,
...@@ -357,6 +357,7 @@ int __init mx6q_clocks_init(void) ...@@ -357,6 +357,7 @@ int __init mx6q_clocks_init(void)
clk[ocram] = imx_clk_gate2("ocram", "ahb", base + 0x74, 28); clk[ocram] = imx_clk_gate2("ocram", "ahb", base + 0x74, 28);
clk[openvg_axi] = imx_clk_gate2("openvg_axi", "axi", base + 0x74, 30); clk[openvg_axi] = imx_clk_gate2("openvg_axi", "axi", base + 0x74, 30);
clk[pcie_axi] = imx_clk_gate2("pcie_axi", "pcie_axi_sel", base + 0x78, 0); clk[pcie_axi] = imx_clk_gate2("pcie_axi", "pcie_axi_sel", base + 0x78, 0);
clk[per1_bch] = imx_clk_gate2("per1_bch", "usdhc3", base + 0x78, 12);
clk[pwm1] = imx_clk_gate2("pwm1", "ipg_per", base + 0x78, 16); clk[pwm1] = imx_clk_gate2("pwm1", "ipg_per", base + 0x78, 16);
clk[pwm2] = imx_clk_gate2("pwm2", "ipg_per", base + 0x78, 18); clk[pwm2] = imx_clk_gate2("pwm2", "ipg_per", base + 0x78, 18);
clk[pwm3] = imx_clk_gate2("pwm3", "ipg_per", base + 0x78, 20); clk[pwm3] = imx_clk_gate2("pwm3", "ipg_per", base + 0x78, 20);
...@@ -395,6 +396,11 @@ int __init mx6q_clocks_init(void) ...@@ -395,6 +396,11 @@ int __init mx6q_clocks_init(void)
clk_register_clkdev(clk[twd], NULL, "smp_twd"); clk_register_clkdev(clk[twd], NULL, "smp_twd");
clk_register_clkdev(clk[usboh3], NULL, "usboh3"); clk_register_clkdev(clk[usboh3], NULL, "usboh3");
clk_register_clkdev(clk[apbh_dma], NULL, "110000.dma-apbh"); clk_register_clkdev(clk[apbh_dma], NULL, "110000.dma-apbh");
clk_register_clkdev(clk[per1_bch], "per1_bch", "112000.gpmi-nand");
clk_register_clkdev(clk[gpmi_bch_apb], "gpmi_bch_apb", "112000.gpmi-nand");
clk_register_clkdev(clk[gpmi_bch], "gpmi_bch", "112000.gpmi-nand");
clk_register_clkdev(clk[gpmi_apb], "gpmi_apb", "112000.gpmi-nand");
clk_register_clkdev(clk[gpmi_io], "gpmi_io", "112000.gpmi-nand");
clk_register_clkdev(clk[uart_serial], "per", "2020000.serial"); clk_register_clkdev(clk[uart_serial], "per", "2020000.serial");
clk_register_clkdev(clk[uart_ipg], "ipg", "2020000.serial"); clk_register_clkdev(clk[uart_ipg], "ipg", "2020000.serial");
clk_register_clkdev(clk[uart_serial], "per", "21e8000.serial"); clk_register_clkdev(clk[uart_serial], "per", "21e8000.serial");
......
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