diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index d542e4db5495b0e7ae30708a4ba7e4da194391ba..7376514a162ee4454d762ec4f8cb12071b4f9c15 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -702,7 +702,7 @@ static void dcn10_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx)
 
 static void dcn10_init_hw(struct dc *dc)
 {
-	int i, opp_id;
+	int i;
 	struct abm *abm = dc->res_pool->abm;
 	struct dmcu *dmcu = dc->res_pool->dmcu;
 	struct dce_hwseq *hws = dc->hwseq;
@@ -765,13 +765,8 @@ static void dcn10_init_hw(struct dc *dc)
 		}
 	}
 
-	/* Initialize MPC tree based on HW values */
-	for (opp_id = 0; opp_id < dc->res_pool->pipe_count; opp_id++) {
-		struct output_pixel_processor *opp = dc->res_pool->opps[opp_id];
-		struct mpc_tree *mpc_tree_params = &(opp->mpc_tree_params);
-
-		dc->res_pool->mpc->funcs->init_mpcc_list_from_hw(dc->res_pool->mpc, mpc_tree_params);
-	}
+	/* Reset all MPCC muxes */
+	dc->res_pool->mpc->funcs->mpc_init(dc->res_pool->mpc);
 
 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
 		struct timing_generator *tg = dc->res_pool->timing_generators[i];
@@ -783,7 +778,7 @@ static void dcn10_init_hw(struct dc *dc)
 
 		pipe_ctx->plane_res.hubp = hubp;
 		hubp->mpcc_id = i;
-		hubp->opp_id = dc->res_pool->mpc->funcs->get_opp_id(dc->res_pool->mpc, i);
+		hubp->opp_id = 0xf;
 		hubp->power_gated = false;
 
 		if (hubp->opp_id != 0xf)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c
index d6606180b50a8a86f59cfbfe4698b5713cf6b914..1e72bd42dca44f47732c9a116185027762104eb5 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c
@@ -101,16 +101,6 @@ void mpc1_assert_idle_mpcc(struct mpc *mpc, int id)
 			1, 100000);
 }
 
-static int mpc1_get_opp_id(struct mpc *mpc, int mpcc_id)
-{
-	struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
-	unsigned int opp_id = 0xF;
-
-	REG_GET(MPCC_OPP_ID[mpcc_id], MPCC_OPP_ID, &opp_id);
-
-	return opp_id;
-}
-
 struct mpcc *mpc1_get_mpcc(struct mpc *mpc, int mpcc_id)
 {
 	struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
@@ -333,24 +323,44 @@ void mpc1_remove_mpcc(
 	}
 }
 
+static void mpc1_init_mpcc(struct mpcc *mpcc, int mpcc_inst)
+{
+	mpcc->mpcc_id = mpcc_inst;
+	mpcc->dpp_id = 0xf;
+	mpcc->mpcc_bot = NULL;
+	mpcc->blnd_cfg.overlap_only = false;
+	mpcc->blnd_cfg.global_alpha = 0xff;
+	mpcc->blnd_cfg.global_gain = 0xff;
+	mpcc->sm_cfg.enable = false;
+}
+
 /*
  * Reset the MPCC HW status by disconnecting all muxes.
  *
  * Parameters:
  * [in/out] mpc		- MPC context.
- * [in]     mpcc_id	- The MPCC physical instance to reset.
  *
  * Return:  void
  */
-void mpc1_reset_mpcc(
-	struct mpc *mpc,
-	int mpcc_id)
+void mpc1_mpc_init(struct mpc *mpc)
 {
 	struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
+	int mpcc_id;
+	int opp_id;
 
-	REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, 0xf);
-	REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, 0xf);
-	REG_SET(MPCC_OPP_ID[mpcc_id],  0, MPCC_OPP_ID,  0xf);
+	mpc10->mpcc_in_use_mask = 0;
+	for (mpcc_id = 0; mpcc_id < mpc10->num_mpcc; mpcc_id++) {
+		REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, 0xf);
+		REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, 0xf);
+		REG_SET(MPCC_OPP_ID[mpcc_id],  0, MPCC_OPP_ID,  0xf);
+
+		mpc1_init_mpcc(&(mpc->mpcc_array[mpcc_id]), mpcc_id);
+	}
+
+	for (opp_id = 0; opp_id < MAX_OPP; opp_id++) {
+		if (REG(MUX[opp_id]))
+			REG_SET(MUX[opp_id], 0, MPC_OUT_MUX, 0xf);
+	}
 }
 
 void mpc1_init_mpcc_list_from_hw(
@@ -399,27 +409,15 @@ void mpc1_init_mpcc_list_from_hw(
 	}
 }
 
-static void mpc1_init_mpcc(struct mpcc *mpcc, int mpcc_inst)
-{
-	mpcc->mpcc_id = mpcc_inst;
-	mpcc->dpp_id = 0xf;
-	mpcc->mpcc_bot = NULL;
-	mpcc->blnd_cfg.overlap_only = false;
-	mpcc->blnd_cfg.global_alpha = 0xff;
-	mpcc->blnd_cfg.global_gain = 0xff;
-	mpcc->sm_cfg.enable = false;
-}
-
 const struct mpc_funcs dcn10_mpc_funcs = {
 	.insert_plane = mpc1_insert_plane,
 	.remove_mpcc = mpc1_remove_mpcc,
-	.reset_mpcc = mpc1_reset_mpcc,
+	.mpc_init = mpc1_mpc_init,
 	.get_mpcc_for_dpp = mpc1_get_mpcc_for_dpp,
 	.wait_for_idle = mpc1_assert_idle_mpcc,
 	.assert_mpcc_idle_before_connect = mpc1_assert_mpcc_idle_before_connect,
 	.init_mpcc_list_from_hw = mpc1_init_mpcc_list_from_hw,
 	.update_blending = mpc1_update_blending,
-	.get_opp_id = mpc1_get_opp_id,
 };
 
 void dcn10_mpc_construct(struct dcn10_mpc *mpc10,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h
index aa2cd40dc022cc8308f6b2e83aea710e568d4f61..267a2995ef6e74b2e05ec492c1a8aff51c4a8bf6 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h
@@ -146,10 +146,8 @@ void mpc1_remove_mpcc(
 	struct mpc_tree *tree,
 	struct mpcc *mpcc);
 
-void mpc1_reset_mpcc(
-	struct mpc *mpc,
-	int mpcc_id);
-
+void mpc1_mpc_init(
+	struct mpc *mpc);
 
 void mpc1_assert_idle_mpcc(
 	struct mpc *mpc,
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
index 2396b15befb06e22bd6d8c6cb26e1636c94462b6..23a8d5e53a89d695136a26c3144529752f17a0f0 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
@@ -151,13 +151,10 @@ struct mpc_funcs {
 	 *
 	 * Parameters:
 	 * [in/out] mpc		- MPC context.
-	 * [in]     mpcc_id	- The MPCC physical instance to reset.
 	 *
 	 * Return:  void
 	 */
-	void (*reset_mpcc)(
-		struct mpc *mpc,
-		int mpcc_id);
+	void (*mpc_init)(struct mpc *mpc);
 
 	/*
 	 * Update the blending configuration for a specified MPCC.
@@ -186,8 +183,6 @@ struct mpc_funcs {
 		struct mpc *mpc,
 		struct mpc_tree *tree);
 
-	int (*get_opp_id)(struct mpc *mpc, int mpcc_id);
-
 };
 
 #endif