clk: tegra: Fix enabling of PLLE

When enabling the PLLE as its final step, clk_plle_enable() would
accidentally OR in the value previously written to the PLLE_SS_CTRL
register.
Signed-off-by: NThierry Reding <treding@nvidia.com>

drivers/clk/tegra/clk-pll.c

@@ -757,7 +757,7 @@ static int clk_plle_enable(struct clk_hw *hw)
 	val |= PLLE_SS_DISABLE;
 	writel(val, pll->clk_base + PLLE_SS_CTRL);
 
-	val |= pll_readl_base(pll);
+	val = pll_readl_base(pll);
 	val |= (PLL_BASE_BYPASS | PLL_BASE_ENABLE);
 	pll_writel_base(val, pll);