提交 293ef19c 编写于 作者: T Tomi Valkeinen

OMAP: DSS2: Add FEAT_DSI_REVERSE_TXCLKESC

OMAP3430 has RESETDONETXCLKESCx bits in the order following bitnumber
order for lanes 0, 1, 2: 28, 27, 26. OMAP3630 and later have them in
saner order: 24, 25, 26 (and 27, 28 for OMAP4).

This patch adds a dss_feature that can be used to differentiate between
those two orders of RESETDONETXCLKESCx bits.
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>
上级 cc5c1850
...@@ -253,7 +253,7 @@ static struct omap_dss_features omap3430_dss_features = { ...@@ -253,7 +253,7 @@ static struct omap_dss_features omap3430_dss_features = {
FEAT_LCDENABLESIGNAL | FEAT_PCKFREEENABLE | FEAT_LCDENABLESIGNAL | FEAT_PCKFREEENABLE |
FEAT_FUNCGATED | FEAT_ROWREPEATENABLE | FEAT_FUNCGATED | FEAT_ROWREPEATENABLE |
FEAT_LINEBUFFERSPLIT | FEAT_RESIZECONF | FEAT_LINEBUFFERSPLIT | FEAT_RESIZECONF |
FEAT_DSI_PLL_FREQSEL, FEAT_DSI_PLL_FREQSEL | FEAT_DSI_REVERSE_TXCLKESC,
.num_mgrs = 2, .num_mgrs = 2,
.num_ovls = 3, .num_ovls = 3,
......
...@@ -45,6 +45,7 @@ enum dss_feat_id { ...@@ -45,6 +45,7 @@ enum dss_feat_id {
FEAT_DSI_PLL_FREQSEL = 1 << 14, FEAT_DSI_PLL_FREQSEL = 1 << 14,
FEAT_DSI_DCS_CMD_CONFIG_VC = 1 << 15, FEAT_DSI_DCS_CMD_CONFIG_VC = 1 << 15,
FEAT_DSI_VC_OCP_WIDTH = 1 << 16, FEAT_DSI_VC_OCP_WIDTH = 1 << 16,
FEAT_DSI_REVERSE_TXCLKESC = 1 << 17,
}; };
/* DSS register field id */ /* DSS register field id */
......
Markdown is supported
0% .
You are about to add 0 people to the discussion. Proceed with caution.
先完成此消息的编辑!
想要评论请 注册