ocxl: Add a kernel API for other opencapi drivers

Some of the functions done by the generic driver should also be needed
by other opencapi drivers: attaching a context to an adapter,
translation fault handling, AFU interrupt allocation...

So to avoid code duplication, the driver provides a kernel API that
other drivers can use, similar to calling a in-kernel library.

It is still a bit theoretical, for lack of real hardware, and will
likely need adjustements down the road. But we used the cxlflash
driver as a guinea pig.
Signed-off-by: NFrederic Barrat <fbarrat@linux.vnet.ibm.com>
Signed-off-by: NMichael Ellerman <mpe@ellerman.id.au>

drivers/misc/ocxl/config.c

@@ -2,8 +2,8 @@
 // Copyright 2017 IBM Corp.
 #include <linux/pci.h>
 #include <asm/pnv-ocxl.h>
+#include <misc/ocxl.h>
 #include <misc/ocxl-config.h>
-#include "ocxl_internal.h"
 
 #define EXTRACT_BIT(val, bit) (!!(val & BIT(bit)))
 #define EXTRACT_BITS(val, s, e) ((val & GENMASK(e, s)) >> s)
@@ -243,6 +243,7 @@ int ocxl_config_read_function(struct pci_dev *dev, struct ocxl_fn_config *fn)
 	rc = validate_function(dev, fn);
 	return rc;
 }
+EXPORT_SYMBOL_GPL(ocxl_config_read_function);
 
 static int read_afu_info(struct pci_dev *dev, struct ocxl_fn_config *fn,
 			int offset, u32 *data)
@@ -301,6 +302,7 @@ int ocxl_config_check_afu_index(struct pci_dev *dev,
 	}
 	return 1;
 }
+EXPORT_SYMBOL_GPL(ocxl_config_check_afu_index);
 
 static int read_afu_name(struct pci_dev *dev, struct ocxl_fn_config *fn,
 			struct ocxl_afu_config *afu)
@@ -498,6 +500,7 @@ int ocxl_config_read_afu(struct pci_dev *dev, struct ocxl_fn_config *fn,
 	rc = validate_afu(dev, afu);
 	return rc;
 }
+EXPORT_SYMBOL_GPL(ocxl_config_read_afu);
 
 int ocxl_config_get_actag_info(struct pci_dev *dev, u16 *base, u16 *enabled,
 			u16 *supported)
@@ -516,6 +519,7 @@ int ocxl_config_get_actag_info(struct pci_dev *dev, u16 *base, u16 *enabled,
 	}
 	return 0;
 }
+EXPORT_SYMBOL_GPL(ocxl_config_get_actag_info);
 
 void ocxl_config_set_afu_actag(struct pci_dev *dev, int pos, int actag_base,
 			int actag_count)
@@ -528,11 +532,13 @@ void ocxl_config_set_afu_actag(struct pci_dev *dev, int pos, int actag_base,
 	val = actag_base & OCXL_DVSEC_ACTAG_MASK;
 	pci_write_config_dword(dev, pos + OCXL_DVSEC_AFU_CTRL_ACTAG_BASE, val);
 }
+EXPORT_SYMBOL_GPL(ocxl_config_set_afu_actag);
 
 int ocxl_config_get_pasid_info(struct pci_dev *dev, int *count)
 {
 	return pnv_ocxl_get_pasid_count(dev, count);
 }
+EXPORT_SYMBOL_GPL(ocxl_config_get_pasid_info);
 
 void ocxl_config_set_afu_pasid(struct pci_dev *dev, int pos, int pasid_base,
 			u32 pasid_count_log)
@@ -550,6 +556,7 @@ void ocxl_config_set_afu_pasid(struct pci_dev *dev, int pos, int pasid_base,
 	pci_write_config_dword(dev, pos + OCXL_DVSEC_AFU_CTRL_PASID_BASE,
 			val32);
 }
+EXPORT_SYMBOL_GPL(ocxl_config_set_afu_pasid);
 
 void ocxl_config_set_afu_state(struct pci_dev *dev, int pos, int enable)
 {
@@ -562,6 +569,7 @@ void ocxl_config_set_afu_state(struct pci_dev *dev, int pos, int enable)
 		val &= 0xFE;
 	pci_write_config_byte(dev, pos + OCXL_DVSEC_AFU_CTRL_ENABLE, val);
 }
+EXPORT_SYMBOL_GPL(ocxl_config_set_afu_state);
 
 int ocxl_config_set_TL(struct pci_dev *dev, int tl_dvsec)
 {
@@ -660,6 +668,7 @@ int ocxl_config_set_TL(struct pci_dev *dev, int tl_dvsec)
 	kfree(recv_rate);
 	return rc;
 }
+EXPORT_SYMBOL_GPL(ocxl_config_set_TL);
 
 int ocxl_config_terminate_pasid(struct pci_dev *dev, int afu_control, int pasid)
 {
@@ -699,6 +708,7 @@ int ocxl_config_terminate_pasid(struct pci_dev *dev, int afu_control, int pasid)
 	}
 	return 0;
 }
+EXPORT_SYMBOL_GPL(ocxl_config_terminate_pasid);
 
 void ocxl_config_set_actag(struct pci_dev *dev, int func_dvsec, u32 tag_first,
 			u32 tag_count)
@@ -710,3 +720,4 @@ void ocxl_config_set_actag(struct pci_dev *dev, int func_dvsec, u32 tag_first,
 	pci_write_config_dword(dev, func_dvsec + OCXL_DVSEC_FUNC_OFF_ACTAG,
 			val);
 }
+EXPORT_SYMBOL_GPL(ocxl_config_set_actag);

drivers/misc/ocxl/link.c

@@ -5,6 +5,7 @@
 #include <linux/mmu_context.h>
 #include <asm/copro.h>
 #include <asm/pnv-ocxl.h>
+#include <misc/ocxl.h>
 #include "ocxl_internal.h"
 
 
@@ -420,6 +421,7 @@ int ocxl_link_setup(struct pci_dev *dev, int PE_mask, void **link_handle)
 	mutex_unlock(&links_list_lock);
 	return rc;
 }
+EXPORT_SYMBOL_GPL(ocxl_link_setup);
 
 static void release_xsl(struct kref *ref)
 {
@@ -439,6 +441,7 @@ void ocxl_link_release(struct pci_dev *dev, void *link_handle)
 	kref_put(&link->ref, release_xsl);
 	mutex_unlock(&links_list_lock);
 }
+EXPORT_SYMBOL_GPL(ocxl_link_release);
 
 static u64 calculate_cfg_state(bool kernel)
 {
@@ -533,6 +536,7 @@ int ocxl_link_add_pe(void *link_handle, int pasid, u32 pidr, u32 tidr,
 	mutex_unlock(&spa->spa_lock);
 	return rc;
 }
+EXPORT_SYMBOL_GPL(ocxl_link_add_pe);
 
 int ocxl_link_remove_pe(void *link_handle, int pasid)
 {
@@ -601,6 +605,7 @@ int ocxl_link_remove_pe(void *link_handle, int pasid)
 	mutex_unlock(&spa->spa_lock);
 	return rc;
 }
+EXPORT_SYMBOL_GPL(ocxl_link_remove_pe);
 
 int ocxl_link_irq_alloc(void *link_handle, int *hw_irq, u64 *trigger_addr)
 {
@@ -621,6 +626,7 @@ int ocxl_link_irq_alloc(void *link_handle, int *hw_irq, u64 *trigger_addr)
 	*trigger_addr = addr;
 	return 0;
 }
+EXPORT_SYMBOL_GPL(ocxl_link_irq_alloc);
 
 void ocxl_link_free_irq(void *link_handle, int hw_irq)
 {
@@ -629,3 +635,4 @@ void ocxl_link_free_irq(void *link_handle, int hw_irq)
 	pnv_ocxl_free_xive_irq(hw_irq);
 	atomic_inc(&link->irq_available);
 }
+EXPORT_SYMBOL_GPL(ocxl_link_free_irq);

drivers/misc/ocxl/ocxl_internal.h

@@ -6,8 +6,8 @@
 #include <linux/pci.h>
 #include <linux/cdev.h>
 #include <linux/list.h>
+#include <misc/ocxl.h>
 
-#define OCXL_AFU_NAME_SZ      (24+1)  /* add 1 for NULL termination */
 #define MAX_IRQ_PER_LINK	2000
 #define MAX_IRQ_PER_CONTEXT	MAX_IRQ_PER_LINK
 
@@ -16,38 +16,6 @@
 
 extern struct pci_driver ocxl_pci_driver;
 
-/*
- * The following 2 structures are a fairly generic way of representing
- * the configuration data for a function and AFU, as read from the
- * configuration space.
- */
-struct ocxl_afu_config {
-	u8 idx;
-	int dvsec_afu_control_pos;
-	char name[OCXL_AFU_NAME_SZ];
-	u8 version_major;
-	u8 version_minor;
-	u8 afuc_type;
-	u8 afum_type;
-	u8 profile;
-	u8 global_mmio_bar;
-	u64 global_mmio_offset;
-	u32 global_mmio_size;
-	u8 pp_mmio_bar;
-	u64 pp_mmio_offset;
-	u32 pp_mmio_stride;
-	u8 log_mem_size;
-	u8 pasid_supported_log;
-	u16 actag_supported;
-};
-
-struct ocxl_fn_config {
-	int dvsec_tl_pos;
-	int dvsec_function_pos;
-	int dvsec_afu_info_pos;
-	s8 max_pasid_log;
-	s8 max_afu_index;
-};
 
 struct ocxl_fn {
 	struct device dev;
@@ -135,43 +103,6 @@ extern void ocxl_unregister_afu(struct ocxl_afu *afu);
 extern int ocxl_file_init(void);
 extern void ocxl_file_exit(void);
 
-extern int ocxl_config_read_function(struct pci_dev *dev,
-				struct ocxl_fn_config *fn);
-
-extern int ocxl_config_check_afu_index(struct pci_dev *dev,
-				struct ocxl_fn_config *fn, int afu_idx);
-extern int ocxl_config_read_afu(struct pci_dev *dev,
-				struct ocxl_fn_config *fn,
-				struct ocxl_afu_config *afu,
-				u8 afu_idx);
-extern int ocxl_config_get_pasid_info(struct pci_dev *dev, int *count);
-extern void ocxl_config_set_afu_pasid(struct pci_dev *dev,
-				int afu_control,
-				int pasid_base, u32 pasid_count_log);
-extern int ocxl_config_get_actag_info(struct pci_dev *dev,
-				u16 *base, u16 *enabled, u16 *supported);
-extern void ocxl_config_set_actag(struct pci_dev *dev, int func_dvsec,
-				u32 tag_first, u32 tag_count);
-extern void ocxl_config_set_afu_actag(struct pci_dev *dev, int afu_control,
-				int actag_base, int actag_count);
-extern void ocxl_config_set_afu_state(struct pci_dev *dev, int afu_control,
-				int enable);
-extern int ocxl_config_set_TL(struct pci_dev *dev, int tl_dvsec);
-extern int ocxl_config_terminate_pasid(struct pci_dev *dev, int afu_control,
-				int pasid);
-
-extern int ocxl_link_setup(struct pci_dev *dev, int PE_mask,
-			void **link_handle);
-extern void ocxl_link_release(struct pci_dev *dev, void *link_handle);
-extern int ocxl_link_add_pe(void *link_handle, int pasid, u32 pidr, u32 tidr,
-		u64 amr, struct mm_struct *mm,
-		void (*xsl_err_cb)(void *data, u64 addr, u64 dsisr),
-		void *xsl_err_data);
-extern int ocxl_link_remove_pe(void *link_handle, int pasid);
-extern int ocxl_link_irq_alloc(void *link_handle, int *hw_irq,
-			u64 *addr);
-extern void ocxl_link_free_irq(void *link_handle, int hw_irq);
-
 extern int ocxl_pasid_afu_alloc(struct ocxl_fn *fn, u32 size);
 extern void ocxl_pasid_afu_free(struct ocxl_fn *fn, u32 start, u32 size);
 extern int ocxl_actag_afu_alloc(struct ocxl_fn *fn, u32 size);

include/misc/ocxl.h

+// SPDX-License-Identifier: GPL-2.0+
+// Copyright 2017 IBM Corp.
+#ifndef _MISC_OCXL_H_
+#define _MISC_OCXL_H_
+
+#include <linux/pci.h>
+
+/*
+ * Opencapi drivers all need some common facilities, like parsing the
+ * device configuration space, adding a Process Element to the Shared
+ * Process Area, etc...
+ *
+ * The ocxl module provides a kernel API, to allow other drivers to
+ * reuse common code. A bit like a in-kernel library.
+ */
+
+#define OCXL_AFU_NAME_SZ      (24+1)  /* add 1 for NULL termination */
+
+/*
+ * The following 2 structures are a fairly generic way of representing
+ * the configuration data for a function and AFU, as read from the
+ * configuration space.
+ */
+struct ocxl_afu_config {
+	u8 idx;
+	int dvsec_afu_control_pos; /* offset of AFU control DVSEC */
+	char name[OCXL_AFU_NAME_SZ];
+	u8 version_major;
+	u8 version_minor;
+	u8 afuc_type;
+	u8 afum_type;
+	u8 profile;
+	u8 global_mmio_bar;     /* global MMIO area */
+	u64 global_mmio_offset;
+	u32 global_mmio_size;
+	u8 pp_mmio_bar;         /* per-process MMIO area */
+	u64 pp_mmio_offset;
+	u32 pp_mmio_stride;
+	u8 log_mem_size;
+	u8 pasid_supported_log;
+	u16 actag_supported;
+};
+
+struct ocxl_fn_config {
+	int dvsec_tl_pos;       /* offset of the Transaction Layer DVSEC */
+	int dvsec_function_pos; /* offset of the Function DVSEC */
+	int dvsec_afu_info_pos; /* offset of the AFU information DVSEC */
+	s8 max_pasid_log;
+	s8 max_afu_index;
+};
+
+/*
+ * Read the configuration space of a function and fill in a
+ * ocxl_fn_config structure with all the function details
+ */
+extern int ocxl_config_read_function(struct pci_dev *dev,
+				struct ocxl_fn_config *fn);
+
+/*
+ * Check if an AFU index is valid for the given function.
+ *
+ * AFU indexes can be sparse, so a driver should check all indexes up
+ * to the maximum found in the function description
+ */
+extern int ocxl_config_check_afu_index(struct pci_dev *dev,
+				struct ocxl_fn_config *fn, int afu_idx);
+
+/*
+ * Read the configuration space of a function for the AFU specified by
+ * the index 'afu_idx'. Fills in a ocxl_afu_config structure
+ */
+extern int ocxl_config_read_afu(struct pci_dev *dev,
+				struct ocxl_fn_config *fn,
+				struct ocxl_afu_config *afu,
+				u8 afu_idx);
+
+/*
+ * Get the max PASID value that can be used by the function
+ */
+extern int ocxl_config_get_pasid_info(struct pci_dev *dev, int *count);
+
+/*
+ * Tell an AFU, by writing in the configuration space, the PASIDs that
+ * it can use. Range starts at 'pasid_base' and its size is a multiple
+ * of 2
+ *
+ * 'afu_control_offset' is the offset of the AFU control DVSEC which
+ * can be found in the function configuration
+ */
+extern void ocxl_config_set_afu_pasid(struct pci_dev *dev,
+				int afu_control_offset,
+				int pasid_base, u32 pasid_count_log);
+
+/*
+ * Get the actag configuration for the function:
+ * 'base' is the first actag value that can be used.
+ * 'enabled' it the number of actags available, starting from base.
+ * 'supported' is the total number of actags desired by all the AFUs
+ *             of the function.
+ */
+extern int ocxl_config_get_actag_info(struct pci_dev *dev,
+				u16 *base, u16 *enabled, u16 *supported);
+
+/*
+ * Tell a function, by writing in the configuration space, the actags
+ * it can use.
+ *
+ * 'func_offset' is the offset of the Function DVSEC that can found in
+ * the function configuration
+ */
+extern void ocxl_config_set_actag(struct pci_dev *dev, int func_offset,
+				u32 actag_base, u32 actag_count);
+
+/*
+ * Tell an AFU, by writing in the configuration space, the actags it
+ * can use.
+ *
+ * 'afu_control_offset' is the offset of the AFU control DVSEC for the
+ * desired AFU. It can be found in the AFU configuration
+ */
+extern void ocxl_config_set_afu_actag(struct pci_dev *dev,
+				int afu_control_offset,
+				int actag_base, int actag_count);
+
+/*
+ * Enable/disable an AFU, by writing in the configuration space.
+ *
+ * 'afu_control_offset' is the offset of the AFU control DVSEC for the
+ * desired AFU. It can be found in the AFU configuration
+ */
+extern void ocxl_config_set_afu_state(struct pci_dev *dev,
+				int afu_control_offset, int enable);
+
+/*
+ * Set the Transaction Layer configuration in the configuration space.
+ * Only needed for function 0.
+ *
+ * It queries the host TL capabilities, find some common ground
+ * between the host and device, and set the Transaction Layer on both
+ * accordingly.
+ */
+extern int ocxl_config_set_TL(struct pci_dev *dev, int tl_dvsec);
+
+/*
+ * Request an AFU to terminate a PASID.
+ * Will return once the AFU has acked the request, or an error in case
+ * of timeout.
+ *
+ * The hardware can only terminate one PASID at a time, so caller must
+ * guarantee some kind of serialization.
+ *
+ * 'afu_control_offset' is the offset of the AFU control DVSEC for the
+ * desired AFU. It can be found in the AFU configuration
+ */
+extern int ocxl_config_terminate_pasid(struct pci_dev *dev,
+				int afu_control_offset, int pasid);
+
+/*
+ * Set up the opencapi link for the function.
+ *
+ * When called for the first time for a link, it sets up the Shared
+ * Process Area for the link and the interrupt handler to process
+ * translation faults.
+ *
+ * Returns a 'link handle' that should be used for further calls for
+ * the link
+ */
+extern int ocxl_link_setup(struct pci_dev *dev, int PE_mask,
+			void **link_handle);
+
+/*
+ * Remove the association between the function and its link.
+ */
+extern void ocxl_link_release(struct pci_dev *dev, void *link_handle);
+
+/*
+ * Add a Process Element to the Shared Process Area for a link.
+ * The process is defined by its PASID, pid, tid and its mm_struct.
+ *
+ * 'xsl_err_cb' is an optional callback if the driver wants to be
+ * notified when the translation fault interrupt handler detects an
+ * address error.
+ * 'xsl_err_data' is an argument passed to the above callback, if
+ * defined
+ */
+extern int ocxl_link_add_pe(void *link_handle, int pasid, u32 pidr, u32 tidr,
+		u64 amr, struct mm_struct *mm,
+		void (*xsl_err_cb)(void *data, u64 addr, u64 dsisr),
+		void *xsl_err_data);
+
+/*
+ * Remove a Process Element from the Shared Process Area for a link
+ */
+extern int ocxl_link_remove_pe(void *link_handle, int pasid);
+
+/*
+ * Allocate an AFU interrupt associated to the link.
+ *
+ * 'hw_irq' is the hardware interrupt number
+ * 'obj_handle' is the 64-bit object handle to be passed to the AFU to
+ * trigger the interrupt.
+ * On P9, 'obj_handle' is an address, which, if written, triggers the
+ * interrupt. It is an MMIO address which needs to be remapped (one
+ * page).
+ */
+extern int ocxl_link_irq_alloc(void *link_handle, int *hw_irq,
+			u64 *obj_handle);
+
+/*
+ * Free a previously allocated AFU interrupt
+ */
+extern void ocxl_link_free_irq(void *link_handle, int hw_irq);
+
+#endif /* _MISC_OCXL_H_ */