提交 2371dd88 编写于 作者: M Maxime Ripard

clk: sunxi: Add A10s gates

The Allwinner A10s has a slightly different gates set than the A10 and
A13, so add these gates to the clk driver.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Tested-by: NEmilio López <emilio@elopez.com.ar>
Reviewed-by: NEmilio López <emilio@elopez.com.ar>
上级 bddbd134
......@@ -14,13 +14,16 @@ Required properties:
"allwinner,sun4i-ahb-clk" - for the AHB clock
"allwinner,sun4i-ahb-gates-clk" - for the AHB gates on A10
"allwinner,sun5i-a13-ahb-gates-clk" - for the AHB gates on A13
"allwinner,sun5i-a10s-ahb-gates-clk" - for the AHB gates on A10s
"allwinner,sun4i-apb0-clk" - for the APB0 clock
"allwinner,sun4i-apb0-gates-clk" - for the APB0 gates on A10
"allwinner,sun5i-a13-apb0-gates-clk" - for the APB0 gates on A13
"allwinner,sun5i-a10s-apb0-gates-clk" - for the APB0 gates on A10s
"allwinner,sun4i-apb1-clk" - for the APB1 clock
"allwinner,sun4i-apb1-mux-clk" - for the APB1 clock muxing
"allwinner,sun4i-apb1-gates-clk" - for the APB1 gates on A10
"allwinner,sun5i-a13-apb1-gates-clk" - for the APB1 gates on A13
"allwinner,sun5i-a10s-apb1-gates-clk" - for the APB1 gates on A10s
Required properties for all clocks:
- reg : shall be the control register address for the clock.
......
Gate clock outputs
------------------
* AXI gates ("allwinner,sun4i-axi-gates-clk")
DRAM 0
* AHB gates ("allwinner,sun5i-a10s-ahb-gates-clk")
USB0 0
EHCI0 1
OHCI0 2
SS 5
DMA 6
BIST 7
MMC0 8
MMC1 9
MMC2 10
NAND 13
SDRAM 14
EMAC 17
TS 18
SPI0 20
SPI1 21
SPI2 22
GPS 26
HSTIMER 28
VE 32
TVE 34
LCD 36
CSI 40
HDMI 43
DE_BE 44
DE_FE 46
IEP 51
MALI400 52
* APB0 gates ("allwinner,sun5i-a10s-apb0-gates-clk")
CODEC 0
IIS 3
PIO 5
IR 6
KEYPAD 10
* APB1 gates ("allwinner,sun5i-a10s-apb1-gates-clk")
I2C0 0
I2C1 1
I2C2 2
UART0 16
UART1 17
UART2 18
UART3 19
Notation:
[*]: The datasheet didn't mention these, but they are present on AW code
[**]: The datasheet had this marked as "NC" but they are used on AW code
......@@ -342,6 +342,10 @@ static const __initconst struct gates_data sun4i_ahb_gates_data = {
.mask = {0x7F77FFF, 0x14FB3F},
};
static const __initconst struct gates_data sun5i_a10s_ahb_gates_data = {
.mask = {0x147667e7, 0x185915},
};
static const __initconst struct gates_data sun5i_a13_ahb_gates_data = {
.mask = {0x107067e7, 0x185111},
};
......@@ -350,6 +354,10 @@ static const __initconst struct gates_data sun4i_apb0_gates_data = {
.mask = {0x4EF},
};
static const __initconst struct gates_data sun5i_a10s_apb0_gates_data = {
.mask = {0x469},
};
static const __initconst struct gates_data sun5i_a13_apb0_gates_data = {
.mask = {0x61},
};
......@@ -358,6 +366,10 @@ static const __initconst struct gates_data sun4i_apb1_gates_data = {
.mask = {0xFF00F7},
};
static const __initconst struct gates_data sun5i_a10s_apb1_gates_data = {
.mask = {0xf0007},
};
static const __initconst struct gates_data sun5i_a13_apb1_gates_data = {
.mask = {0xa0007},
};
......@@ -443,10 +455,13 @@ static const __initconst struct of_device_id clk_mux_match[] = {
static const __initconst struct of_device_id clk_gates_match[] = {
{.compatible = "allwinner,sun4i-axi-gates-clk", .data = &sun4i_axi_gates_data,},
{.compatible = "allwinner,sun4i-ahb-gates-clk", .data = &sun4i_ahb_gates_data,},
{.compatible = "allwinner,sun5i-a10s-ahb-gates-clk", .data = &sun5i_a10s_ahb_gates_data,},
{.compatible = "allwinner,sun5i-a13-ahb-gates-clk", .data = &sun5i_a13_ahb_gates_data,},
{.compatible = "allwinner,sun4i-apb0-gates-clk", .data = &sun4i_apb0_gates_data,},
{.compatible = "allwinner,sun5i-a10s-apb0-gates-clk", .data = &sun5i_a10s_apb0_gates_data,},
{.compatible = "allwinner,sun5i-a13-apb0-gates-clk", .data = &sun5i_a13_apb0_gates_data,},
{.compatible = "allwinner,sun4i-apb1-gates-clk", .data = &sun4i_apb1_gates_data,},
{.compatible = "allwinner,sun5i-a10s-apb1-gates-clk", .data = &sun5i_a10s_apb1_gates_data,},
{.compatible = "allwinner,sun5i-a13-apb1-gates-clk", .data = &sun5i_a13_apb1_gates_data,},
{}
};
......
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