diff --git a/drivers/gpu/drm/omapdrm/dss/dsi.c b/drivers/gpu/drm/omapdrm/dss/dsi.c
index 08751c9cc973a43505ca5ca11057ce9ce8895206..0ef01a6dd6be32a4658dfdc0cb5f240ec731e875 100644
--- a/drivers/gpu/drm/omapdrm/dss/dsi.c
+++ b/drivers/gpu/drm/omapdrm/dss/dsi.c
@@ -3982,7 +3982,7 @@ static void dsi_update_screen_dispc(struct platform_device *dsidev)
 
 	dss_mgr_set_timings(mgr->id, &dsi->timings);
 
-	dss_mgr_start_update(mgr);
+	dss_mgr_start_update(mgr->id);
 
 	if (dsi->te_enabled) {
 		/* disable LP_RX_TO, so that we can receive TE.  Time to wait
diff --git a/drivers/gpu/drm/omapdrm/dss/omapdss.h b/drivers/gpu/drm/omapdrm/dss/omapdss.h
index 25c3449111b29d82843f4b981eca1c58aaee7d0f..4d72909313e4b18b105958f1b2040ee8d9c402f7 100644
--- a/drivers/gpu/drm/omapdrm/dss/omapdss.h
+++ b/drivers/gpu/drm/omapdrm/dss/omapdss.h
@@ -92,7 +92,7 @@ void dss_mgr_set_lcd_config(enum omap_channel channel,
 		const struct dss_lcd_mgr_config *config);
 int dss_mgr_enable(enum omap_channel channel);
 void dss_mgr_disable(enum omap_channel channel);
-void dss_mgr_start_update(struct omap_overlay_manager *mgr);
+void dss_mgr_start_update(enum omap_channel channel);
 int dss_mgr_register_framedone_handler(struct omap_overlay_manager *mgr,
 		void (*handler)(void *), void *data);
 void dss_mgr_unregister_framedone_handler(struct omap_overlay_manager *mgr,
diff --git a/drivers/gpu/drm/omapdrm/dss/output.c b/drivers/gpu/drm/omapdrm/dss/output.c
index c6238746efe172c17214a49073729578459a34cb..39a0d7f59a808964d57b23026d1b30693763baa9 100644
--- a/drivers/gpu/drm/omapdrm/dss/output.c
+++ b/drivers/gpu/drm/omapdrm/dss/output.c
@@ -228,9 +228,9 @@ void dss_mgr_disable(enum omap_channel channel)
 }
 EXPORT_SYMBOL(dss_mgr_disable);
 
-void dss_mgr_start_update(struct omap_overlay_manager *mgr)
+void dss_mgr_start_update(enum omap_channel channel)
 {
-	dss_mgr_ops->start_update(mgr->id);
+	dss_mgr_ops->start_update(channel);
 }
 EXPORT_SYMBOL(dss_mgr_start_update);