提交 1bb38e8b 编写于 作者: M Maya Erez 提交者: Kalle Valo

wil6210: fix eDMA RX chaining

HW requires Rx buffers to be 4 bytes aligned. Modify the driver to
meet this requirement.
Enable OFU rdy valid bug fix, to prevent hang in oful34_rx while
there is back-pressure from host during RX.
Signed-off-by: NMaya Erez <merez@codeaurora.org>
Signed-off-by: NKalle Valo <kvalo@codeaurora.org>
上级 d554edcd
...@@ -1614,6 +1614,13 @@ int wil_reset(struct wil6210_priv *wil, bool load_fw) ...@@ -1614,6 +1614,13 @@ int wil_reset(struct wil6210_priv *wil, bool load_fw)
wil->txrx_ops.configure_interrupt_moderation(wil); wil->txrx_ops.configure_interrupt_moderation(wil);
/* Enable OFU rdy valid bug fix, to prevent hang in oful34_rx
* while there is back-pressure from Host during RX
*/
if (wil->hw_version >= HW_VER_TALYN_MB)
wil_s(wil, RGF_DMA_MISC_CTL,
BIT_OFUL34_RDY_VALID_BUG_FIX_EN);
rc = wil_restore_vifs(wil); rc = wil_restore_vifs(wil);
if (rc) { if (rc) {
wil_err(wil, "failed to restore vifs, rc %d\n", rc); wil_err(wil, "failed to restore vifs, rc %d\n", rc);
......
...@@ -27,6 +27,8 @@ ...@@ -27,6 +27,8 @@
#include "trace.h" #include "trace.h"
#define WIL_EDMA_MAX_DATA_OFFSET (2) #define WIL_EDMA_MAX_DATA_OFFSET (2)
/* RX buffer size must be aligned to 4 bytes */
#define WIL_EDMA_RX_BUF_LEN_DEFAULT (2048)
static void wil_tx_desc_unmap_edma(struct device *dev, static void wil_tx_desc_unmap_edma(struct device *dev,
union wil_tx_desc *desc, union wil_tx_desc *desc,
...@@ -158,8 +160,7 @@ static int wil_ring_alloc_skb_edma(struct wil6210_priv *wil, ...@@ -158,8 +160,7 @@ static int wil_ring_alloc_skb_edma(struct wil6210_priv *wil,
struct wil_ring *ring, u32 i) struct wil_ring *ring, u32 i)
{ {
struct device *dev = wil_to_dev(wil); struct device *dev = wil_to_dev(wil);
unsigned int sz = wil->rx_buf_len + ETH_HLEN + unsigned int sz = ALIGN(wil->rx_buf_len, 4);
WIL_EDMA_MAX_DATA_OFFSET;
dma_addr_t pa; dma_addr_t pa;
u16 buff_id; u16 buff_id;
struct list_head *active = &wil->rx_buff_mgmt.active; struct list_head *active = &wil->rx_buff_mgmt.active;
...@@ -600,7 +601,7 @@ static bool wil_is_rx_idle_edma(struct wil6210_priv *wil) ...@@ -600,7 +601,7 @@ static bool wil_is_rx_idle_edma(struct wil6210_priv *wil)
static void wil_rx_buf_len_init_edma(struct wil6210_priv *wil) static void wil_rx_buf_len_init_edma(struct wil6210_priv *wil)
{ {
wil->rx_buf_len = rx_large_buf ? wil->rx_buf_len = rx_large_buf ?
WIL_MAX_ETH_MTU : TXRX_BUF_LEN_DEFAULT - WIL_MAX_MPDU_OVERHEAD; WIL_MAX_ETH_MTU : WIL_EDMA_RX_BUF_LEN_DEFAULT;
} }
static int wil_rx_init_edma(struct wil6210_priv *wil, u16 desc_ring_size) static int wil_rx_init_edma(struct wil6210_priv *wil, u16 desc_ring_size)
...@@ -633,8 +634,7 @@ static int wil_rx_init_edma(struct wil6210_priv *wil, u16 desc_ring_size) ...@@ -633,8 +634,7 @@ static int wil_rx_init_edma(struct wil6210_priv *wil, u16 desc_ring_size)
wil_rx_buf_len_init_edma(wil); wil_rx_buf_len_init_edma(wil);
max_rx_pl_per_desc = wil->rx_buf_len + ETH_HLEN + max_rx_pl_per_desc = ALIGN(wil->rx_buf_len, 4);
WIL_EDMA_MAX_DATA_OFFSET;
/* Use debugfs dbg_num_rx_srings if set, reserve one sring for TX */ /* Use debugfs dbg_num_rx_srings if set, reserve one sring for TX */
if (wil->num_rx_status_rings > WIL6210_MAX_STATUS_RINGS - 1) if (wil->num_rx_status_rings > WIL6210_MAX_STATUS_RINGS - 1)
...@@ -869,8 +869,7 @@ static struct sk_buff *wil_sring_reap_rx_edma(struct wil6210_priv *wil, ...@@ -869,8 +869,7 @@ static struct sk_buff *wil_sring_reap_rx_edma(struct wil6210_priv *wil,
struct sk_buff *skb; struct sk_buff *skb;
dma_addr_t pa; dma_addr_t pa;
struct wil_ring_rx_data *rxdata = &sring->rx_data; struct wil_ring_rx_data *rxdata = &sring->rx_data;
unsigned int sz = wil->rx_buf_len + ETH_HLEN + unsigned int sz = ALIGN(wil->rx_buf_len, 4);
WIL_EDMA_MAX_DATA_OFFSET;
struct wil_net_stats *stats = NULL; struct wil_net_stats *stats = NULL;
u16 dmalen; u16 dmalen;
int cid; int cid;
......
...@@ -302,6 +302,8 @@ struct RGF_ICR { ...@@ -302,6 +302,8 @@ struct RGF_ICR {
#define BIT_DMA_ITR_RX_IDL_CNT_CTL_FOREVER BIT(2) #define BIT_DMA_ITR_RX_IDL_CNT_CTL_FOREVER BIT(2)
#define BIT_DMA_ITR_RX_IDL_CNT_CTL_CLR BIT(3) #define BIT_DMA_ITR_RX_IDL_CNT_CTL_CLR BIT(3)
#define BIT_DMA_ITR_RX_IDL_CNT_CTL_REACHED_TRESH BIT(4) #define BIT_DMA_ITR_RX_IDL_CNT_CTL_REACHED_TRESH BIT(4)
#define RGF_DMA_MISC_CTL (0x881d6c)
#define BIT_OFUL34_RDY_VALID_BUG_FIX_EN BIT(7)
#define RGF_DMA_PSEUDO_CAUSE (0x881c68) #define RGF_DMA_PSEUDO_CAUSE (0x881c68)
#define RGF_DMA_PSEUDO_CAUSE_MASK_SW (0x881c6c) #define RGF_DMA_PSEUDO_CAUSE_MASK_SW (0x881c6c)
......
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