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提交 17de50b7 编写于 作者: E Eilon Greenstein 提交者： David S. Miller
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bnx2x: Change GPIO for any port 

Change GPIO for any port
The set GPIO function should receive the port index to allow changing
the GPIO of another port. This is needed for the common init phase (one
the first driver is loaded for the chip)
Signed-off-by: NEilon Greenstein <eilong@broadcom.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>
上级 8c99e7b0
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Showing with 51 addition and 43 deletion
drivers/net/bnx2x.h
浏览文件 @ 17de50b7
...@@ -924,7 +924,7 @@ struct bnx2x { ...@@ -924,7 +924,7 @@ struct bnx2x {
void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32); void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32);
void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr, void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
u32 len32); u32 len32);
int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode); int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms, static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms,
int wait) int wait)
......
drivers/net/bnx2x_link.c
浏览文件 @ 17de50b7
...@@ -1844,13 +1844,13 @@ static u8 bnx2x_emac_program(struct link_params *params, ...@@ -1844,13 +1844,13 @@ static u8 bnx2x_emac_program(struct link_params *params,
/*****************************************************************************/ /*****************************************************************************/
/* External Phy section */ /* External Phy section */
/*****************************************************************************/ /*****************************************************************************/
static void bnx2x_hw_reset(struct bnx2x *bp) static void bnx2x_hw_reset(struct bnx2x *bp, u8 port)
{ {
bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
MISC_REGISTERS_GPIO_OUTPUT_LOW); MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
msleep(1); msleep(1);
bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
MISC_REGISTERS_GPIO_OUTPUT_HIGH); MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
} }
static void bnx2x_ext_phy_reset(struct link_params *params, static void bnx2x_ext_phy_reset(struct link_params *params,
...@@ -1879,10 +1879,11 @@ static void bnx2x_ext_phy_reset(struct link_params *params, ...@@ -1879,10 +1879,11 @@ static void bnx2x_ext_phy_reset(struct link_params *params,
/* Restore normal power mode*/ /* Restore normal power mode*/
bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
MISC_REGISTERS_GPIO_OUTPUT_HIGH); MISC_REGISTERS_GPIO_OUTPUT_HIGH,
params->port);
/* HW reset */ /* HW reset */
bnx2x_hw_reset(bp); bnx2x_hw_reset(bp, params->port);
bnx2x_cl45_write(bp, params->port, bnx2x_cl45_write(bp, params->port,
ext_phy_type, ext_phy_type,
...@@ -1894,7 +1895,8 @@ static void bnx2x_ext_phy_reset(struct link_params *params, ...@@ -1894,7 +1895,8 @@ static void bnx2x_ext_phy_reset(struct link_params *params,
/* Unset Low Power Mode and SW reset */ /* Unset Low Power Mode and SW reset */
/* Restore normal power mode*/ /* Restore normal power mode*/
bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
MISC_REGISTERS_GPIO_OUTPUT_HIGH); MISC_REGISTERS_GPIO_OUTPUT_HIGH,
params->port);
DP(NETIF_MSG_LINK, "XGXS 8072\n"); DP(NETIF_MSG_LINK, "XGXS 8072\n");
bnx2x_cl45_write(bp, params->port, bnx2x_cl45_write(bp, params->port,
...@@ -1912,19 +1914,14 @@ static void bnx2x_ext_phy_reset(struct link_params *params, ...@@ -1912,19 +1914,14 @@ static void bnx2x_ext_phy_reset(struct link_params *params,
/* Restore normal power mode*/ /* Restore normal power mode*/
bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
MISC_REGISTERS_GPIO_OUTPUT_HIGH); MISC_REGISTERS_GPIO_OUTPUT_HIGH,
params->port);
bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
MISC_REGISTERS_GPIO_OUTPUT_HIGH); MISC_REGISTERS_GPIO_OUTPUT_HIGH,
params->port);
DP(NETIF_MSG_LINK, "XGXS 8073\n"); DP(NETIF_MSG_LINK, "XGXS 8073\n");
bnx2x_cl45_write(bp,
params->port,
ext_phy_type,
ext_phy_addr,
MDIO_PMA_DEVAD,
MDIO_PMA_REG_CTRL,
1<<15);
} }
break; break;
...@@ -1933,10 +1930,11 @@ static void bnx2x_ext_phy_reset(struct link_params *params, ...@@ -1933,10 +1930,11 @@ static void bnx2x_ext_phy_reset(struct link_params *params,
/* Restore normal power mode*/ /* Restore normal power mode*/
bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
MISC_REGISTERS_GPIO_OUTPUT_HIGH); MISC_REGISTERS_GPIO_OUTPUT_HIGH,
params->port);
/* HW reset */ /* HW reset */
bnx2x_hw_reset(bp); bnx2x_hw_reset(bp, params->port);
break; break;
...@@ -1959,7 +1957,7 @@ static void bnx2x_ext_phy_reset(struct link_params *params, ...@@ -1959,7 +1957,7 @@ static void bnx2x_ext_phy_reset(struct link_params *params,
case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482: case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482:
DP(NETIF_MSG_LINK, "SerDes 5482\n"); DP(NETIF_MSG_LINK, "SerDes 5482\n");
bnx2x_hw_reset(bp); bnx2x_hw_reset(bp, params->port);
break; break;
default: default:
...@@ -3287,11 +3285,13 @@ static void bnx2x_turn_on_ef(struct bnx2x *bp, u8 port, u8 ext_phy_addr, ...@@ -3287,11 +3285,13 @@ static void bnx2x_turn_on_ef(struct bnx2x *bp, u8 port, u8 ext_phy_addr,
/* take ext phy out of reset */ /* take ext phy out of reset */
bnx2x_set_gpio(bp, bnx2x_set_gpio(bp,
MISC_REGISTERS_GPIO_2, MISC_REGISTERS_GPIO_2,
MISC_REGISTERS_GPIO_HIGH); MISC_REGISTERS_GPIO_HIGH,
port);
bnx2x_set_gpio(bp, bnx2x_set_gpio(bp,
MISC_REGISTERS_GPIO_1, MISC_REGISTERS_GPIO_1,
MISC_REGISTERS_GPIO_HIGH); MISC_REGISTERS_GPIO_HIGH,
port);
/* wait for 5ms */ /* wait for 5ms */
msleep(5); msleep(5);
...@@ -3311,13 +3311,17 @@ static void bnx2x_turn_on_ef(struct bnx2x *bp, u8 port, u8 ext_phy_addr, ...@@ -3311,13 +3311,17 @@ static void bnx2x_turn_on_ef(struct bnx2x *bp, u8 port, u8 ext_phy_addr,
} }
} }
static void bnx2x_turn_off_sf(struct bnx2x *bp) static void bnx2x_turn_off_sf(struct bnx2x *bp, u8 port)
{ {
/* put sf to reset */ /* put sf to reset */
bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, MISC_REGISTERS_GPIO_LOW); bnx2x_set_gpio(bp,
MISC_REGISTERS_GPIO_1,
MISC_REGISTERS_GPIO_LOW,
port);
bnx2x_set_gpio(bp, bnx2x_set_gpio(bp,
MISC_REGISTERS_GPIO_2, MISC_REGISTERS_GPIO_2,
MISC_REGISTERS_GPIO_LOW); MISC_REGISTERS_GPIO_LOW,
port);
} }
u8 bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 driver_loaded, u8 bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 driver_loaded,
...@@ -3371,7 +3375,7 @@ u8 bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 driver_loaded, ...@@ -3371,7 +3375,7 @@ u8 bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 driver_loaded,
version[4] = '\0'; version[4] = '\0';
if (!driver_loaded) if (!driver_loaded)
bnx2x_turn_off_sf(bp); bnx2x_turn_off_sf(bp, params->port);
break; break;
case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072: case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073: case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
...@@ -4013,10 +4017,12 @@ u8 bnx2x_link_reset(struct link_params *params, struct link_vars *vars) ...@@ -4013,10 +4017,12 @@ u8 bnx2x_link_reset(struct link_params *params, struct link_vars *vars)
/* HW reset */ /* HW reset */
bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
MISC_REGISTERS_GPIO_OUTPUT_LOW); MISC_REGISTERS_GPIO_OUTPUT_LOW,
port);
bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
MISC_REGISTERS_GPIO_OUTPUT_LOW); MISC_REGISTERS_GPIO_OUTPUT_LOW,
port);
DP(NETIF_MSG_LINK, "reset external PHY\n"); DP(NETIF_MSG_LINK, "reset external PHY\n");
} else if (ext_phy_type == } else if (ext_phy_type ==
...@@ -4025,7 +4031,8 @@ u8 bnx2x_link_reset(struct link_params *params, struct link_vars *vars) ...@@ -4025,7 +4031,8 @@ u8 bnx2x_link_reset(struct link_params *params, struct link_vars *vars)
"low power mode\n", "low power mode\n",
port); port);
bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
MISC_REGISTERS_GPIO_OUTPUT_LOW); MISC_REGISTERS_GPIO_OUTPUT_LOW,
port);
} }
} }
/* reset the SerDes/XGXS */ /* reset the SerDes/XGXS */
...@@ -4271,7 +4278,7 @@ static u8 bnx2x_sfx7101_flash_download(struct bnx2x *bp, u8 port, ...@@ -4271,7 +4278,7 @@ static u8 bnx2x_sfx7101_flash_download(struct bnx2x *bp, u8 port,
and issuing a reset.*/ and issuing a reset.*/
bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0, bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
MISC_REGISTERS_GPIO_HIGH); MISC_REGISTERS_GPIO_HIGH, port);
bnx2x_sfx7101_sp_sw_reset(bp, port, ext_phy_addr); bnx2x_sfx7101_sp_sw_reset(bp, port, ext_phy_addr);
...@@ -4503,7 +4510,8 @@ static u8 bnx2x_sfx7101_flash_download(struct bnx2x *bp, u8 port, ...@@ -4503,7 +4510,8 @@ static u8 bnx2x_sfx7101_flash_download(struct bnx2x *bp, u8 port,
} }
/* DSP Remove Download Mode */ /* DSP Remove Download Mode */
bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0, MISC_REGISTERS_GPIO_LOW); bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
MISC_REGISTERS_GPIO_LOW, port);
bnx2x_sfx7101_sp_sw_reset(bp, port, ext_phy_addr); bnx2x_sfx7101_sp_sw_reset(bp, port, ext_phy_addr);
...@@ -4511,7 +4519,7 @@ static u8 bnx2x_sfx7101_flash_download(struct bnx2x *bp, u8 port, ...@@ -4511,7 +4519,7 @@ static u8 bnx2x_sfx7101_flash_download(struct bnx2x *bp, u8 port,
for (cnt = 0; cnt < 100; cnt++) for (cnt = 0; cnt < 100; cnt++)
msleep(5); msleep(5);
bnx2x_hw_reset(bp); bnx2x_hw_reset(bp, port);
for (cnt = 0; cnt < 100; cnt++) for (cnt = 0; cnt < 100; cnt++)
msleep(5); msleep(5);
...@@ -4586,7 +4594,7 @@ u8 bnx2x_flash_download(struct bnx2x *bp, u8 port, u32 ext_phy_config, ...@@ -4586,7 +4594,7 @@ u8 bnx2x_flash_download(struct bnx2x *bp, u8 port, u32 ext_phy_config,
rc = bnx2x_sfx7101_flash_download(bp, port, ext_phy_addr, rc = bnx2x_sfx7101_flash_download(bp, port, ext_phy_addr,
data, size); data, size);
if (!driver_loaded) if (!driver_loaded)
bnx2x_turn_off_sf(bp); bnx2x_turn_off_sf(bp, port);
break; break;
case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT: case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE: case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
......
drivers/net/bnx2x_main.c
浏览文件 @ 17de50b7
...@@ -1788,11 +1788,11 @@ static void bnx2x_release_phy_lock(struct bnx2x *bp) ...@@ -1788,11 +1788,11 @@ static void bnx2x_release_phy_lock(struct bnx2x *bp)
mutex_unlock(&bp->port.phy_mutex); mutex_unlock(&bp->port.phy_mutex);
} }
int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode) int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
{ {
/* The GPIO should be swapped if swap register is set and active */ /* The GPIO should be swapped if swap register is set and active */
int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ BP_PORT(bp); REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
int gpio_shift = gpio_num + int gpio_shift = gpio_num +
(gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
u32 gpio_mask = (1 << gpio_shift); u32 gpio_mask = (1 << gpio_shift);
...@@ -1824,7 +1824,7 @@ int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode) ...@@ -1824,7 +1824,7 @@ int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode)
gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS); gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
break; break;
case MISC_REGISTERS_GPIO_INPUT_HI_Z : case MISC_REGISTERS_GPIO_INPUT_HI_Z:
DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> input\n", DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> input\n",
gpio_num, gpio_shift); gpio_num, gpio_shift);
/* set FLOAT */ /* set FLOAT */
...@@ -2553,12 +2553,12 @@ static inline void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn) ...@@ -2553,12 +2553,12 @@ static inline void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
case SHARED_HW_CFG_BOARD_TYPE_BCM957710A1022G: case SHARED_HW_CFG_BOARD_TYPE_BCM957710A1022G:
/* Fan failure attention */ /* Fan failure attention */
/* The PHY reset is controled by GPIO 1 */ /* The PHY reset is controlled by GPIO 1 */
bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
MISC_REGISTERS_GPIO_OUTPUT_LOW); MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
/* Low power mode is controled by GPIO 2 */ /* Low power mode is controlled by GPIO 2 */
bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
MISC_REGISTERS_GPIO_OUTPUT_LOW); MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
/* mark the failure */ /* mark the failure */
bp->link_params.ext_phy_config &= bp->link_params.ext_phy_config &=
~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK; ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
......
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