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提交 0fcb6155 编写于 作者: J Jerome Glisse 提交者： Alex Deucher
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radeon/kms: cleanup async dma packet checking 

This simplify and cleanup the async dma checking.
Signed-off-by: NJerome Glisse <jglisse@redhat.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
上级 4e872ae2
隐藏空白更改
内联 并排
Showing with 417 addition and 435 deletion
drivers/gpu/drm/radeon/evergreen.c
浏览文件 @ 0fcb6155
...@@ -3280,14 +3280,14 @@ void evergreen_dma_fence_ring_emit(struct radeon_device *rdev, ...@@ -3280,14 +3280,14 @@ void evergreen_dma_fence_ring_emit(struct radeon_device *rdev,
struct radeon_ring *ring = &rdev->ring[fence->ring]; struct radeon_ring *ring = &rdev->ring[fence->ring];
u64 addr = rdev->fence_drv[fence->ring].gpu_addr; u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
/* write the fence */ /* write the fence */
radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_FENCE, 0, 0, 0)); radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_FENCE, 0, 0));
radeon_ring_write(ring, addr & 0xfffffffc); radeon_ring_write(ring, addr & 0xfffffffc);
radeon_ring_write(ring, (upper_32_bits(addr) & 0xff)); radeon_ring_write(ring, (upper_32_bits(addr) & 0xff));
radeon_ring_write(ring, fence->seq); radeon_ring_write(ring, fence->seq);
/* generate an interrupt */ /* generate an interrupt */
radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_TRAP, 0, 0, 0)); radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_TRAP, 0, 0));
/* flush HDP */ /* flush HDP */
radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0)); radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0));
radeon_ring_write(ring, (0xf << 16) | (HDP_MEM_COHERENCY_FLUSH_CNTL >> 2)); radeon_ring_write(ring, (0xf << 16) | (HDP_MEM_COHERENCY_FLUSH_CNTL >> 2));
radeon_ring_write(ring, 1); radeon_ring_write(ring, 1);
} }
...@@ -3310,7 +3310,7 @@ void evergreen_dma_ring_ib_execute(struct radeon_device *rdev, ...@@ -3310,7 +3310,7 @@ void evergreen_dma_ring_ib_execute(struct radeon_device *rdev,
while ((next_rptr & 7) != 5) while ((next_rptr & 7) != 5)
next_rptr++; next_rptr++;
next_rptr += 3; next_rptr += 3;
radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1)); radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 1));
radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff); radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff);
radeon_ring_write(ring, next_rptr); radeon_ring_write(ring, next_rptr);
...@@ -3320,8 +3320,8 @@ void evergreen_dma_ring_ib_execute(struct radeon_device *rdev, ...@@ -3320,8 +3320,8 @@ void evergreen_dma_ring_ib_execute(struct radeon_device *rdev,
* Pad as necessary with NOPs. * Pad as necessary with NOPs.
*/ */
while ((ring->wptr & 7) != 5) while ((ring->wptr & 7) != 5)
radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0)); radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_NOP, 0, 0));
radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_INDIRECT_BUFFER, 0, 0, 0)); radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_INDIRECT_BUFFER, 0, 0));
radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0)); radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0));
radeon_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF)); radeon_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF));
...@@ -3380,7 +3380,7 @@ int evergreen_copy_dma(struct radeon_device *rdev, ...@@ -3380,7 +3380,7 @@ int evergreen_copy_dma(struct radeon_device *rdev,
if (cur_size_in_dw > 0xFFFFF) if (cur_size_in_dw > 0xFFFFF)
cur_size_in_dw = 0xFFFFF; cur_size_in_dw = 0xFFFFF;
size_in_dw -= cur_size_in_dw; size_in_dw -= cur_size_in_dw;
radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_COPY, 0, 0, cur_size_in_dw)); radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_COPY, 0, cur_size_in_dw));
radeon_ring_write(ring, dst_offset & 0xfffffffc); radeon_ring_write(ring, dst_offset & 0xfffffffc);
radeon_ring_write(ring, src_offset & 0xfffffffc); radeon_ring_write(ring, src_offset & 0xfffffffc);
radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff); radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff);
...@@ -3488,7 +3488,7 @@ static int evergreen_startup(struct radeon_device *rdev) ...@@ -3488,7 +3488,7 @@ static int evergreen_startup(struct radeon_device *rdev)
ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET, r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
DMA_RB_RPTR, DMA_RB_WPTR, DMA_RB_RPTR, DMA_RB_WPTR,
2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0)); 2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0));
if (r) if (r)
return r; return r;
......
drivers/gpu/drm/radeon/evergreen_cs.c
浏览文件 @ 0fcb6155
...@@ -2670,16 +2670,6 @@ int evergreen_cs_parse(struct radeon_cs_parser *p) ...@@ -2670,16 +2670,6 @@ int evergreen_cs_parse(struct radeon_cs_parser *p)
return 0; return 0;
} }
/*
* DMA
*/
#define GET_DMA_CMD(h) (((h) & 0xf0000000) >> 28)
#define GET_DMA_COUNT(h) ((h) & 0x000fffff)
#define GET_DMA_T(h) (((h) & 0x00800000) >> 23)
#define GET_DMA_NEW(h) (((h) & 0x04000000) >> 26)
#define GET_DMA_MISC(h) (((h) & 0x0700000) >> 20)
/** /**
* evergreen_dma_cs_parse() - parse the DMA IB * evergreen_dma_cs_parse() - parse the DMA IB
* @p: parser structure holding parsing context. * @p: parser structure holding parsing context.
...@@ -2693,9 +2683,9 @@ int evergreen_dma_cs_parse(struct radeon_cs_parser *p) ...@@ -2693,9 +2683,9 @@ int evergreen_dma_cs_parse(struct radeon_cs_parser *p)
{ {
struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx]; struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
struct radeon_cs_reloc *src_reloc, *dst_reloc, *dst2_reloc; struct radeon_cs_reloc *src_reloc, *dst_reloc, *dst2_reloc;
u32 header, cmd, count, tiled, new_cmd, misc; u32 header, cmd, count, sub_cmd;
volatile u32 *ib = p->ib.ptr; volatile u32 *ib = p->ib.ptr;
u32 idx, idx_value; u32 idx;
u64 src_offset, dst_offset, dst2_offset; u64 src_offset, dst_offset, dst2_offset;
int r; int r;
...@@ -2709,9 +2699,7 @@ int evergreen_dma_cs_parse(struct radeon_cs_parser *p) ...@@ -2709,9 +2699,7 @@ int evergreen_dma_cs_parse(struct radeon_cs_parser *p)
header = radeon_get_ib_value(p, idx); header = radeon_get_ib_value(p, idx);
cmd = GET_DMA_CMD(header); cmd = GET_DMA_CMD(header);
count = GET_DMA_COUNT(header); count = GET_DMA_COUNT(header);
tiled = GET_DMA_T(header); sub_cmd = GET_DMA_SUB_CMD(header);
new_cmd = GET_DMA_NEW(header);
misc = GET_DMA_MISC(header);
switch (cmd) { switch (cmd) {
case DMA_PACKET_WRITE: case DMA_PACKET_WRITE:
...@@ -2720,19 +2708,27 @@ int evergreen_dma_cs_parse(struct radeon_cs_parser *p) ...@@ -2720,19 +2708,27 @@ int evergreen_dma_cs_parse(struct radeon_cs_parser *p)
DRM_ERROR("bad DMA_PACKET_WRITE\n"); DRM_ERROR("bad DMA_PACKET_WRITE\n");
return -EINVAL; return -EINVAL;
} }
if (tiled) { switch (sub_cmd) {
/* tiled */
case 8:
dst_offset = ib[idx+1]; dst_offset = ib[idx+1];
dst_offset <<= 8; dst_offset <<= 8;
ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8); ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8);
p->idx += count + 7; p->idx += count + 7;
} else { break;
/* linear */
case 0:
dst_offset = ib[idx+1]; dst_offset = ib[idx+1];
dst_offset |= ((u64)(ib[idx+2] & 0xff)) << 32; dst_offset |= ((u64)(ib[idx+2] & 0xff)) << 32;
ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc); ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
ib[idx+2] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff; ib[idx+2] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff;
p->idx += count + 3; p->idx += count + 3;
break;
default:
DRM_ERROR("bad DMA_PACKET_WRITE [%6d] 0x%08x sub cmd is not 0 or 8\n", idx, ib[idx+0]);
return -EINVAL;
} }
if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) { if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
dev_warn(p->dev, "DMA write buffer too small (%llu %lu)\n", dev_warn(p->dev, "DMA write buffer too small (%llu %lu)\n",
...@@ -2751,338 +2747,330 @@ int evergreen_dma_cs_parse(struct radeon_cs_parser *p) ...@@ -2751,338 +2747,330 @@ int evergreen_dma_cs_parse(struct radeon_cs_parser *p)
DRM_ERROR("bad DMA_PACKET_COPY\n"); DRM_ERROR("bad DMA_PACKET_COPY\n");
return -EINVAL; return -EINVAL;
} }
if (tiled) { switch (sub_cmd) {
idx_value = radeon_get_ib_value(p, idx + 2); /* Copy L2L, DW aligned */
if (new_cmd) { case 0x00:
switch (misc) { /* L2L, dw */
case 0: src_offset = ib[idx+2];
/* L2T, frame to fields */ src_offset |= ((u64)(ib[idx+4] & 0xff)) << 32;
if (idx_value & (1 << 31)) { dst_offset = ib[idx+1];
DRM_ERROR("bad L2T, frame to fields DMA_PACKET_COPY\n"); dst_offset |= ((u64)(ib[idx+3] & 0xff)) << 32;
return -EINVAL; if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {
} dev_warn(p->dev, "DMA L2L, dw src buffer too small (%llu %lu)\n",
r = r600_dma_cs_next_reloc(p, &dst2_reloc); src_offset + (count * 4), radeon_bo_size(src_reloc->robj));
if (r) { return -EINVAL;
DRM_ERROR("bad L2T, frame to fields DMA_PACKET_COPY\n"); }
return -EINVAL; if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
} dev_warn(p->dev, "DMA L2L, dw dst buffer too small (%llu %lu)\n",
dst_offset = ib[idx+1]; dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
dst_offset <<= 8; return -EINVAL;
dst2_offset = ib[idx+2]; }
dst2_offset <<= 8; ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
src_offset = ib[idx+8]; ib[idx+2] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc);
src_offset |= ((u64)(ib[idx+9] & 0xff)) << 32; ib[idx+3] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff;
if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) { ib[idx+4] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
dev_warn(p->dev, "DMA L2T, frame to fields src buffer too small (%llu %lu)\n", p->idx += 5;
src_offset + (count * 4), radeon_bo_size(src_reloc->robj)); break;
return -EINVAL; /* Copy L2T/T2L */
} case 0x08:
if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) { /* detile bit */
dev_warn(p->dev, "DMA L2T, frame to fields buffer too small (%llu %lu)\n", if (ib[idx + 2] & (1 << 31)) {
dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj)); /* tiled src, linear dst */
return -EINVAL; src_offset = ib[idx+1];
} src_offset <<= 8;
if ((dst2_offset + (count * 4)) > radeon_bo_size(dst2_reloc->robj)) { ib[idx+1] += (u32)(src_reloc->lobj.gpu_offset >> 8);
dev_warn(p->dev, "DMA L2T, frame to fields buffer too small (%llu %lu)\n",
dst2_offset + (count * 4), radeon_bo_size(dst2_reloc->robj)); dst_offset = radeon_get_ib_value(p, idx + 7);
return -EINVAL; dst_offset |= ((u64)(ib[idx+8] & 0xff)) << 32;
} ib[idx+7] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8); ib[idx+8] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff;
ib[idx+2] += (u32)(dst2_reloc->lobj.gpu_offset >> 8);
ib[idx+8] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc);
ib[idx+9] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
p->idx += 10;
break;
case 1:
/* L2T, T2L partial */
if (p->family < CHIP_CAYMAN) {
DRM_ERROR("L2T, T2L Partial is cayman only !\n");
return -EINVAL;
}
/* detile bit */
if (idx_value & (1 << 31)) {
/* tiled src, linear dst */
ib[idx+1] += (u32)(src_reloc->lobj.gpu_offset >> 8);
ib[idx+7] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
ib[idx+8] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff;
} else {
/* linear src, tiled dst */
ib[idx+7] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc);
ib[idx+8] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8);
}
p->idx += 12;
break;
case 3:
/* L2T, broadcast */
if (idx_value & (1 << 31)) {
DRM_ERROR("bad L2T, broadcast DMA_PACKET_COPY\n");
return -EINVAL;
}
r = r600_dma_cs_next_reloc(p, &dst2_reloc);
if (r) {
DRM_ERROR("bad L2T, broadcast DMA_PACKET_COPY\n");
return -EINVAL;
}
dst_offset = ib[idx+1];
dst_offset <<= 8;
dst2_offset = ib[idx+2];
dst2_offset <<= 8;
src_offset = ib[idx+8];
src_offset |= ((u64)(ib[idx+9] & 0xff)) << 32;
if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {
dev_warn(p->dev, "DMA L2T, broadcast src buffer too small (%llu %lu)\n",
src_offset + (count * 4), radeon_bo_size(src_reloc->robj));
return -EINVAL;
}
if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
dev_warn(p->dev, "DMA L2T, broadcast dst buffer too small (%llu %lu)\n",
dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
return -EINVAL;
}
if ((dst2_offset + (count * 4)) > radeon_bo_size(dst2_reloc->robj)) {
dev_warn(p->dev, "DMA L2T, broadcast dst2 buffer too small (%llu %lu)\n",
dst2_offset + (count * 4), radeon_bo_size(dst2_reloc->robj));
return -EINVAL;
}
ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8);
ib[idx+2] += (u32)(dst2_reloc->lobj.gpu_offset >> 8);
ib[idx+8] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc);
ib[idx+9] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
p->idx += 10;
break;
case 4:
/* L2T, T2L */
/* detile bit */
if (idx_value & (1 << 31)) {
/* tiled src, linear dst */
src_offset = ib[idx+1];
src_offset <<= 8;
ib[idx+1] += (u32)(src_reloc->lobj.gpu_offset >> 8);
dst_offset = ib[idx+7];
dst_offset |= ((u64)(ib[idx+8] & 0xff)) << 32;
ib[idx+7] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
ib[idx+8] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff;
} else {
/* linear src, tiled dst */
src_offset = ib[idx+7];
src_offset |= ((u64)(ib[idx+8] & 0xff)) << 32;
ib[idx+7] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc);
ib[idx+8] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
dst_offset = ib[idx+1];
dst_offset <<= 8;
ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8);
}
if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {
dev_warn(p->dev, "DMA L2T, T2L src buffer too small (%llu %lu)\n",
src_offset + (count * 4), radeon_bo_size(src_reloc->robj));
return -EINVAL;
}
if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
dev_warn(p->dev, "DMA L2T, T2L dst buffer too small (%llu %lu)\n",
dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
return -EINVAL;
}
p->idx += 9;
break;
case 5:
/* T2T partial */
if (p->family < CHIP_CAYMAN) {
DRM_ERROR("L2T, T2L Partial is cayman only !\n");
return -EINVAL;
}
ib[idx+1] += (u32)(src_reloc->lobj.gpu_offset >> 8);
ib[idx+4] += (u32)(dst_reloc->lobj.gpu_offset >> 8);
p->idx += 13;
break;
case 7:
/* L2T, broadcast */
if (idx_value & (1 << 31)) {
DRM_ERROR("bad L2T, broadcast DMA_PACKET_COPY\n");
return -EINVAL;
}
r = r600_dma_cs_next_reloc(p, &dst2_reloc);
if (r) {
DRM_ERROR("bad L2T, broadcast DMA_PACKET_COPY\n");
return -EINVAL;
}
dst_offset = ib[idx+1];
dst_offset <<= 8;
dst2_offset = ib[idx+2];
dst2_offset <<= 8;
src_offset = ib[idx+8];
src_offset |= ((u64)(ib[idx+9] & 0xff)) << 32;
if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {
dev_warn(p->dev, "DMA L2T, broadcast src buffer too small (%llu %lu)\n",
src_offset + (count * 4), radeon_bo_size(src_reloc->robj));
return -EINVAL;
}
if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
dev_warn(p->dev, "DMA L2T, broadcast dst buffer too small (%llu %lu)\n",
dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
return -EINVAL;
}
if ((dst2_offset + (count * 4)) > radeon_bo_size(dst2_reloc->robj)) {
dev_warn(p->dev, "DMA L2T, broadcast dst2 buffer too small (%llu %lu)\n",
dst2_offset + (count * 4), radeon_bo_size(dst2_reloc->robj));
return -EINVAL;
}
ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8);
ib[idx+2] += (u32)(dst2_reloc->lobj.gpu_offset >> 8);
ib[idx+8] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc);
ib[idx+9] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
p->idx += 10;
break;
default:
DRM_ERROR("bad DMA_PACKET_COPY misc %u\n", misc);
return -EINVAL;
}
} else { } else {
switch (misc) { /* linear src, tiled dst */
case 0: src_offset = ib[idx+7];
/* detile bit */ src_offset |= ((u64)(ib[idx+8] & 0xff)) << 32;
if (idx_value & (1 << 31)) { ib[idx+7] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc);
/* tiled src, linear dst */ ib[idx+8] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
src_offset = ib[idx+1];
src_offset <<= 8; dst_offset = ib[idx+1];
ib[idx+1] += (u32)(src_reloc->lobj.gpu_offset >> 8); dst_offset <<= 8;
ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8);
dst_offset = ib[idx+7];
dst_offset |= ((u64)(ib[idx+8] & 0xff)) << 32;
ib[idx+7] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
ib[idx+8] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff;
} else {
/* linear src, tiled dst */
src_offset = ib[idx+7];
src_offset |= ((u64)(ib[idx+8] & 0xff)) << 32;
ib[idx+7] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc);
ib[idx+8] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
dst_offset = ib[idx+1];
dst_offset <<= 8;
ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8);
}
if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {
dev_warn(p->dev, "DMA L2T, broadcast src buffer too small (%llu %lu)\n",
src_offset + (count * 4), radeon_bo_size(src_reloc->robj));
return -EINVAL;
}
if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
dev_warn(p->dev, "DMA L2T, broadcast dst buffer too small (%llu %lu)\n",
dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
return -EINVAL;
}
p->idx += 9;
break;
default:
DRM_ERROR("bad DMA_PACKET_COPY misc %u\n", misc);
return -EINVAL;
}
} }
} else { if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {
if (new_cmd) { dev_warn(p->dev, "DMA L2T, src buffer too small (%llu %lu)\n",
switch (misc) { src_offset + (count * 4), radeon_bo_size(src_reloc->robj));
case 0: return -EINVAL;
/* L2L, byte */ }
src_offset = ib[idx+2]; if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
src_offset |= ((u64)(ib[idx+4] & 0xff)) << 32; dev_warn(p->dev, "DMA L2T, dst buffer too small (%llu %lu)\n",
dst_offset = ib[idx+1]; dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
dst_offset |= ((u64)(ib[idx+3] & 0xff)) << 32; return -EINVAL;
if ((src_offset + count) > radeon_bo_size(src_reloc->robj)) { }
dev_warn(p->dev, "DMA L2L, byte src buffer too small (%llu %lu)\n", p->idx += 9;
src_offset + count, radeon_bo_size(src_reloc->robj)); break;
return -EINVAL; /* Copy L2L, byte aligned */
} case 0x40:
if ((dst_offset + count) > radeon_bo_size(dst_reloc->robj)) { /* L2L, byte */
dev_warn(p->dev, "DMA L2L, byte dst buffer too small (%llu %lu)\n", src_offset = ib[idx+2];
dst_offset + count, radeon_bo_size(dst_reloc->robj)); src_offset |= ((u64)(ib[idx+4] & 0xff)) << 32;
return -EINVAL; dst_offset = ib[idx+1];
} dst_offset |= ((u64)(ib[idx+3] & 0xff)) << 32;
ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xffffffff); if ((src_offset + count) > radeon_bo_size(src_reloc->robj)) {
ib[idx+2] += (u32)(src_reloc->lobj.gpu_offset & 0xffffffff); dev_warn(p->dev, "DMA L2L, byte src buffer too small (%llu %lu)\n",
ib[idx+3] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff; src_offset + count, radeon_bo_size(src_reloc->robj));
ib[idx+4] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff; return -EINVAL;
p->idx += 5; }
break; if ((dst_offset + count) > radeon_bo_size(dst_reloc->robj)) {
case 1: dev_warn(p->dev, "DMA L2L, byte dst buffer too small (%llu %lu)\n",
/* L2L, partial */ dst_offset + count, radeon_bo_size(dst_reloc->robj));
if (p->family < CHIP_CAYMAN) { return -EINVAL;
DRM_ERROR("L2L Partial is cayman only !\n"); }
return -EINVAL; ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xffffffff);
} ib[idx+2] += (u32)(src_reloc->lobj.gpu_offset & 0xffffffff);
ib[idx+1] += (u32)(src_reloc->lobj.gpu_offset & 0xffffffff); ib[idx+3] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff;
ib[idx+2] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff; ib[idx+4] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
ib[idx+4] += (u32)(dst_reloc->lobj.gpu_offset & 0xffffffff); p->idx += 5;
ib[idx+5] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff; break;
/* Copy L2L, partial */
p->idx += 9; case 0x41:
break; /* L2L, partial */
case 4: if (p->family < CHIP_CAYMAN) {
/* L2L, dw, broadcast */ DRM_ERROR("L2L Partial is cayman only !\n");
r = r600_dma_cs_next_reloc(p, &dst2_reloc); return -EINVAL;
if (r) { }
DRM_ERROR("bad L2L, dw, broadcast DMA_PACKET_COPY\n"); ib[idx+1] += (u32)(src_reloc->lobj.gpu_offset & 0xffffffff);
return -EINVAL; ib[idx+2] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
} ib[idx+4] += (u32)(dst_reloc->lobj.gpu_offset & 0xffffffff);
dst_offset = ib[idx+1]; ib[idx+5] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff;
dst_offset |= ((u64)(ib[idx+4] & 0xff)) << 32;
dst2_offset = ib[idx+2]; p->idx += 9;
dst2_offset |= ((u64)(ib[idx+5] & 0xff)) << 32; break;
src_offset = ib[idx+3]; /* Copy L2L, DW aligned, broadcast */
src_offset |= ((u64)(ib[idx+6] & 0xff)) << 32; case 0x44:
if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) { /* L2L, dw, broadcast */
dev_warn(p->dev, "DMA L2L, dw, broadcast src buffer too small (%llu %lu)\n", r = r600_dma_cs_next_reloc(p, &dst2_reloc);
src_offset + (count * 4), radeon_bo_size(src_reloc->robj)); if (r) {
return -EINVAL; DRM_ERROR("bad L2L, dw, broadcast DMA_PACKET_COPY\n");
} return -EINVAL;
if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) { }
dev_warn(p->dev, "DMA L2L, dw, broadcast dst buffer too small (%llu %lu)\n", dst_offset = ib[idx+1];
dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj)); dst_offset |= ((u64)(ib[idx+4] & 0xff)) << 32;
return -EINVAL; dst2_offset = ib[idx+2];
} dst2_offset |= ((u64)(ib[idx+5] & 0xff)) << 32;
if ((dst2_offset + (count * 4)) > radeon_bo_size(dst2_reloc->robj)) { src_offset = ib[idx+3];
dev_warn(p->dev, "DMA L2L, dw, broadcast dst2 buffer too small (%llu %lu)\n", src_offset |= ((u64)(ib[idx+6] & 0xff)) << 32;
dst2_offset + (count * 4), radeon_bo_size(dst2_reloc->robj)); if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {
return -EINVAL; dev_warn(p->dev, "DMA L2L, dw, broadcast src buffer too small (%llu %lu)\n",
} src_offset + (count * 4), radeon_bo_size(src_reloc->robj));
ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc); return -EINVAL;
ib[idx+2] += (u32)(dst2_reloc->lobj.gpu_offset & 0xfffffffc); }
ib[idx+3] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc); if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
ib[idx+4] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff; dev_warn(p->dev, "DMA L2L, dw, broadcast dst buffer too small (%llu %lu)\n",
ib[idx+5] += upper_32_bits(dst2_reloc->lobj.gpu_offset) & 0xff; dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
ib[idx+6] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff; return -EINVAL;
p->idx += 7; }
break; if ((dst2_offset + (count * 4)) > radeon_bo_size(dst2_reloc->robj)) {
default: dev_warn(p->dev, "DMA L2L, dw, broadcast dst2 buffer too small (%llu %lu)\n",
DRM_ERROR("bad DMA_PACKET_COPY misc %u\n", misc); dst2_offset + (count * 4), radeon_bo_size(dst2_reloc->robj));
return -EINVAL; return -EINVAL;
} }
ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
ib[idx+2] += (u32)(dst2_reloc->lobj.gpu_offset & 0xfffffffc);
ib[idx+3] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc);
ib[idx+4] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff;
ib[idx+5] += upper_32_bits(dst2_reloc->lobj.gpu_offset) & 0xff;
ib[idx+6] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
p->idx += 7;
break;
/* Copy L2T Frame to Field */
case 0x48:
if (ib[idx + 2] & (1 << 31)) {
DRM_ERROR("bad L2T, frame to fields DMA_PACKET_COPY\n");
return -EINVAL;
}
r = r600_dma_cs_next_reloc(p, &dst2_reloc);
if (r) {
DRM_ERROR("bad L2T, frame to fields DMA_PACKET_COPY\n");
return -EINVAL;
}
dst_offset = ib[idx+1];
dst_offset <<= 8;
dst2_offset = ib[idx+2];
dst2_offset <<= 8;
src_offset = ib[idx+8];
src_offset |= ((u64)(ib[idx+9] & 0xff)) << 32;
if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {
dev_warn(p->dev, "DMA L2T, frame to fields src buffer too small (%llu %lu)\n",
src_offset + (count * 4), radeon_bo_size(src_reloc->robj));
return -EINVAL;
}
if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
dev_warn(p->dev, "DMA L2T, frame to fields buffer too small (%llu %lu)\n",
dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
return -EINVAL;
}
if ((dst2_offset + (count * 4)) > radeon_bo_size(dst2_reloc->robj)) {
dev_warn(p->dev, "DMA L2T, frame to fields buffer too small (%llu %lu)\n",
dst2_offset + (count * 4), radeon_bo_size(dst2_reloc->robj));
return -EINVAL;
}
ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8);
ib[idx+2] += (u32)(dst2_reloc->lobj.gpu_offset >> 8);
ib[idx+8] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc);
ib[idx+9] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
p->idx += 10;
break;
/* Copy L2T/T2L, partial */
case 0x49:
/* L2T, T2L partial */
if (p->family < CHIP_CAYMAN) {
DRM_ERROR("L2T, T2L Partial is cayman only !\n");
return -EINVAL;
}
/* detile bit */
if (ib[idx + 2 ] & (1 << 31)) {
/* tiled src, linear dst */
ib[idx+1] += (u32)(src_reloc->lobj.gpu_offset >> 8);
ib[idx+7] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
ib[idx+8] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff;
} else {
/* linear src, tiled dst */
ib[idx+7] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc);
ib[idx+8] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8);
}
p->idx += 12;
break;
/* Copy L2T broadcast */
case 0x4b:
/* L2T, broadcast */
if (ib[idx + 2] & (1 << 31)) {
DRM_ERROR("bad L2T, broadcast DMA_PACKET_COPY\n");
return -EINVAL;
}
r = r600_dma_cs_next_reloc(p, &dst2_reloc);
if (r) {
DRM_ERROR("bad L2T, broadcast DMA_PACKET_COPY\n");
return -EINVAL;
}
dst_offset = ib[idx+1];
dst_offset <<= 8;
dst2_offset = ib[idx+2];
dst2_offset <<= 8;
src_offset = ib[idx+8];
src_offset |= ((u64)(ib[idx+9] & 0xff)) << 32;
if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {
dev_warn(p->dev, "DMA L2T, broadcast src buffer too small (%llu %lu)\n",
src_offset + (count * 4), radeon_bo_size(src_reloc->robj));
return -EINVAL;
}
if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
dev_warn(p->dev, "DMA L2T, broadcast dst buffer too small (%llu %lu)\n",
dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
return -EINVAL;
}
if ((dst2_offset + (count * 4)) > radeon_bo_size(dst2_reloc->robj)) {
dev_warn(p->dev, "DMA L2T, broadcast dst2 buffer too small (%llu %lu)\n",
dst2_offset + (count * 4), radeon_bo_size(dst2_reloc->robj));
return -EINVAL;
}
ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8);
ib[idx+2] += (u32)(dst2_reloc->lobj.gpu_offset >> 8);
ib[idx+8] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc);
ib[idx+9] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
p->idx += 10;
break;
/* Copy L2T/T2L (tile units) */
case 0x4c:
/* L2T, T2L */
/* detile bit */
if (ib[idx + 2] & (1 << 31)) {
/* tiled src, linear dst */
src_offset = ib[idx+1];
src_offset <<= 8;
ib[idx+1] += (u32)(src_reloc->lobj.gpu_offset >> 8);
dst_offset = ib[idx+7];
dst_offset |= ((u64)(ib[idx+8] & 0xff)) << 32;
ib[idx+7] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
ib[idx+8] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff;
} else { } else {
/* L2L, dw */ /* linear src, tiled dst */
src_offset = ib[idx+2]; src_offset = ib[idx+7];
src_offset |= ((u64)(ib[idx+4] & 0xff)) << 32; src_offset |= ((u64)(ib[idx+8] & 0xff)) << 32;
ib[idx+7] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc);
ib[idx+8] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
dst_offset = ib[idx+1]; dst_offset = ib[idx+1];
dst_offset |= ((u64)(ib[idx+3] & 0xff)) << 32; dst_offset <<= 8;
if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) { ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8);
dev_warn(p->dev, "DMA L2L, dw src buffer too small (%llu %lu)\n",
src_offset + (count * 4), radeon_bo_size(src_reloc->robj));
return -EINVAL;
}
if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
dev_warn(p->dev, "DMA L2L, dw dst buffer too small (%llu %lu)\n",
dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
return -EINVAL;
}
ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
ib[idx+2] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc);
ib[idx+3] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff;
ib[idx+4] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
p->idx += 5;
} }
if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {
dev_warn(p->dev, "DMA L2T, T2L src buffer too small (%llu %lu)\n",
src_offset + (count * 4), radeon_bo_size(src_reloc->robj));
return -EINVAL;
}
if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
dev_warn(p->dev, "DMA L2T, T2L dst buffer too small (%llu %lu)\n",
dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
return -EINVAL;
}
p->idx += 9;
break;
/* Copy T2T, partial (tile units) */
case 0x4d:
/* T2T partial */
if (p->family < CHIP_CAYMAN) {
DRM_ERROR("L2T, T2L Partial is cayman only !\n");
return -EINVAL;
}
ib[idx+1] += (u32)(src_reloc->lobj.gpu_offset >> 8);
ib[idx+4] += (u32)(dst_reloc->lobj.gpu_offset >> 8);
p->idx += 13;
break;
/* Copy L2T broadcast (tile units) */
case 0x4f:
/* L2T, broadcast */
if (ib[idx + 2] & (1 << 31)) {
DRM_ERROR("bad L2T, broadcast DMA_PACKET_COPY\n");
return -EINVAL;
}
r = r600_dma_cs_next_reloc(p, &dst2_reloc);
if (r) {
DRM_ERROR("bad L2T, broadcast DMA_PACKET_COPY\n");
return -EINVAL;
}
dst_offset = ib[idx+1];
dst_offset <<= 8;
dst2_offset = ib[idx+2];
dst2_offset <<= 8;
src_offset = ib[idx+8];
src_offset |= ((u64)(ib[idx+9] & 0xff)) << 32;
if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {
dev_warn(p->dev, "DMA L2T, broadcast src buffer too small (%llu %lu)\n",
src_offset + (count * 4), radeon_bo_size(src_reloc->robj));
return -EINVAL;
}
if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
dev_warn(p->dev, "DMA L2T, broadcast dst buffer too small (%llu %lu)\n",
dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
return -EINVAL;
}
if ((dst2_offset + (count * 4)) > radeon_bo_size(dst2_reloc->robj)) {
dev_warn(p->dev, "DMA L2T, broadcast dst2 buffer too small (%llu %lu)\n",
dst2_offset + (count * 4), radeon_bo_size(dst2_reloc->robj));
return -EINVAL;
}
ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8);
ib[idx+2] += (u32)(dst2_reloc->lobj.gpu_offset >> 8);
ib[idx+8] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc);
ib[idx+9] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
p->idx += 10;
break;
default:
DRM_ERROR("bad DMA_PACKET_COPY [%6d] 0x%08x invalid sub cmd\n", idx, ib[idx+0]);
return -EINVAL;
} }
break; break;
case DMA_PACKET_CONSTANT_FILL: case DMA_PACKET_CONSTANT_FILL:
...@@ -3435,88 +3423,79 @@ int evergreen_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib) ...@@ -3435,88 +3423,79 @@ int evergreen_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib)
int evergreen_dma_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib) int evergreen_dma_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib)
{ {
u32 idx = 0; u32 idx = 0;
u32 header, cmd, count, tiled, new_cmd, misc; u32 header, cmd, count, sub_cmd;
do { do {
header = ib->ptr[idx]; header = ib->ptr[idx];
cmd = GET_DMA_CMD(header); cmd = GET_DMA_CMD(header);
count = GET_DMA_COUNT(header); count = GET_DMA_COUNT(header);
tiled = GET_DMA_T(header); sub_cmd = GET_DMA_SUB_CMD(header);
new_cmd = GET_DMA_NEW(header);
misc = GET_DMA_MISC(header);
switch (cmd) { switch (cmd) {
case DMA_PACKET_WRITE: case DMA_PACKET_WRITE:
if (tiled) switch (sub_cmd) {
/* tiled */
case 8:
idx += count + 7; idx += count + 7;
else break;
/* linear */
case 0:
idx += count + 3; idx += count + 3;
break;
default:
DRM_ERROR("bad DMA_PACKET_WRITE [%6d] 0x%08x sub cmd is not 0 or 8\n", idx, ib->ptr[idx]);
return -EINVAL;
}
break; break;
case DMA_PACKET_COPY: case DMA_PACKET_COPY:
if (tiled) { switch (sub_cmd) {
if (new_cmd) { /* Copy L2L, DW aligned */
switch (misc) { case 0x00:
case 0: idx += 5;
/* L2T, frame to fields */ break;
idx += 10; /* Copy L2T/T2L */
break; case 0x08:
case 1: idx += 9;
/* L2T, T2L partial */ break;
idx += 12; /* Copy L2L, byte aligned */
break; case 0x40:
case 3: idx += 5;
/* L2T, broadcast */ break;
idx += 10; /* Copy L2L, partial */
break; case 0x41:
case 4: idx += 9;
/* L2T, T2L */ break;
idx += 9; /* Copy L2L, DW aligned, broadcast */
break; case 0x44:
case 5: idx += 7;
/* T2T partial */ break;
idx += 13; /* Copy L2T Frame to Field */
break; case 0x48:
case 7: idx += 10;
/* L2T, broadcast */ break;
idx += 10; /* Copy L2T/T2L, partial */
break; case 0x49:
default: idx += 12;
DRM_ERROR("bad DMA_PACKET_COPY misc %u\n", misc); break;
return -EINVAL; /* Copy L2T broadcast */
} case 0x4b:
} else { idx += 10;
switch (misc) { break;
case 0: /* Copy L2T/T2L (tile units) */
idx += 9; case 0x4c:
break; idx += 9;
default: break;
DRM_ERROR("bad DMA_PACKET_COPY misc %u\n", misc); /* Copy T2T, partial (tile units) */
return -EINVAL; case 0x4d:
} idx += 13;
} break;
} else { /* Copy L2T broadcast (tile units) */
if (new_cmd) { case 0x4f:
switch (misc) { idx += 10;
case 0: break;
/* L2L, byte */ default:
idx += 5; DRM_ERROR("bad DMA_PACKET_COPY [%6d] 0x%08x invalid sub cmd\n", idx, ib->ptr[idx]);
break; return -EINVAL;
case 1:
/* L2L, partial */
idx += 9;
break;
case 4:
/* L2L, dw, broadcast */
idx += 7;
break;
default:
DRM_ERROR("bad DMA_PACKET_COPY misc %u\n", misc);
return -EINVAL;
}
} else {
/* L2L, dw */
idx += 5;
}
} }
break; break;
case DMA_PACKET_CONSTANT_FILL: case DMA_PACKET_CONSTANT_FILL:
......
drivers/gpu/drm/radeon/evergreend.h
浏览文件 @ 0fcb6155
...@@ -924,20 +924,23 @@ ...@@ -924,20 +924,23 @@
#define CAYMAN_DMA1_CNTL 0xd82c #define CAYMAN_DMA1_CNTL 0xd82c
/* async DMA packets */ /* async DMA packets */
#define DMA_PACKET(cmd, t, s, n) ((((cmd) & 0xF) << 28) | \ #define DMA_PACKET(cmd, sub_cmd, n) ((((cmd) & 0xF) << 28) | \
(((t) & 0x1) << 23) | \ (((sub_cmd) & 0xFF) << 20) |\
(((s) & 0x1) << 22) | \ (((n) & 0xFFFFF) << 0))
(((n) & 0xFFFFF) << 0)) #define GET_DMA_CMD(h) (((h) & 0xf0000000) >> 28)
#define GET_DMA_COUNT(h) ((h) & 0x000fffff)
#define GET_DMA_SUB_CMD(h) (((h) & 0x0ff00000) >> 20)
/* async DMA Packet types */ /* async DMA Packet types */
#define DMA_PACKET_WRITE 0x2 #define DMA_PACKET_WRITE 0x2
#define DMA_PACKET_COPY 0x3 #define DMA_PACKET_COPY 0x3
#define DMA_PACKET_INDIRECT_BUFFER 0x4 #define DMA_PACKET_INDIRECT_BUFFER 0x4
#define DMA_PACKET_SEMAPHORE 0x5 #define DMA_PACKET_SEMAPHORE 0x5
#define DMA_PACKET_FENCE 0x6 #define DMA_PACKET_FENCE 0x6
#define DMA_PACKET_TRAP 0x7 #define DMA_PACKET_TRAP 0x7
#define DMA_PACKET_SRBM_WRITE 0x9 #define DMA_PACKET_SRBM_WRITE 0x9
#define DMA_PACKET_CONSTANT_FILL 0xd #define DMA_PACKET_CONSTANT_FILL 0xd
#define DMA_PACKET_NOP 0xf #define DMA_PACKET_NOP 0xf
/* PCIE link stuff */ /* PCIE link stuff */
#define PCIE_LC_TRAINING_CNTL 0xa1 /* PCIE_P */ #define PCIE_LC_TRAINING_CNTL 0xa1 /* PCIE_P */
......
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