提交 009be664 编写于 作者: D Daniel Vetter

drm/i915: set stc evict disable lra evict w/a

Our workaround list kindly lists that this new default value needs to
be updated in Bspec. Naturally, this did not happen.
Acked-by: NBen Widawsky <ben@bwidawsk.net>
Signed-Off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
上级 bf97b276
...@@ -639,6 +639,7 @@ ...@@ -639,6 +639,7 @@
#define CM0_MASK_SHIFT 16 #define CM0_MASK_SHIFT 16
#define CM0_IZ_OPT_DISABLE (1<<6) #define CM0_IZ_OPT_DISABLE (1<<6)
#define CM0_ZR_OPT_DISABLE (1<<5) #define CM0_ZR_OPT_DISABLE (1<<5)
#define CM0_STC_EVICT_DISABLE_LRA_SNB (1<<5)
#define CM0_DEPTH_EVICT_DISABLE (1<<4) #define CM0_DEPTH_EVICT_DISABLE (1<<4)
#define CM0_COLOR_EVICT_DISABLE (1<<3) #define CM0_COLOR_EVICT_DISABLE (1<<3)
#define CM0_DEPTH_WRITE_DISABLE (1<<1) #define CM0_DEPTH_WRITE_DISABLE (1<<1)
......
...@@ -8878,6 +8878,10 @@ static void gen6_init_clock_gating(struct drm_device *dev) ...@@ -8878,6 +8878,10 @@ static void gen6_init_clock_gating(struct drm_device *dev)
I915_WRITE(WM2_LP_ILK, 0); I915_WRITE(WM2_LP_ILK, 0);
I915_WRITE(WM1_LP_ILK, 0); I915_WRITE(WM1_LP_ILK, 0);
/* clear masked bit */
I915_WRITE(CACHE_MODE_0,
CM0_STC_EVICT_DISABLE_LRA_SNB << CM0_MASK_SHIFT);
I915_WRITE(GEN6_UCGCTL1, I915_WRITE(GEN6_UCGCTL1,
I915_READ(GEN6_UCGCTL1) | I915_READ(GEN6_UCGCTL1) |
GEN6_BLBUNIT_CLOCK_GATE_DISABLE | GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
......
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