mipsregs.h 61.3 KB
Newer Older
L
Linus Torvalds 已提交
1 2 3 4 5 6 7 8 9
/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle
 * Copyright (C) 2000 Silicon Graphics, Inc.
 * Modified for further R[236]000 support by Paul M. Antoine, 1996.
 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
10
 * Copyright (C) 2000, 07 MIPS Technologies, Inc.
11
 * Copyright (C) 2003, 2004  Maciej W. Rozycki
L
Linus Torvalds 已提交
12 13 14 15 16
 */
#ifndef _ASM_MIPSREGS_H
#define _ASM_MIPSREGS_H

#include <linux/linkage.h>
Q
Qais Yousef 已提交
17
#include <linux/types.h>
L
Linus Torvalds 已提交
18
#include <asm/hazards.h>
M
Marc St-Jean 已提交
19
#include <asm/war.h>
L
Linus Torvalds 已提交
20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52

/*
 * The following macros are especially useful for __asm__
 * inline assembler.
 */
#ifndef __STR
#define __STR(x) #x
#endif
#ifndef STR
#define STR(x) __STR(x)
#endif

/*
 *  Configure language
 */
#ifdef __ASSEMBLY__
#define _ULCAST_
#else
#define _ULCAST_ (unsigned long)
#endif

/*
 * Coprocessor 0 register names
 */
#define CP0_INDEX $0
#define CP0_RANDOM $1
#define CP0_ENTRYLO0 $2
#define CP0_ENTRYLO1 $3
#define CP0_CONF $3
#define CP0_CONTEXT $4
#define CP0_PAGEMASK $5
#define CP0_WIRED $6
#define CP0_INFO $7
53
#define CP0_HWRENA $7, 0
L
Linus Torvalds 已提交
54
#define CP0_BADVADDR $8
55
#define CP0_BADINSTR $8, 1
L
Linus Torvalds 已提交
56 57 58 59 60 61 62
#define CP0_COUNT $9
#define CP0_ENTRYHI $10
#define CP0_COMPARE $11
#define CP0_STATUS $12
#define CP0_CAUSE $13
#define CP0_EPC $14
#define CP0_PRID $15
63 64
#define CP0_EBASE $15, 1
#define CP0_CMGCRBASE $15, 3
L
Linus Torvalds 已提交
65
#define CP0_CONFIG $16
66 67
#define CP0_CONFIG3 $16, 3
#define CP0_CONFIG5 $16, 5
L
Linus Torvalds 已提交
68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104
#define CP0_LLADDR $17
#define CP0_WATCHLO $18
#define CP0_WATCHHI $19
#define CP0_XCONTEXT $20
#define CP0_FRAMEMASK $21
#define CP0_DIAGNOSTIC $22
#define CP0_DEBUG $23
#define CP0_DEPC $24
#define CP0_PERFORMANCE $25
#define CP0_ECC $26
#define CP0_CACHEERR $27
#define CP0_TAGLO $28
#define CP0_TAGHI $29
#define CP0_ERROREPC $30
#define CP0_DESAVE $31

/*
 * R4640/R4650 cp0 register names.  These registers are listed
 * here only for completeness; without MMU these CPUs are not useable
 * by Linux.  A future ELKS port might take make Linux run on them
 * though ...
 */
#define CP0_IBASE $0
#define CP0_IBOUND $1
#define CP0_DBASE $2
#define CP0_DBOUND $3
#define CP0_CALG $17
#define CP0_IWATCH $18
#define CP0_DWATCH $19

/*
 * Coprocessor 0 Set 1 register names
 */
#define CP0_S1_DERRADDR0  $26
#define CP0_S1_DERRADDR1  $27
#define CP0_S1_INTCONTROL $20

105 106 107 108 109 110 111 112 113 114
/*
 * Coprocessor 0 Set 2 register names
 */
#define CP0_S2_SRSCTL	  $12	/* MIPSR2 */

/*
 * Coprocessor 0 Set 3 register names
 */
#define CP0_S3_SRSMAP	  $12	/* MIPSR2 */

L
Linus Torvalds 已提交
115 116 117 118 119 120
/*
 *  TX39 Series
 */
#define CP0_TX39_CACHE	$7


121 122 123 124 125 126 127 128 129 130 131 132 133 134
/* Generic EntryLo bit definitions */
#define ENTRYLO_G		(_ULCAST_(1) << 0)
#define ENTRYLO_V		(_ULCAST_(1) << 1)
#define ENTRYLO_D		(_ULCAST_(1) << 2)
#define ENTRYLO_C_SHIFT		3
#define ENTRYLO_C		(_ULCAST_(7) << ENTRYLO_C_SHIFT)

/* R3000 EntryLo bit definitions */
#define R3K_ENTRYLO_G		(_ULCAST_(1) << 8)
#define R3K_ENTRYLO_V		(_ULCAST_(1) << 9)
#define R3K_ENTRYLO_D		(_ULCAST_(1) << 10)
#define R3K_ENTRYLO_N		(_ULCAST_(1) << 11)

/* MIPS32/64 EntryLo bit definitions */
135 136 137
#define MIPS_ENTRYLO_PFN_SHIFT	6
#define MIPS_ENTRYLO_XI		(_ULCAST_(1) << (BITS_PER_LONG - 2))
#define MIPS_ENTRYLO_RI		(_ULCAST_(1) << (BITS_PER_LONG - 1))
138

L
Linus Torvalds 已提交
139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154
/*
 * Values for PageMask register
 */
#ifdef CONFIG_CPU_VR41XX

/* Why doesn't stupidity hurt ... */

#define PM_1K		0x00000000
#define PM_4K		0x00001800
#define PM_16K		0x00007800
#define PM_64K		0x0001f800
#define PM_256K		0x0007f800

#else

#define PM_4K		0x00000000
155
#define PM_8K		0x00002000
L
Linus Torvalds 已提交
156
#define PM_16K		0x00006000
157
#define PM_32K		0x0000e000
L
Linus Torvalds 已提交
158
#define PM_64K		0x0001e000
159
#define PM_128K		0x0003e000
L
Linus Torvalds 已提交
160
#define PM_256K		0x0007e000
161
#define PM_512K		0x000fe000
L
Linus Torvalds 已提交
162
#define PM_1M		0x001fe000
163
#define PM_2M		0x003fe000
L
Linus Torvalds 已提交
164
#define PM_4M		0x007fe000
165
#define PM_8M		0x00ffe000
L
Linus Torvalds 已提交
166
#define PM_16M		0x01ffe000
167
#define PM_32M		0x03ffe000
L
Linus Torvalds 已提交
168 169
#define PM_64M		0x07ffe000
#define PM_256M		0x1fffe000
170
#define PM_1G		0x7fffe000
L
Linus Torvalds 已提交
171 172 173 174 175 176 177

#endif

/*
 * Default page size for a given kernel configuration
 */
#ifdef CONFIG_PAGE_SIZE_4KB
R
Ralf Baechle 已提交
178
#define PM_DEFAULT_MASK PM_4K
179
#elif defined(CONFIG_PAGE_SIZE_8KB)
R
Ralf Baechle 已提交
180
#define PM_DEFAULT_MASK PM_8K
L
Linus Torvalds 已提交
181
#elif defined(CONFIG_PAGE_SIZE_16KB)
R
Ralf Baechle 已提交
182
#define PM_DEFAULT_MASK PM_16K
183
#elif defined(CONFIG_PAGE_SIZE_32KB)
R
Ralf Baechle 已提交
184
#define PM_DEFAULT_MASK PM_32K
L
Linus Torvalds 已提交
185
#elif defined(CONFIG_PAGE_SIZE_64KB)
R
Ralf Baechle 已提交
186
#define PM_DEFAULT_MASK PM_64K
L
Linus Torvalds 已提交
187 188 189 190
#else
#error Bad page size configuration!
#endif

D
David Daney 已提交
191 192 193 194 195 196 197 198 199 200 201 202 203
/*
 * Default huge tlb size for a given kernel configuration
 */
#ifdef CONFIG_PAGE_SIZE_4KB
#define PM_HUGE_MASK	PM_1M
#elif defined(CONFIG_PAGE_SIZE_8KB)
#define PM_HUGE_MASK	PM_4M
#elif defined(CONFIG_PAGE_SIZE_16KB)
#define PM_HUGE_MASK	PM_16M
#elif defined(CONFIG_PAGE_SIZE_32KB)
#define PM_HUGE_MASK	PM_64M
#elif defined(CONFIG_PAGE_SIZE_64KB)
#define PM_HUGE_MASK	PM_256M
204
#elif defined(CONFIG_MIPS_HUGE_TLB_SUPPORT)
D
David Daney 已提交
205 206
#error Bad page size configuration for hugetlbfs!
#endif
L
Linus Torvalds 已提交
207 208 209 210 211 212 213 214 215 216 217 218 219 220

/*
 * Values used for computation of new tlb entries
 */
#define PL_4K		12
#define PL_16K		14
#define PL_64K		16
#define PL_256K		18
#define PL_1M		20
#define PL_4M		22
#define PL_16M		24
#define PL_64M		26
#define PL_256M		28

221 222 223
/*
 * PageGrain bits
 */
R
Ralf Baechle 已提交
224 225 226 227
#define PG_RIE		(_ULCAST_(1) <<	 31)
#define PG_XIE		(_ULCAST_(1) <<	 30)
#define PG_ELPA		(_ULCAST_(1) <<	 29)
#define PG_ESP		(_ULCAST_(1) <<	 28)
228
#define PG_IEC		(_ULCAST_(1) <<  27)
229

230 231 232
/* MIPS32/64 EntryHI bit definitions */
#define MIPS_ENTRYHI_EHINV	(_ULCAST_(1) << 10)

L
Linus Torvalds 已提交
233 234 235
/*
 * R4x00 interrupt enable / cause bits
 */
R
Ralf Baechle 已提交
236 237 238 239 240 241 242 243
#define IE_SW0		(_ULCAST_(1) <<	 8)
#define IE_SW1		(_ULCAST_(1) <<	 9)
#define IE_IRQ0		(_ULCAST_(1) << 10)
#define IE_IRQ1		(_ULCAST_(1) << 11)
#define IE_IRQ2		(_ULCAST_(1) << 12)
#define IE_IRQ3		(_ULCAST_(1) << 13)
#define IE_IRQ4		(_ULCAST_(1) << 14)
#define IE_IRQ5		(_ULCAST_(1) << 15)
L
Linus Torvalds 已提交
244 245 246 247

/*
 * R4x00 interrupt cause bits
 */
R
Ralf Baechle 已提交
248 249 250 251 252 253 254 255
#define C_SW0		(_ULCAST_(1) <<	 8)
#define C_SW1		(_ULCAST_(1) <<	 9)
#define C_IRQ0		(_ULCAST_(1) << 10)
#define C_IRQ1		(_ULCAST_(1) << 11)
#define C_IRQ2		(_ULCAST_(1) << 12)
#define C_IRQ3		(_ULCAST_(1) << 13)
#define C_IRQ4		(_ULCAST_(1) << 14)
#define C_IRQ5		(_ULCAST_(1) << 15)
L
Linus Torvalds 已提交
256 257 258 259 260 261 262 263 264 265 266 267 268

/*
 * Bitfields in the R4xx0 cp0 status register
 */
#define ST0_IE			0x00000001
#define ST0_EXL			0x00000002
#define ST0_ERL			0x00000004
#define ST0_KSU			0x00000018
#  define KSU_USER		0x00000010
#  define KSU_SUPERVISOR	0x00000008
#  define KSU_KERNEL		0x00000000
#define ST0_UX			0x00000020
#define ST0_SX			0x00000040
R
Ralf Baechle 已提交
269
#define ST0_KX			0x00000080
L
Linus Torvalds 已提交
270 271 272 273 274 275 276 277 278 279 280 281 282
#define ST0_DE			0x00010000
#define ST0_CE			0x00020000

/*
 * Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate
 * cacheops in userspace.  This bit exists only on RM7000 and RM9000
 * processors.
 */
#define ST0_CO			0x08000000

/*
 * Bitfields in the R[23]000 cp0 status register.
 */
R
Ralf Baechle 已提交
283
#define ST0_IEC			0x00000001
L
Linus Torvalds 已提交
284 285 286 287 288 289 290 291 292 293 294 295 296
#define ST0_KUC			0x00000002
#define ST0_IEP			0x00000004
#define ST0_KUP			0x00000008
#define ST0_IEO			0x00000010
#define ST0_KUO			0x00000020
/* bits 6 & 7 are reserved on R[23]000 */
#define ST0_ISC			0x00010000
#define ST0_SWC			0x00020000
#define ST0_CM			0x00080000

/*
 * Bits specific to the R4640/R4650
 */
R
Ralf Baechle 已提交
297
#define ST0_UM			(_ULCAST_(1) <<	 4)
L
Linus Torvalds 已提交
298 299 300
#define ST0_IL			(_ULCAST_(1) << 23)
#define ST0_DL			(_ULCAST_(1) << 24)

301
/*
302
 * Enable the MIPS MDMX and DSP ASEs
303 304 305
 */
#define ST0_MX			0x01000000

L
Linus Torvalds 已提交
306 307 308 309
/*
 * Status register bits available in all MIPS CPUs.
 */
#define ST0_IM			0x0000ff00
R
Ralf Baechle 已提交
310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341
#define	 STATUSB_IP0		8
#define	 STATUSF_IP0		(_ULCAST_(1) <<	 8)
#define	 STATUSB_IP1		9
#define	 STATUSF_IP1		(_ULCAST_(1) <<	 9)
#define	 STATUSB_IP2		10
#define	 STATUSF_IP2		(_ULCAST_(1) << 10)
#define	 STATUSB_IP3		11
#define	 STATUSF_IP3		(_ULCAST_(1) << 11)
#define	 STATUSB_IP4		12
#define	 STATUSF_IP4		(_ULCAST_(1) << 12)
#define	 STATUSB_IP5		13
#define	 STATUSF_IP5		(_ULCAST_(1) << 13)
#define	 STATUSB_IP6		14
#define	 STATUSF_IP6		(_ULCAST_(1) << 14)
#define	 STATUSB_IP7		15
#define	 STATUSF_IP7		(_ULCAST_(1) << 15)
#define	 STATUSB_IP8		0
#define	 STATUSF_IP8		(_ULCAST_(1) <<	 0)
#define	 STATUSB_IP9		1
#define	 STATUSF_IP9		(_ULCAST_(1) <<	 1)
#define	 STATUSB_IP10		2
#define	 STATUSF_IP10		(_ULCAST_(1) <<	 2)
#define	 STATUSB_IP11		3
#define	 STATUSF_IP11		(_ULCAST_(1) <<	 3)
#define	 STATUSB_IP12		4
#define	 STATUSF_IP12		(_ULCAST_(1) <<	 4)
#define	 STATUSB_IP13		5
#define	 STATUSF_IP13		(_ULCAST_(1) <<	 5)
#define	 STATUSB_IP14		6
#define	 STATUSF_IP14		(_ULCAST_(1) <<	 6)
#define	 STATUSB_IP15		7
#define	 STATUSF_IP15		(_ULCAST_(1) <<	 7)
L
Linus Torvalds 已提交
342
#define ST0_CH			0x00040000
343
#define ST0_NMI			0x00080000
L
Linus Torvalds 已提交
344 345 346 347 348 349 350 351 352 353 354 355
#define ST0_SR			0x00100000
#define ST0_TS			0x00200000
#define ST0_BEV			0x00400000
#define ST0_RE			0x02000000
#define ST0_FR			0x04000000
#define ST0_CU			0xf0000000
#define ST0_CU0			0x10000000
#define ST0_CU1			0x20000000
#define ST0_CU2			0x40000000
#define ST0_CU3			0x80000000
#define ST0_XX			0x80000000	/* MIPS IV naming */

356 357 358
/*
 * Bitfields and bit numbers in the coprocessor 0 IntCtl register. (MIPSR2)
 */
359 360
#define INTCTLB_IPFDC		23
#define INTCTLF_IPFDC		(_ULCAST_(7) << INTCTLB_IPFDC)
361 362 363 364 365
#define INTCTLB_IPPCI		26
#define INTCTLF_IPPCI		(_ULCAST_(7) << INTCTLB_IPPCI)
#define INTCTLB_IPTI		29
#define INTCTLF_IPTI		(_ULCAST_(7) << INTCTLB_IPTI)

L
Linus Torvalds 已提交
366 367 368 369 370
/*
 * Bitfields and bit numbers in the coprocessor 0 cause register.
 *
 * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
 */
371 372 373 374
#define CAUSEB_EXCCODE		2
#define CAUSEF_EXCCODE		(_ULCAST_(31)  <<  2)
#define CAUSEB_IP		8
#define CAUSEF_IP		(_ULCAST_(255) <<  8)
R
Ralf Baechle 已提交
375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390
#define	 CAUSEB_IP0		8
#define	 CAUSEF_IP0		(_ULCAST_(1)   <<  8)
#define	 CAUSEB_IP1		9
#define	 CAUSEF_IP1		(_ULCAST_(1)   <<  9)
#define	 CAUSEB_IP2		10
#define	 CAUSEF_IP2		(_ULCAST_(1)   << 10)
#define	 CAUSEB_IP3		11
#define	 CAUSEF_IP3		(_ULCAST_(1)   << 11)
#define	 CAUSEB_IP4		12
#define	 CAUSEF_IP4		(_ULCAST_(1)   << 12)
#define	 CAUSEB_IP5		13
#define	 CAUSEF_IP5		(_ULCAST_(1)   << 13)
#define	 CAUSEB_IP6		14
#define	 CAUSEF_IP6		(_ULCAST_(1)   << 14)
#define	 CAUSEB_IP7		15
#define	 CAUSEF_IP7		(_ULCAST_(1)   << 15)
391 392 393 394 395 396
#define CAUSEB_FDCI		21
#define CAUSEF_FDCI		(_ULCAST_(1)   << 21)
#define CAUSEB_IV		23
#define CAUSEF_IV		(_ULCAST_(1)   << 23)
#define CAUSEB_PCI		26
#define CAUSEF_PCI		(_ULCAST_(1)   << 26)
397 398
#define CAUSEB_DC		27
#define CAUSEF_DC		(_ULCAST_(1)   << 27)
399 400 401 402 403 404
#define CAUSEB_CE		28
#define CAUSEF_CE		(_ULCAST_(3)   << 28)
#define CAUSEB_TI		30
#define CAUSEF_TI		(_ULCAST_(1)   << 30)
#define CAUSEB_BD		31
#define CAUSEF_BD		(_ULCAST_(1)   << 31)
L
Linus Torvalds 已提交
405

406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424
/*
 * Cause.ExcCode trap codes.
 */
#define EXCCODE_INT		0	/* Interrupt pending */
#define EXCCODE_MOD		1	/* TLB modified fault */
#define EXCCODE_TLBL		2	/* TLB miss on load or ifetch */
#define EXCCODE_TLBS		3	/* TLB miss on a store */
#define EXCCODE_ADEL		4	/* Address error on a load or ifetch */
#define EXCCODE_ADES		5	/* Address error on a store */
#define EXCCODE_IBE		6	/* Bus error on an ifetch */
#define EXCCODE_DBE		7	/* Bus error on a load or store */
#define EXCCODE_SYS		8	/* System call */
#define EXCCODE_BP		9	/* Breakpoint */
#define EXCCODE_RI		10	/* Reserved instruction exception */
#define EXCCODE_CPU		11	/* Coprocessor unusable */
#define EXCCODE_OV		12	/* Arithmetic overflow */
#define EXCCODE_TR		13	/* Trap instruction */
#define EXCCODE_MSAFPE		14	/* MSA floating point exception */
#define EXCCODE_FPE		15	/* Floating point exception */
J
James Hogan 已提交
425 426
#define EXCCODE_TLBRI		19	/* TLB Read-Inhibit exception */
#define EXCCODE_TLBXI		20	/* TLB Execution-Inhibit exception */
427
#define EXCCODE_MSADIS		21	/* MSA disabled exception */
J
James Hogan 已提交
428
#define EXCCODE_MDMX		22	/* MDMX unusable exception */
429
#define EXCCODE_WATCH		23	/* Watch address reference */
J
James Hogan 已提交
430 431 432 433 434 435 436
#define EXCCODE_MCHECK		24	/* Machine check */
#define EXCCODE_THREAD		25	/* Thread exceptions (MT) */
#define EXCCODE_DSPDIS		26	/* DSP disabled exception */
#define EXCCODE_GE		27	/* Virtualized guest exception (VZ) */

/* Implementation specific trap codes used by MIPS cores */
#define MIPS_EXCCODE_TLBPAR	16	/* TLB parity error exception */
437

L
Linus Torvalds 已提交
438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453
/*
 * Bits in the coprocessor 0 config register.
 */
/* Generic bits.  */
#define CONF_CM_CACHABLE_NO_WA		0
#define CONF_CM_CACHABLE_WA		1
#define CONF_CM_UNCACHED		2
#define CONF_CM_CACHABLE_NONCOHERENT	3
#define CONF_CM_CACHABLE_CE		4
#define CONF_CM_CACHABLE_COW		5
#define CONF_CM_CACHABLE_CUW		6
#define CONF_CM_CACHABLE_ACCELERATED	7
#define CONF_CM_CMASK			7
#define CONF_BE			(_ULCAST_(1) << 15)

/* Bits common to various processors.  */
R
Ralf Baechle 已提交
454 455 456 457 458
#define CONF_CU			(_ULCAST_(1) <<	 3)
#define CONF_DB			(_ULCAST_(1) <<	 4)
#define CONF_IB			(_ULCAST_(1) <<	 5)
#define CONF_DC			(_ULCAST_(7) <<	 6)
#define CONF_IC			(_ULCAST_(7) <<	 9)
L
Linus Torvalds 已提交
459 460 461 462 463 464 465 466 467
#define CONF_EB			(_ULCAST_(1) << 13)
#define CONF_EM			(_ULCAST_(1) << 14)
#define CONF_SM			(_ULCAST_(1) << 16)
#define CONF_SC			(_ULCAST_(1) << 17)
#define CONF_EW			(_ULCAST_(3) << 18)
#define CONF_EP			(_ULCAST_(15)<< 24)
#define CONF_EC			(_ULCAST_(7) << 28)
#define CONF_CM			(_ULCAST_(1) << 31)

R
Ralf Baechle 已提交
468
/* Bits specific to the R4xx0.	*/
L
Linus Torvalds 已提交
469 470
#define R4K_CONF_SW		(_ULCAST_(1) << 20)
#define R4K_CONF_SS		(_ULCAST_(1) << 21)
R
Ralf Baechle 已提交
471
#define R4K_CONF_SB		(_ULCAST_(3) << 22)
L
Linus Torvalds 已提交
472

R
Ralf Baechle 已提交
473
/* Bits specific to the R5000.	*/
L
Linus Torvalds 已提交
474 475 476
#define R5K_CONF_SE		(_ULCAST_(1) << 12)
#define R5K_CONF_SS		(_ULCAST_(3) << 20)

R
Ralf Baechle 已提交
477 478
/* Bits specific to the RM7000.	 */
#define RM7K_CONF_SE		(_ULCAST_(1) <<	 3)
479 480 481 482 483
#define RM7K_CONF_TE		(_ULCAST_(1) << 12)
#define RM7K_CONF_CLK		(_ULCAST_(1) << 16)
#define RM7K_CONF_TC		(_ULCAST_(1) << 17)
#define RM7K_CONF_SI		(_ULCAST_(3) << 20)
#define RM7K_CONF_SC		(_ULCAST_(1) << 31)
484

R
Ralf Baechle 已提交
485 486 487 488 489 490
/* Bits specific to the R10000.	 */
#define R10K_CONF_DN		(_ULCAST_(3) <<	 3)
#define R10K_CONF_CT		(_ULCAST_(1) <<	 5)
#define R10K_CONF_PE		(_ULCAST_(1) <<	 6)
#define R10K_CONF_PM		(_ULCAST_(3) <<	 7)
#define R10K_CONF_EC		(_ULCAST_(15)<<	 9)
L
Linus Torvalds 已提交
491 492 493 494 495 496 497
#define R10K_CONF_SB		(_ULCAST_(1) << 13)
#define R10K_CONF_SK		(_ULCAST_(1) << 14)
#define R10K_CONF_SS		(_ULCAST_(7) << 16)
#define R10K_CONF_SC		(_ULCAST_(7) << 19)
#define R10K_CONF_DC		(_ULCAST_(7) << 26)
#define R10K_CONF_IC		(_ULCAST_(7) << 29)

R
Ralf Baechle 已提交
498
/* Bits specific to the VR41xx.	 */
L
Linus Torvalds 已提交
499
#define VR41_CONF_CS		(_ULCAST_(1) << 12)
500
#define VR41_CONF_P4K		(_ULCAST_(1) << 13)
501
#define VR41_CONF_BP		(_ULCAST_(1) << 16)
L
Linus Torvalds 已提交
502 503 504
#define VR41_CONF_M16		(_ULCAST_(1) << 20)
#define VR41_CONF_AD		(_ULCAST_(1) << 23)

R
Ralf Baechle 已提交
505
/* Bits specific to the R30xx.	*/
L
Linus Torvalds 已提交
506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521
#define R30XX_CONF_FDM		(_ULCAST_(1) << 19)
#define R30XX_CONF_REV		(_ULCAST_(1) << 22)
#define R30XX_CONF_AC		(_ULCAST_(1) << 23)
#define R30XX_CONF_RF		(_ULCAST_(1) << 24)
#define R30XX_CONF_HALT		(_ULCAST_(1) << 25)
#define R30XX_CONF_FPINT	(_ULCAST_(7) << 26)
#define R30XX_CONF_DBR		(_ULCAST_(1) << 29)
#define R30XX_CONF_SB		(_ULCAST_(1) << 30)
#define R30XX_CONF_LOCK		(_ULCAST_(1) << 31)

/* Bits specific to the TX49.  */
#define TX49_CONF_DC		(_ULCAST_(1) << 16)
#define TX49_CONF_IC		(_ULCAST_(1) << 17)  /* conflict with CONF_SC */
#define TX49_CONF_HALT		(_ULCAST_(1) << 18)
#define TX49_CONF_CWFON		(_ULCAST_(1) << 27)

R
Ralf Baechle 已提交
522 523
/* Bits specific to the MIPS32/64 PRA.	*/
#define MIPS_CONF_MT		(_ULCAST_(7) <<	 7)
524 525
#define MIPS_CONF_MT_TLB	(_ULCAST_(1) <<  7)
#define MIPS_CONF_MT_FTLB	(_ULCAST_(4) <<  7)
L
Linus Torvalds 已提交
526 527 528 529
#define MIPS_CONF_AR		(_ULCAST_(7) << 10)
#define MIPS_CONF_AT		(_ULCAST_(3) << 13)
#define MIPS_CONF_M		(_ULCAST_(1) << 31)

530 531 532
/*
 * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above.
 */
R
Ralf Baechle 已提交
533 534 535 536 537 538 539
#define MIPS_CONF1_FP		(_ULCAST_(1) <<	 0)
#define MIPS_CONF1_EP		(_ULCAST_(1) <<	 1)
#define MIPS_CONF1_CA		(_ULCAST_(1) <<	 2)
#define MIPS_CONF1_WR		(_ULCAST_(1) <<	 3)
#define MIPS_CONF1_PC		(_ULCAST_(1) <<	 4)
#define MIPS_CONF1_MD		(_ULCAST_(1) <<	 5)
#define MIPS_CONF1_C2		(_ULCAST_(1) <<	 6)
540 541
#define MIPS_CONF1_DA_SHF	7
#define MIPS_CONF1_DA_SZ	3
R
Ralf Baechle 已提交
542
#define MIPS_CONF1_DA		(_ULCAST_(7) <<	 7)
543 544
#define MIPS_CONF1_DL_SHF	10
#define MIPS_CONF1_DL_SZ	3
545
#define MIPS_CONF1_DL		(_ULCAST_(7) << 10)
546 547
#define MIPS_CONF1_DS_SHF	13
#define MIPS_CONF1_DS_SZ	3
548
#define MIPS_CONF1_DS		(_ULCAST_(7) << 13)
549 550
#define MIPS_CONF1_IA_SHF	16
#define MIPS_CONF1_IA_SZ	3
551
#define MIPS_CONF1_IA		(_ULCAST_(7) << 16)
552 553
#define MIPS_CONF1_IL_SHF	19
#define MIPS_CONF1_IL_SZ	3
554
#define MIPS_CONF1_IL		(_ULCAST_(7) << 19)
555 556
#define MIPS_CONF1_IS_SHF	22
#define MIPS_CONF1_IS_SZ	3
557
#define MIPS_CONF1_IS		(_ULCAST_(7) << 22)
558 559 560
#define MIPS_CONF1_TLBS_SHIFT   (25)
#define MIPS_CONF1_TLBS_SIZE    (6)
#define MIPS_CONF1_TLBS         (_ULCAST_(63) << MIPS_CONF1_TLBS_SHIFT)
561

R
Ralf Baechle 已提交
562 563 564
#define MIPS_CONF2_SA		(_ULCAST_(15)<<	 0)
#define MIPS_CONF2_SL		(_ULCAST_(15)<<	 4)
#define MIPS_CONF2_SS		(_ULCAST_(15)<<	 8)
565 566 567 568 569 570
#define MIPS_CONF2_SU		(_ULCAST_(15)<< 12)
#define MIPS_CONF2_TA		(_ULCAST_(15)<< 16)
#define MIPS_CONF2_TL		(_ULCAST_(15)<< 20)
#define MIPS_CONF2_TS		(_ULCAST_(15)<< 24)
#define MIPS_CONF2_TU		(_ULCAST_(7) << 28)

R
Ralf Baechle 已提交
571 572 573
#define MIPS_CONF3_TL		(_ULCAST_(1) <<	 0)
#define MIPS_CONF3_SM		(_ULCAST_(1) <<	 1)
#define MIPS_CONF3_MT		(_ULCAST_(1) <<	 2)
574
#define MIPS_CONF3_CDMM		(_ULCAST_(1) <<	 3)
R
Ralf Baechle 已提交
575 576 577 578
#define MIPS_CONF3_SP		(_ULCAST_(1) <<	 4)
#define MIPS_CONF3_VINT		(_ULCAST_(1) <<	 5)
#define MIPS_CONF3_VEIC		(_ULCAST_(1) <<	 6)
#define MIPS_CONF3_LPA		(_ULCAST_(1) <<	 7)
579 580
#define MIPS_CONF3_ITL		(_ULCAST_(1) <<	 8)
#define MIPS_CONF3_CTXTC	(_ULCAST_(1) <<	 9)
581
#define MIPS_CONF3_DSP		(_ULCAST_(1) << 10)
582
#define MIPS_CONF3_DSP2P	(_ULCAST_(1) << 11)
583
#define MIPS_CONF3_RXI		(_ULCAST_(1) << 12)
584
#define MIPS_CONF3_ULRI		(_ULCAST_(1) << 13)
585
#define MIPS_CONF3_ISA		(_ULCAST_(3) << 14)
586
#define MIPS_CONF3_ISA_OE	(_ULCAST_(1) << 16)
587 588 589
#define MIPS_CONF3_MCU		(_ULCAST_(1) << 17)
#define MIPS_CONF3_MMAR		(_ULCAST_(7) << 18)
#define MIPS_CONF3_IPLW		(_ULCAST_(3) << 21)
590
#define MIPS_CONF3_VZ		(_ULCAST_(1) << 23)
591 592 593 594 595 596 597 598 599
#define MIPS_CONF3_PW		(_ULCAST_(1) << 24)
#define MIPS_CONF3_SC		(_ULCAST_(1) << 25)
#define MIPS_CONF3_BI		(_ULCAST_(1) << 26)
#define MIPS_CONF3_BP		(_ULCAST_(1) << 27)
#define MIPS_CONF3_MSA		(_ULCAST_(1) << 28)
#define MIPS_CONF3_CMGCR	(_ULCAST_(1) << 29)
#define MIPS_CONF3_BPG		(_ULCAST_(1) << 30)

#define MIPS_CONF4_MMUSIZEEXT_SHIFT	(0)
600
#define MIPS_CONF4_MMUSIZEEXT	(_ULCAST_(255) << 0)
601 602 603 604 605 606 607 608 609
#define MIPS_CONF4_FTLBSETS_SHIFT	(0)
#define MIPS_CONF4_FTLBSETS	(_ULCAST_(15) << MIPS_CONF4_FTLBSETS_SHIFT)
#define MIPS_CONF4_FTLBWAYS_SHIFT	(4)
#define MIPS_CONF4_FTLBWAYS	(_ULCAST_(15) << MIPS_CONF4_FTLBWAYS_SHIFT)
#define MIPS_CONF4_FTLBPAGESIZE_SHIFT	(8)
/* bits 10:8 in FTLB-only configurations */
#define MIPS_CONF4_FTLBPAGESIZE (_ULCAST_(7) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
/* bits 12:8 in VTLB-FTLB only configurations */
#define MIPS_CONF4_VFTLBPAGESIZE (_ULCAST_(31) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
610 611
#define MIPS_CONF4_MMUEXTDEF	(_ULCAST_(3) << 14)
#define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14)
612 613 614 615 616 617 618 619
#define MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT	(_ULCAST_(2) << 14)
#define MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT	(_ULCAST_(3) << 14)
#define MIPS_CONF4_KSCREXIST	(_ULCAST_(255) << 16)
#define MIPS_CONF4_VTLBSIZEEXT_SHIFT	(24)
#define MIPS_CONF4_VTLBSIZEEXT	(_ULCAST_(15) << MIPS_CONF4_VTLBSIZEEXT_SHIFT)
#define MIPS_CONF4_AE		(_ULCAST_(1) << 28)
#define MIPS_CONF4_IE		(_ULCAST_(3) << 29)
#define MIPS_CONF4_TLBINV	(_ULCAST_(2) << 29)
620

621 622
#define MIPS_CONF5_NF		(_ULCAST_(1) << 0)
#define MIPS_CONF5_UFR		(_ULCAST_(1) << 2)
623
#define MIPS_CONF5_MRP		(_ULCAST_(1) << 3)
624
#define MIPS_CONF5_LLB		(_ULCAST_(1) << 4)
625
#define MIPS_CONF5_MVH		(_ULCAST_(1) << 5)
626
#define MIPS_CONF5_VP		(_ULCAST_(1) << 7)
627 628
#define MIPS_CONF5_FRE		(_ULCAST_(1) << 8)
#define MIPS_CONF5_UFE		(_ULCAST_(1) << 9)
629 630 631 632 633
#define MIPS_CONF5_MSAEN	(_ULCAST_(1) << 27)
#define MIPS_CONF5_EVA		(_ULCAST_(1) << 28)
#define MIPS_CONF5_CV		(_ULCAST_(1) << 29)
#define MIPS_CONF5_K		(_ULCAST_(1) << 30)

634
#define MIPS_CONF6_SYND		(_ULCAST_(1) << 13)
L
Leonid Yegoshin 已提交
635 636
/* proAptiv FTLB on/off bit */
#define MIPS_CONF6_FTLBEN	(_ULCAST_(1) << 15)
637 638
/* FTLB probability bits */
#define MIPS_CONF6_FTLBP_SHIFT	(16)
639

640 641
#define MIPS_CONF7_WII		(_ULCAST_(1) << 31)

M
Marc St-Jean 已提交
642 643
#define MIPS_CONF7_RPS		(_ULCAST_(1) << 2)

644 645
#define MIPS_CONF7_IAR		(_ULCAST_(1) << 10)
#define MIPS_CONF7_AR		(_ULCAST_(1) << 16)
646 647
/* FTLB probability bits for R6 */
#define MIPS_CONF7_FTLBP_SHIFT	(18)
648

649 650 651 652 653 654
/* MAAR bit definitions */
#define MIPS_MAAR_ADDR		((BIT_ULL(BITS_PER_LONG - 12) - 1) << 12)
#define MIPS_MAAR_ADDR_SHIFT	12
#define MIPS_MAAR_S		(_ULCAST_(1) << 1)
#define MIPS_MAAR_V		(_ULCAST_(1) << 0)

655 656 657 658
/* CMGCRBase bit definitions */
#define MIPS_CMGCRB_BASE	11
#define MIPS_CMGCRF_BASE	(~_ULCAST_((1 << MIPS_CMGCRB_BASE) - 1))

659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678
/*
 * Bits in the MIPS32 Memory Segmentation registers.
 */
#define MIPS_SEGCFG_PA_SHIFT	9
#define MIPS_SEGCFG_PA		(_ULCAST_(127) << MIPS_SEGCFG_PA_SHIFT)
#define MIPS_SEGCFG_AM_SHIFT	4
#define MIPS_SEGCFG_AM		(_ULCAST_(7) << MIPS_SEGCFG_AM_SHIFT)
#define MIPS_SEGCFG_EU_SHIFT	3
#define MIPS_SEGCFG_EU		(_ULCAST_(1) << MIPS_SEGCFG_EU_SHIFT)
#define MIPS_SEGCFG_C_SHIFT	0
#define MIPS_SEGCFG_C		(_ULCAST_(7) << MIPS_SEGCFG_C_SHIFT)

#define MIPS_SEGCFG_UUSK	_ULCAST_(7)
#define MIPS_SEGCFG_USK		_ULCAST_(5)
#define MIPS_SEGCFG_MUSUK	_ULCAST_(4)
#define MIPS_SEGCFG_MUSK	_ULCAST_(3)
#define MIPS_SEGCFG_MSK		_ULCAST_(2)
#define MIPS_SEGCFG_MK		_ULCAST_(1)
#define MIPS_SEGCFG_UK		_ULCAST_(0)

679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709
#define MIPS_PWFIELD_GDI_SHIFT	24
#define MIPS_PWFIELD_GDI_MASK	0x3f000000
#define MIPS_PWFIELD_UDI_SHIFT	18
#define MIPS_PWFIELD_UDI_MASK	0x00fc0000
#define MIPS_PWFIELD_MDI_SHIFT	12
#define MIPS_PWFIELD_MDI_MASK	0x0003f000
#define MIPS_PWFIELD_PTI_SHIFT	6
#define MIPS_PWFIELD_PTI_MASK	0x00000fc0
#define MIPS_PWFIELD_PTEI_SHIFT	0
#define MIPS_PWFIELD_PTEI_MASK	0x0000003f

#define MIPS_PWSIZE_GDW_SHIFT	24
#define MIPS_PWSIZE_GDW_MASK	0x3f000000
#define MIPS_PWSIZE_UDW_SHIFT	18
#define MIPS_PWSIZE_UDW_MASK	0x00fc0000
#define MIPS_PWSIZE_MDW_SHIFT	12
#define MIPS_PWSIZE_MDW_MASK	0x0003f000
#define MIPS_PWSIZE_PTW_SHIFT	6
#define MIPS_PWSIZE_PTW_MASK	0x00000fc0
#define MIPS_PWSIZE_PTEW_SHIFT	0
#define MIPS_PWSIZE_PTEW_MASK	0x0000003f

#define MIPS_PWCTL_PWEN_SHIFT	31
#define MIPS_PWCTL_PWEN_MASK	0x80000000
#define MIPS_PWCTL_DPH_SHIFT	7
#define MIPS_PWCTL_DPH_MASK	0x00000080
#define MIPS_PWCTL_HUGEPG_SHIFT	6
#define MIPS_PWCTL_HUGEPG_MASK	0x00000060
#define MIPS_PWCTL_PSN_SHIFT	0
#define MIPS_PWCTL_PSN_MASK	0x0000003f

710 711 712 713 714 715 716 717
/* CDMMBase register bit definitions */
#define MIPS_CDMMBASE_SIZE_SHIFT 0
#define MIPS_CDMMBASE_SIZE	(_ULCAST_(511) << MIPS_CDMMBASE_SIZE_SHIFT)
#define MIPS_CDMMBASE_CI	(_ULCAST_(1) << 9)
#define MIPS_CDMMBASE_EN	(_ULCAST_(1) << 10)
#define MIPS_CDMMBASE_ADDR_SHIFT 11
#define MIPS_CDMMBASE_ADDR_START 15

718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750
/*
 * Bitfields in the TX39 family CP0 Configuration Register 3
 */
#define TX39_CONF_ICS_SHIFT	19
#define TX39_CONF_ICS_MASK	0x00380000
#define TX39_CONF_ICS_1KB	0x00000000
#define TX39_CONF_ICS_2KB	0x00080000
#define TX39_CONF_ICS_4KB	0x00100000
#define TX39_CONF_ICS_8KB	0x00180000
#define TX39_CONF_ICS_16KB	0x00200000

#define TX39_CONF_DCS_SHIFT	16
#define TX39_CONF_DCS_MASK	0x00070000
#define TX39_CONF_DCS_1KB	0x00000000
#define TX39_CONF_DCS_2KB	0x00010000
#define TX39_CONF_DCS_4KB	0x00020000
#define TX39_CONF_DCS_8KB	0x00030000
#define TX39_CONF_DCS_16KB	0x00040000

#define TX39_CONF_CWFON		0x00004000
#define TX39_CONF_WBON		0x00002000
#define TX39_CONF_RF_SHIFT	10
#define TX39_CONF_RF_MASK	0x00000c00
#define TX39_CONF_DOZE		0x00000200
#define TX39_CONF_HALT		0x00000100
#define TX39_CONF_LOCK		0x00000080
#define TX39_CONF_ICE		0x00000020
#define TX39_CONF_DCE		0x00000010
#define TX39_CONF_IRSIZE_SHIFT	2
#define TX39_CONF_IRSIZE_MASK	0x0000000c
#define TX39_CONF_DRSIZE_SHIFT	0
#define TX39_CONF_DRSIZE_MASK	0x00000003

751 752 753 754 755 756 757 758 759
/*
 * Interesting Bits in the R10K CP0 Branch Diagnostic Register
 */
/* Disable Branch Target Address Cache */
#define R10K_DIAG_D_BTAC	(_ULCAST_(1) << 27)
/* Enable Branch Prediction Global History */
#define R10K_DIAG_E_GHIST	(_ULCAST_(1) << 26)
/* Disable Branch Return Cache */
#define R10K_DIAG_D_BRC		(_ULCAST_(1) << 22)
760 761 762 763

/*
 * Coprocessor 1 (FPU) register names
 */
764 765 766 767 768 769 770
#define CP1_REVISION	$0
#define CP1_UFR		$1
#define CP1_UNFR	$4
#define CP1_FCCR	$25
#define CP1_FEXR	$26
#define CP1_FENR	$28
#define CP1_STATUS	$31
771 772 773 774 775 776 777 778 779 780 781 782


/*
 * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
 */
#define MIPS_FPIR_S		(_ULCAST_(1) << 16)
#define MIPS_FPIR_D		(_ULCAST_(1) << 17)
#define MIPS_FPIR_PS		(_ULCAST_(1) << 18)
#define MIPS_FPIR_3D		(_ULCAST_(1) << 19)
#define MIPS_FPIR_W		(_ULCAST_(1) << 20)
#define MIPS_FPIR_L		(_ULCAST_(1) << 21)
#define MIPS_FPIR_F64		(_ULCAST_(1) << 22)
783 784
#define MIPS_FPIR_HAS2008	(_ULCAST_(1) << 23)
#define MIPS_FPIR_UFRP		(_ULCAST_(1) << 28)
785 786
#define MIPS_FPIR_FREP		(_ULCAST_(1) << 29)

787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814
/*
 * Bits in the MIPS32/64 coprocessor 1 (FPU) condition codes register.
 */
#define MIPS_FCCR_CONDX_S	0
#define MIPS_FCCR_CONDX		(_ULCAST_(255) << MIPS_FCCR_CONDX_S)
#define MIPS_FCCR_COND0_S	0
#define MIPS_FCCR_COND0		(_ULCAST_(1) << MIPS_FCCR_COND0_S)
#define MIPS_FCCR_COND1_S	1
#define MIPS_FCCR_COND1		(_ULCAST_(1) << MIPS_FCCR_COND1_S)
#define MIPS_FCCR_COND2_S	2
#define MIPS_FCCR_COND2		(_ULCAST_(1) << MIPS_FCCR_COND2_S)
#define MIPS_FCCR_COND3_S	3
#define MIPS_FCCR_COND3		(_ULCAST_(1) << MIPS_FCCR_COND3_S)
#define MIPS_FCCR_COND4_S	4
#define MIPS_FCCR_COND4		(_ULCAST_(1) << MIPS_FCCR_COND4_S)
#define MIPS_FCCR_COND5_S	5
#define MIPS_FCCR_COND5		(_ULCAST_(1) << MIPS_FCCR_COND5_S)
#define MIPS_FCCR_COND6_S	6
#define MIPS_FCCR_COND6		(_ULCAST_(1) << MIPS_FCCR_COND6_S)
#define MIPS_FCCR_COND7_S	7
#define MIPS_FCCR_COND7		(_ULCAST_(1) << MIPS_FCCR_COND7_S)

/*
 * Bits in the MIPS32/64 coprocessor 1 (FPU) enables register.
 */
#define MIPS_FENR_FS_S		2
#define MIPS_FENR_FS		(_ULCAST_(1) << MIPS_FENR_FS_S)

815 816 817
/*
 * FPU Status Register Values
 */
818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839
#define FPU_CSR_COND_S	23					/* $fcc0 */
#define FPU_CSR_COND	(_ULCAST_(1) << FPU_CSR_COND_S)

#define FPU_CSR_FS_S	24		/* flush denormalised results to 0 */
#define FPU_CSR_FS	(_ULCAST_(1) << FPU_CSR_FS_S)

#define FPU_CSR_CONDX_S	25					/* $fcc[7:1] */
#define FPU_CSR_CONDX	(_ULCAST_(127) << FPU_CSR_CONDX_S)
#define FPU_CSR_COND1_S	25					/* $fcc1 */
#define FPU_CSR_COND1	(_ULCAST_(1) << FPU_CSR_COND1_S)
#define FPU_CSR_COND2_S	26					/* $fcc2 */
#define FPU_CSR_COND2	(_ULCAST_(1) << FPU_CSR_COND2_S)
#define FPU_CSR_COND3_S	27					/* $fcc3 */
#define FPU_CSR_COND3	(_ULCAST_(1) << FPU_CSR_COND3_S)
#define FPU_CSR_COND4_S	28					/* $fcc4 */
#define FPU_CSR_COND4	(_ULCAST_(1) << FPU_CSR_COND4_S)
#define FPU_CSR_COND5_S	29					/* $fcc5 */
#define FPU_CSR_COND5	(_ULCAST_(1) << FPU_CSR_COND5_S)
#define FPU_CSR_COND6_S	30					/* $fcc6 */
#define FPU_CSR_COND6	(_ULCAST_(1) << FPU_CSR_COND6_S)
#define FPU_CSR_COND7_S	31					/* $fcc7 */
#define FPU_CSR_COND7	(_ULCAST_(1) << FPU_CSR_COND7_S)
840 841

/*
842
 * Bits 22:20 of the FPU Status Register will be read as 0,
843 844
 * and should be written as zero.
 */
845 846 847 848
#define FPU_CSR_RSVD	(_ULCAST_(7) << 20)

#define FPU_CSR_ABS2008	(_ULCAST_(1) << 19)
#define FPU_CSR_NAN2008	(_ULCAST_(1) << 18)
849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884

/*
 * X the exception cause indicator
 * E the exception enable
 * S the sticky/flag bit
*/
#define FPU_CSR_ALL_X	0x0003f000
#define FPU_CSR_UNI_X	0x00020000
#define FPU_CSR_INV_X	0x00010000
#define FPU_CSR_DIV_X	0x00008000
#define FPU_CSR_OVF_X	0x00004000
#define FPU_CSR_UDF_X	0x00002000
#define FPU_CSR_INE_X	0x00001000

#define FPU_CSR_ALL_E	0x00000f80
#define FPU_CSR_INV_E	0x00000800
#define FPU_CSR_DIV_E	0x00000400
#define FPU_CSR_OVF_E	0x00000200
#define FPU_CSR_UDF_E	0x00000100
#define FPU_CSR_INE_E	0x00000080

#define FPU_CSR_ALL_S	0x0000007c
#define FPU_CSR_INV_S	0x00000040
#define FPU_CSR_DIV_S	0x00000020
#define FPU_CSR_OVF_S	0x00000010
#define FPU_CSR_UDF_S	0x00000008
#define FPU_CSR_INE_S	0x00000004

/* Bits 0 and 1 of FPU Status Register specify the rounding mode */
#define FPU_CSR_RM	0x00000003
#define FPU_CSR_RN	0x0	/* nearest */
#define FPU_CSR_RZ	0x1	/* towards zero */
#define FPU_CSR_RU	0x2	/* towards +Infinity */
#define FPU_CSR_RD	0x3	/* towards -Infinity */


L
Linus Torvalds 已提交
885 886
#ifndef __ASSEMBLY__

887
/*
888
 * Macros for handling the ISA mode bit for MIPS16 and microMIPS.
889
 */
890 891
#if defined(CONFIG_SYS_SUPPORTS_MIPS16) || \
    defined(CONFIG_SYS_SUPPORTS_MICROMIPS)
892 893 894
#define get_isa16_mode(x)		((x) & 0x1)
#define msk_isa16_mode(x)		((x) & ~0x1)
#define set_isa16_mode(x)		do { (x) |= 0x1; } while(0)
895 896 897 898 899
#else
#define get_isa16_mode(x)		0
#define msk_isa16_mode(x)		(x)
#define set_isa16_mode(x)		do { } while(0)
#endif
900 901 902 903 904 905 906 907 908 909 910 911

/*
 * microMIPS instructions can be 16-bit or 32-bit in length. This
 * returns a 1 if the instruction is 16-bit and a 0 if 32-bit.
 */
static inline int mm_insn_16bit(u16 insn)
{
	u16 opcode = (insn >> 10) & 0x7;

	return (opcode >= 1 && opcode <= 3) ? 1 : 0;
}

912 913 914 915 916 917 918 919 920 921 922 923 924
/*
 * TLB Invalidate Flush
 */
static inline void tlbinvf(void)
{
	__asm__ __volatile__(
		".set push\n\t"
		".set noreorder\n\t"
		".word 0x42000004\n\t" /* tlbinvf */
		".set pop");
}


L
Linus Torvalds 已提交
925
/*
R
Ralf Baechle 已提交
926
 * Functions to access the R10000 performance counters.	 These are basically
L
Linus Torvalds 已提交
927 928 929 930 931 932 933 934 935 936
 * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit
 * performance counter number encoded into bits 1 ... 5 of the instruction.
 * Only performance counters 0 to 1 actually exist, so for a non-R10000 aware
 * disassembler these will look like an access to sel 0 or 1.
 */
#define read_r10k_perf_cntr(counter)				\
({								\
	unsigned int __res;					\
	__asm__ __volatile__(					\
	"mfpc\t%0, %1"						\
R
Ralf Baechle 已提交
937
	: "=r" (__res)						\
L
Linus Torvalds 已提交
938 939
	: "i" (counter));					\
								\
R
Ralf Baechle 已提交
940
	__res;							\
L
Linus Torvalds 已提交
941 942
})

R
Ralf Baechle 已提交
943
#define write_r10k_perf_cntr(counter,val)			\
L
Linus Torvalds 已提交
944 945 946 947 948 949 950 951 952 953 954 955
do {								\
	__asm__ __volatile__(					\
	"mtpc\t%0, %1"						\
	:							\
	: "r" (val), "i" (counter));				\
} while (0)

#define read_r10k_perf_event(counter)				\
({								\
	unsigned int __res;					\
	__asm__ __volatile__(					\
	"mfps\t%0, %1"						\
R
Ralf Baechle 已提交
956
	: "=r" (__res)						\
L
Linus Torvalds 已提交
957 958
	: "i" (counter));					\
								\
R
Ralf Baechle 已提交
959
	__res;							\
L
Linus Torvalds 已提交
960 961
})

R
Ralf Baechle 已提交
962
#define write_r10k_perf_cntl(counter,val)			\
L
Linus Torvalds 已提交
963 964 965 966 967 968 969 970 971 972 973 974 975
do {								\
	__asm__ __volatile__(					\
	"mtps\t%0, %1"						\
	:							\
	: "r" (val), "i" (counter));				\
} while (0)


/*
 * Macros to access the system control coprocessor
 */

#define __read_32bit_c0_register(source, sel)				\
976
({ unsigned int __res;							\
L
Linus Torvalds 已提交
977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013
	if (sel == 0)							\
		__asm__ __volatile__(					\
			"mfc0\t%0, " #source "\n\t"			\
			: "=r" (__res));				\
	else								\
		__asm__ __volatile__(					\
			".set\tmips32\n\t"				\
			"mfc0\t%0, " #source ", " #sel "\n\t"		\
			".set\tmips0\n\t"				\
			: "=r" (__res));				\
	__res;								\
})

#define __read_64bit_c0_register(source, sel)				\
({ unsigned long long __res;						\
	if (sizeof(unsigned long) == 4)					\
		__res = __read_64bit_c0_split(source, sel);		\
	else if (sel == 0)						\
		__asm__ __volatile__(					\
			".set\tmips3\n\t"				\
			"dmfc0\t%0, " #source "\n\t"			\
			".set\tmips0"					\
			: "=r" (__res));				\
	else								\
		__asm__ __volatile__(					\
			".set\tmips64\n\t"				\
			"dmfc0\t%0, " #source ", " #sel "\n\t"		\
			".set\tmips0"					\
			: "=r" (__res));				\
	__res;								\
})

#define __write_32bit_c0_register(register, sel, value)			\
do {									\
	if (sel == 0)							\
		__asm__ __volatile__(					\
			"mtc0\t%z0, " #register "\n\t"			\
R
Ralf Baechle 已提交
1014
			: : "Jr" ((unsigned int)(value)));		\
L
Linus Torvalds 已提交
1015 1016 1017 1018 1019
	else								\
		__asm__ __volatile__(					\
			".set\tmips32\n\t"				\
			"mtc0\t%z0, " #register ", " #sel "\n\t"	\
			".set\tmips0"					\
R
Ralf Baechle 已提交
1020
			: : "Jr" ((unsigned int)(value)));		\
L
Linus Torvalds 已提交
1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057
} while (0)

#define __write_64bit_c0_register(register, sel, value)			\
do {									\
	if (sizeof(unsigned long) == 4)					\
		__write_64bit_c0_split(register, sel, value);		\
	else if (sel == 0)						\
		__asm__ __volatile__(					\
			".set\tmips3\n\t"				\
			"dmtc0\t%z0, " #register "\n\t"			\
			".set\tmips0"					\
			: : "Jr" (value));				\
	else								\
		__asm__ __volatile__(					\
			".set\tmips64\n\t"				\
			"dmtc0\t%z0, " #register ", " #sel "\n\t"	\
			".set\tmips0"					\
			: : "Jr" (value));				\
} while (0)

#define __read_ulong_c0_register(reg, sel)				\
	((sizeof(unsigned long) == 4) ?					\
	(unsigned long) __read_32bit_c0_register(reg, sel) :		\
	(unsigned long) __read_64bit_c0_register(reg, sel))

#define __write_ulong_c0_register(reg, sel, val)			\
do {									\
	if (sizeof(unsigned long) == 4)					\
		__write_32bit_c0_register(reg, sel, val);		\
	else								\
		__write_64bit_c0_register(reg, sel, val);		\
} while (0)

/*
 * On RM7000/RM9000 these are uses to access cop0 set 1 registers
 */
#define __read_32bit_c0_ctrl_register(source)				\
1058
({ unsigned int __res;							\
L
Linus Torvalds 已提交
1059 1060 1061 1062 1063 1064 1065 1066 1067 1068
	__asm__ __volatile__(						\
		"cfc0\t%0, " #source "\n\t"				\
		: "=r" (__res));					\
	__res;								\
})

#define __write_32bit_c0_ctrl_register(register, value)			\
do {									\
	__asm__ __volatile__(						\
		"ctc0\t%z0, " #register "\n\t"				\
R
Ralf Baechle 已提交
1069
		: : "Jr" ((unsigned int)(value)));			\
L
Linus Torvalds 已提交
1070 1071 1072 1073 1074 1075 1076 1077
} while (0)

/*
 * These versions are only needed for systems with more than 38 bits of
 * physical address space running the 32-bit kernel.  That's none atm :-)
 */
#define __read_64bit_c0_split(source, sel)				\
({									\
1078 1079
	unsigned long long __val;					\
	unsigned long __flags;						\
L
Linus Torvalds 已提交
1080
									\
1081
	local_irq_save(__flags);					\
L
Linus Torvalds 已提交
1082 1083 1084 1085 1086
	if (sel == 0)							\
		__asm__ __volatile__(					\
			".set\tmips64\n\t"				\
			"dmfc0\t%M0, " #source "\n\t"			\
			"dsll\t%L0, %M0, 32\n\t"			\
1087 1088
			"dsra\t%M0, %M0, 32\n\t"			\
			"dsra\t%L0, %L0, 32\n\t"			\
L
Linus Torvalds 已提交
1089
			".set\tmips0"					\
1090
			: "=r" (__val));				\
L
Linus Torvalds 已提交
1091 1092 1093 1094 1095
	else								\
		__asm__ __volatile__(					\
			".set\tmips64\n\t"				\
			"dmfc0\t%M0, " #source ", " #sel "\n\t"		\
			"dsll\t%L0, %M0, 32\n\t"			\
1096 1097
			"dsra\t%M0, %M0, 32\n\t"			\
			"dsra\t%L0, %L0, 32\n\t"			\
L
Linus Torvalds 已提交
1098
			".set\tmips0"					\
1099 1100
			: "=r" (__val));				\
	local_irq_restore(__flags);					\
L
Linus Torvalds 已提交
1101
									\
1102
	__val;								\
L
Linus Torvalds 已提交
1103 1104 1105 1106
})

#define __write_64bit_c0_split(source, sel, val)			\
do {									\
1107
	unsigned long __flags;						\
L
Linus Torvalds 已提交
1108
									\
1109
	local_irq_save(__flags);					\
L
Linus Torvalds 已提交
1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129
	if (sel == 0)							\
		__asm__ __volatile__(					\
			".set\tmips64\n\t"				\
			"dsll\t%L0, %L0, 32\n\t"			\
			"dsrl\t%L0, %L0, 32\n\t"			\
			"dsll\t%M0, %M0, 32\n\t"			\
			"or\t%L0, %L0, %M0\n\t"				\
			"dmtc0\t%L0, " #source "\n\t"			\
			".set\tmips0"					\
			: : "r" (val));					\
	else								\
		__asm__ __volatile__(					\
			".set\tmips64\n\t"				\
			"dsll\t%L0, %L0, 32\n\t"			\
			"dsrl\t%L0, %L0, 32\n\t"			\
			"dsll\t%M0, %M0, 32\n\t"			\
			"or\t%L0, %L0, %M0\n\t"				\
			"dmtc0\t%L0, " #source ", " #sel "\n\t"		\
			".set\tmips0"					\
			: : "r" (val));					\
1130
	local_irq_restore(__flags);					\
L
Linus Torvalds 已提交
1131 1132
} while (0)

1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165
#define __readx_32bit_c0_register(source)				\
({									\
	unsigned int __res;						\
									\
	__asm__ __volatile__(						\
	"	.set	push					\n"	\
	"	.set	noat					\n"	\
	"	.set	mips32r2				\n"	\
	"	.insn						\n"	\
	"	# mfhc0 $1, %1					\n"	\
	"	.word	(0x40410000 | ((%1 & 0x1f) << 11))	\n"	\
	"	move	%0, $1					\n"	\
	"	.set	pop					\n"	\
	: "=r" (__res)							\
	: "i" (source));						\
	__res;								\
})

#define __writex_32bit_c0_register(register, value)			\
do {									\
	__asm__ __volatile__(						\
	"	.set	push					\n"	\
	"	.set	noat					\n"	\
	"	.set	mips32r2				\n"	\
	"	move	$1, %0					\n"	\
	"	# mthc0 $1, %1					\n"	\
	"	.insn						\n"	\
	"	.word	(0x40c10000 | ((%1 & 0x1f) << 11))	\n"	\
	"	.set	pop					\n"	\
	:								\
	: "r" (value), "i" (register));					\
} while (0)

L
Linus Torvalds 已提交
1166 1167 1168
#define read_c0_index()		__read_32bit_c0_register($0, 0)
#define write_c0_index(val)	__write_32bit_c0_register($0, 0, val)

1169 1170 1171
#define read_c0_random()	__read_32bit_c0_register($1, 0)
#define write_c0_random(val)	__write_32bit_c0_register($1, 0, val)

L
Linus Torvalds 已提交
1172 1173 1174
#define read_c0_entrylo0()	__read_ulong_c0_register($2, 0)
#define write_c0_entrylo0(val)	__write_ulong_c0_register($2, 0, val)

1175 1176 1177
#define readx_c0_entrylo0()	__readx_32bit_c0_register(2)
#define writex_c0_entrylo0(val)	__writex_32bit_c0_register(2, val)

L
Linus Torvalds 已提交
1178 1179 1180
#define read_c0_entrylo1()	__read_ulong_c0_register($3, 0)
#define write_c0_entrylo1(val)	__write_ulong_c0_register($3, 0, val)

1181 1182 1183
#define readx_c0_entrylo1()	__readx_32bit_c0_register(3)
#define writex_c0_entrylo1(val)	__writex_32bit_c0_register(3, val)

L
Linus Torvalds 已提交
1184 1185 1186 1187 1188 1189
#define read_c0_conf()		__read_32bit_c0_register($3, 0)
#define write_c0_conf(val)	__write_32bit_c0_register($3, 0, val)

#define read_c0_context()	__read_ulong_c0_register($4, 0)
#define write_c0_context(val)	__write_ulong_c0_register($4, 0, val)

1190
#define read_c0_userlocal()	__read_ulong_c0_register($4, 2)
R
Ralf Baechle 已提交
1191
#define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val)
1192

L
Linus Torvalds 已提交
1193 1194 1195
#define read_c0_pagemask()	__read_32bit_c0_register($5, 0)
#define write_c0_pagemask(val)	__write_32bit_c0_register($5, 0, val)

1196
#define read_c0_pagegrain()	__read_32bit_c0_register($5, 1)
R
Ralf Baechle 已提交
1197
#define write_c0_pagegrain(val) __write_32bit_c0_register($5, 1, val)
1198

L
Linus Torvalds 已提交
1199 1200 1201 1202 1203
#define read_c0_wired()		__read_32bit_c0_register($6, 0)
#define write_c0_wired(val)	__write_32bit_c0_register($6, 0, val)

#define read_c0_info()		__read_32bit_c0_register($7, 0)

R
Ralf Baechle 已提交
1204
#define read_c0_cache()		__read_32bit_c0_register($7, 0) /* TX39xx */
L
Linus Torvalds 已提交
1205 1206
#define write_c0_cache(val)	__write_32bit_c0_register($7, 0, val)

1207 1208 1209
#define read_c0_badvaddr()	__read_ulong_c0_register($8, 0)
#define write_c0_badvaddr(val)	__write_ulong_c0_register($8, 0, val)

L
Linus Torvalds 已提交
1210 1211 1212
#define read_c0_count()		__read_32bit_c0_register($9, 0)
#define write_c0_count(val)	__write_32bit_c0_register($9, 0, val)

1213 1214 1215 1216 1217 1218
#define read_c0_count2()	__read_32bit_c0_register($9, 6) /* pnx8550 */
#define write_c0_count2(val)	__write_32bit_c0_register($9, 6, val)

#define read_c0_count3()	__read_32bit_c0_register($9, 7) /* pnx8550 */
#define write_c0_count3(val)	__write_32bit_c0_register($9, 7, val)

L
Linus Torvalds 已提交
1219 1220 1221 1222 1223 1224
#define read_c0_entryhi()	__read_ulong_c0_register($10, 0)
#define write_c0_entryhi(val)	__write_ulong_c0_register($10, 0, val)

#define read_c0_compare()	__read_32bit_c0_register($11, 0)
#define write_c0_compare(val)	__write_32bit_c0_register($11, 0, val)

1225 1226 1227 1228 1229 1230
#define read_c0_compare2()	__read_32bit_c0_register($11, 6) /* pnx8550 */
#define write_c0_compare2(val)	__write_32bit_c0_register($11, 6, val)

#define read_c0_compare3()	__read_32bit_c0_register($11, 7) /* pnx8550 */
#define write_c0_compare3(val)	__write_32bit_c0_register($11, 7, val)

L
Linus Torvalds 已提交
1231
#define read_c0_status()	__read_32bit_c0_register($12, 0)
R
Ralf Baechle 已提交
1232

L
Linus Torvalds 已提交
1233 1234 1235 1236 1237 1238 1239 1240 1241 1242
#define write_c0_status(val)	__write_32bit_c0_register($12, 0, val)

#define read_c0_cause()		__read_32bit_c0_register($13, 0)
#define write_c0_cause(val)	__write_32bit_c0_register($13, 0, val)

#define read_c0_epc()		__read_ulong_c0_register($14, 0)
#define write_c0_epc(val)	__write_ulong_c0_register($14, 0, val)

#define read_c0_prid()		__read_32bit_c0_register($15, 0)

1243 1244
#define read_c0_cmgcrbase()	__read_ulong_c0_register($15, 3)

L
Linus Torvalds 已提交
1245 1246 1247 1248
#define read_c0_config()	__read_32bit_c0_register($16, 0)
#define read_c0_config1()	__read_32bit_c0_register($16, 1)
#define read_c0_config2()	__read_32bit_c0_register($16, 2)
#define read_c0_config3()	__read_32bit_c0_register($16, 3)
1249 1250 1251 1252
#define read_c0_config4()	__read_32bit_c0_register($16, 4)
#define read_c0_config5()	__read_32bit_c0_register($16, 5)
#define read_c0_config6()	__read_32bit_c0_register($16, 6)
#define read_c0_config7()	__read_32bit_c0_register($16, 7)
L
Linus Torvalds 已提交
1253 1254 1255 1256
#define write_c0_config(val)	__write_32bit_c0_register($16, 0, val)
#define write_c0_config1(val)	__write_32bit_c0_register($16, 1, val)
#define write_c0_config2(val)	__write_32bit_c0_register($16, 2, val)
#define write_c0_config3(val)	__write_32bit_c0_register($16, 3, val)
1257 1258 1259 1260
#define write_c0_config4(val)	__write_32bit_c0_register($16, 4, val)
#define write_c0_config5(val)	__write_32bit_c0_register($16, 5, val)
#define write_c0_config6(val)	__write_32bit_c0_register($16, 6, val)
#define write_c0_config7(val)	__write_32bit_c0_register($16, 7, val)
L
Linus Torvalds 已提交
1261

1262 1263
#define read_c0_lladdr()	__read_ulong_c0_register($17, 0)
#define write_c0_lladdr(val)	__write_ulong_c0_register($17, 0, val)
1264 1265 1266 1267 1268
#define read_c0_maar()		__read_ulong_c0_register($17, 1)
#define write_c0_maar(val)	__write_ulong_c0_register($17, 1, val)
#define read_c0_maari()		__read_32bit_c0_register($17, 2)
#define write_c0_maari(val)	__write_32bit_c0_register($17, 2, val)

L
Linus Torvalds 已提交
1269
/*
L
Lucas De Marchi 已提交
1270
 * The WatchLo register.  There may be up to 8 of them.
L
Linus Torvalds 已提交
1271 1272 1273 1274 1275 1276 1277 1278 1279 1280 1281 1282 1283 1284 1285 1286 1287 1288 1289
 */
#define read_c0_watchlo0()	__read_ulong_c0_register($18, 0)
#define read_c0_watchlo1()	__read_ulong_c0_register($18, 1)
#define read_c0_watchlo2()	__read_ulong_c0_register($18, 2)
#define read_c0_watchlo3()	__read_ulong_c0_register($18, 3)
#define read_c0_watchlo4()	__read_ulong_c0_register($18, 4)
#define read_c0_watchlo5()	__read_ulong_c0_register($18, 5)
#define read_c0_watchlo6()	__read_ulong_c0_register($18, 6)
#define read_c0_watchlo7()	__read_ulong_c0_register($18, 7)
#define write_c0_watchlo0(val)	__write_ulong_c0_register($18, 0, val)
#define write_c0_watchlo1(val)	__write_ulong_c0_register($18, 1, val)
#define write_c0_watchlo2(val)	__write_ulong_c0_register($18, 2, val)
#define write_c0_watchlo3(val)	__write_ulong_c0_register($18, 3, val)
#define write_c0_watchlo4(val)	__write_ulong_c0_register($18, 4, val)
#define write_c0_watchlo5(val)	__write_ulong_c0_register($18, 5, val)
#define write_c0_watchlo6(val)	__write_ulong_c0_register($18, 6, val)
#define write_c0_watchlo7(val)	__write_ulong_c0_register($18, 7, val)

/*
L
Lucas De Marchi 已提交
1290
 * The WatchHi register.  There may be up to 8 of them.
L
Linus Torvalds 已提交
1291 1292 1293 1294 1295 1296 1297 1298 1299 1300 1301 1302 1303 1304 1305 1306 1307 1308 1309 1310 1311 1312 1313 1314 1315 1316
 */
#define read_c0_watchhi0()	__read_32bit_c0_register($19, 0)
#define read_c0_watchhi1()	__read_32bit_c0_register($19, 1)
#define read_c0_watchhi2()	__read_32bit_c0_register($19, 2)
#define read_c0_watchhi3()	__read_32bit_c0_register($19, 3)
#define read_c0_watchhi4()	__read_32bit_c0_register($19, 4)
#define read_c0_watchhi5()	__read_32bit_c0_register($19, 5)
#define read_c0_watchhi6()	__read_32bit_c0_register($19, 6)
#define read_c0_watchhi7()	__read_32bit_c0_register($19, 7)

#define write_c0_watchhi0(val)	__write_32bit_c0_register($19, 0, val)
#define write_c0_watchhi1(val)	__write_32bit_c0_register($19, 1, val)
#define write_c0_watchhi2(val)	__write_32bit_c0_register($19, 2, val)
#define write_c0_watchhi3(val)	__write_32bit_c0_register($19, 3, val)
#define write_c0_watchhi4(val)	__write_32bit_c0_register($19, 4, val)
#define write_c0_watchhi5(val)	__write_32bit_c0_register($19, 5, val)
#define write_c0_watchhi6(val)	__write_32bit_c0_register($19, 6, val)
#define write_c0_watchhi7(val)	__write_32bit_c0_register($19, 7, val)

#define read_c0_xcontext()	__read_ulong_c0_register($20, 0)
#define write_c0_xcontext(val)	__write_ulong_c0_register($20, 0, val)

#define read_c0_intcontrol()	__read_32bit_c0_ctrl_register($20)
#define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val)

#define read_c0_framemask()	__read_32bit_c0_register($21, 0)
R
Ralf Baechle 已提交
1317
#define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val)
L
Linus Torvalds 已提交
1318 1319 1320 1321

#define read_c0_diag()		__read_32bit_c0_register($22, 0)
#define write_c0_diag(val)	__write_32bit_c0_register($22, 0, val)

1322 1323 1324 1325
/* R10K CP0 Branch Diagnostic register is 64bits wide */
#define read_c0_r10k_diag()	__read_64bit_c0_register($22, 0)
#define write_c0_r10k_diag(val)	__write_64bit_c0_register($22, 0, val)

L
Linus Torvalds 已提交
1326 1327 1328 1329 1330 1331 1332 1333 1334 1335 1336 1337 1338 1339 1340 1341 1342 1343 1344 1345 1346 1347 1348 1349 1350
#define read_c0_diag1()		__read_32bit_c0_register($22, 1)
#define write_c0_diag1(val)	__write_32bit_c0_register($22, 1, val)

#define read_c0_diag2()		__read_32bit_c0_register($22, 2)
#define write_c0_diag2(val)	__write_32bit_c0_register($22, 2, val)

#define read_c0_diag3()		__read_32bit_c0_register($22, 3)
#define write_c0_diag3(val)	__write_32bit_c0_register($22, 3, val)

#define read_c0_diag4()		__read_32bit_c0_register($22, 4)
#define write_c0_diag4(val)	__write_32bit_c0_register($22, 4, val)

#define read_c0_diag5()		__read_32bit_c0_register($22, 5)
#define write_c0_diag5(val)	__write_32bit_c0_register($22, 5, val)

#define read_c0_debug()		__read_32bit_c0_register($23, 0)
#define write_c0_debug(val)	__write_32bit_c0_register($23, 0, val)

#define read_c0_depc()		__read_ulong_c0_register($24, 0)
#define write_c0_depc(val)	__write_ulong_c0_register($24, 0, val)

/*
 * MIPS32 / MIPS64 performance counters
 */
#define read_c0_perfctrl0()	__read_32bit_c0_register($25, 0)
R
Ralf Baechle 已提交
1351
#define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val)
L
Linus Torvalds 已提交
1352
#define read_c0_perfcntr0()	__read_32bit_c0_register($25, 1)
R
Ralf Baechle 已提交
1353
#define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val)
1354 1355
#define read_c0_perfcntr0_64()	__read_64bit_c0_register($25, 1)
#define write_c0_perfcntr0_64(val) __write_64bit_c0_register($25, 1, val)
L
Linus Torvalds 已提交
1356
#define read_c0_perfctrl1()	__read_32bit_c0_register($25, 2)
R
Ralf Baechle 已提交
1357
#define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val)
L
Linus Torvalds 已提交
1358
#define read_c0_perfcntr1()	__read_32bit_c0_register($25, 3)
R
Ralf Baechle 已提交
1359
#define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val)
1360 1361
#define read_c0_perfcntr1_64()	__read_64bit_c0_register($25, 3)
#define write_c0_perfcntr1_64(val) __write_64bit_c0_register($25, 3, val)
L
Linus Torvalds 已提交
1362
#define read_c0_perfctrl2()	__read_32bit_c0_register($25, 4)
R
Ralf Baechle 已提交
1363
#define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val)
L
Linus Torvalds 已提交
1364
#define read_c0_perfcntr2()	__read_32bit_c0_register($25, 5)
R
Ralf Baechle 已提交
1365
#define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val)
1366 1367
#define read_c0_perfcntr2_64()	__read_64bit_c0_register($25, 5)
#define write_c0_perfcntr2_64(val) __write_64bit_c0_register($25, 5, val)
L
Linus Torvalds 已提交
1368
#define read_c0_perfctrl3()	__read_32bit_c0_register($25, 6)
R
Ralf Baechle 已提交
1369
#define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val)
L
Linus Torvalds 已提交
1370
#define read_c0_perfcntr3()	__read_32bit_c0_register($25, 7)
R
Ralf Baechle 已提交
1371
#define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val)
1372 1373
#define read_c0_perfcntr3_64()	__read_64bit_c0_register($25, 7)
#define write_c0_perfcntr3_64(val) __write_64bit_c0_register($25, 7, val)
L
Linus Torvalds 已提交
1374 1375 1376 1377 1378

#define read_c0_ecc()		__read_32bit_c0_register($26, 0)
#define write_c0_ecc(val)	__write_32bit_c0_register($26, 0, val)

#define read_c0_derraddr0()	__read_ulong_c0_register($26, 1)
R
Ralf Baechle 已提交
1379
#define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val)
L
Linus Torvalds 已提交
1380 1381 1382 1383

#define read_c0_cacheerr()	__read_32bit_c0_register($27, 0)

#define read_c0_derraddr1()	__read_ulong_c0_register($27, 1)
R
Ralf Baechle 已提交
1384
#define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val)
L
Linus Torvalds 已提交
1385 1386 1387 1388

#define read_c0_taglo()		__read_32bit_c0_register($28, 0)
#define write_c0_taglo(val)	__write_32bit_c0_register($28, 0, val)

1389 1390 1391
#define read_c0_dtaglo()	__read_32bit_c0_register($28, 2)
#define write_c0_dtaglo(val)	__write_32bit_c0_register($28, 2, val)

1392 1393 1394 1395 1396 1397
#define read_c0_ddatalo()	__read_32bit_c0_register($28, 3)
#define write_c0_ddatalo(val)	__write_32bit_c0_register($28, 3, val)

#define read_c0_staglo()	__read_32bit_c0_register($28, 4)
#define write_c0_staglo(val)	__write_32bit_c0_register($28, 4, val)

L
Linus Torvalds 已提交
1398 1399 1400 1401 1402 1403
#define read_c0_taghi()		__read_32bit_c0_register($29, 0)
#define write_c0_taghi(val)	__write_32bit_c0_register($29, 0, val)

#define read_c0_errorepc()	__read_ulong_c0_register($30, 0)
#define write_c0_errorepc(val)	__write_ulong_c0_register($30, 0, val)

1404
/* MIPSR2 */
1405
#define read_c0_hwrena()	__read_32bit_c0_register($7, 0)
1406 1407 1408 1409 1410 1411 1412 1413 1414 1415 1416
#define write_c0_hwrena(val)	__write_32bit_c0_register($7, 0, val)

#define read_c0_intctl()	__read_32bit_c0_register($12, 1)
#define write_c0_intctl(val)	__write_32bit_c0_register($12, 1, val)

#define read_c0_srsctl()	__read_32bit_c0_register($12, 2)
#define write_c0_srsctl(val)	__write_32bit_c0_register($12, 2, val)

#define read_c0_srsmap()	__read_32bit_c0_register($12, 3)
#define write_c0_srsmap(val)	__write_32bit_c0_register($12, 3, val)

1417
#define read_c0_ebase()		__read_32bit_c0_register($15, 1)
1418 1419
#define write_c0_ebase(val)	__write_32bit_c0_register($15, 1, val)

1420 1421 1422
#define read_c0_cdmmbase()	__read_ulong_c0_register($15, 2)
#define write_c0_cdmmbase(val)	__write_ulong_c0_register($15, 2, val)

1423 1424 1425 1426 1427 1428 1429 1430 1431
/* MIPSR3 */
#define read_c0_segctl0()	__read_32bit_c0_register($5, 2)
#define write_c0_segctl0(val)	__write_32bit_c0_register($5, 2, val)

#define read_c0_segctl1()	__read_32bit_c0_register($5, 3)
#define write_c0_segctl1(val)	__write_32bit_c0_register($5, 3, val)

#define read_c0_segctl2()	__read_32bit_c0_register($5, 4)
#define write_c0_segctl2(val)	__write_32bit_c0_register($5, 4, val)
1432

1433 1434 1435 1436 1437 1438 1439 1440 1441 1442 1443 1444 1445
/* Hardware Page Table Walker */
#define read_c0_pwbase()	__read_ulong_c0_register($5, 5)
#define write_c0_pwbase(val)	__write_ulong_c0_register($5, 5, val)

#define read_c0_pwfield()	__read_ulong_c0_register($5, 6)
#define write_c0_pwfield(val)	__write_ulong_c0_register($5, 6, val)

#define read_c0_pwsize()	__read_ulong_c0_register($5, 7)
#define write_c0_pwsize(val)	__write_ulong_c0_register($5, 7, val)

#define read_c0_pwctl()		__read_32bit_c0_register($6, 6)
#define write_c0_pwctl(val)	__write_32bit_c0_register($6, 6, val)

1446 1447 1448 1449 1450 1451 1452 1453
/* Cavium OCTEON (cnMIPS) */
#define read_c0_cvmcount()	__read_ulong_c0_register($9, 6)
#define write_c0_cvmcount(val)	__write_ulong_c0_register($9, 6, val)

#define read_c0_cvmctl()	__read_64bit_c0_register($9, 7)
#define write_c0_cvmctl(val)	__write_64bit_c0_register($9, 7, val)

#define read_c0_cvmmemctl()	__read_64bit_c0_register($11, 7)
R
Ralf Baechle 已提交
1454
#define write_c0_cvmmemctl(val) __write_64bit_c0_register($11, 7, val)
1455
/*
R
Ralf Baechle 已提交
1456
 * The cacheerr registers are not standardized.	 On OCTEON, they are
1457 1458 1459 1460 1461 1462 1463 1464
 * 64 bits wide.
 */
#define read_octeon_c0_icacheerr()	__read_64bit_c0_register($27, 0)
#define write_octeon_c0_icacheerr(val)	__write_64bit_c0_register($27, 0, val)

#define read_octeon_c0_dcacheerr()	__read_64bit_c0_register($27, 1)
#define write_octeon_c0_dcacheerr(val)	__write_64bit_c0_register($27, 1, val)

1465 1466 1467 1468 1469 1470 1471 1472 1473 1474
/* BMIPS3300 */
#define read_c0_brcm_config_0()		__read_32bit_c0_register($22, 0)
#define write_c0_brcm_config_0(val)	__write_32bit_c0_register($22, 0, val)

#define read_c0_brcm_bus_pll()		__read_32bit_c0_register($22, 4)
#define write_c0_brcm_bus_pll(val)	__write_32bit_c0_register($22, 4, val)

#define read_c0_brcm_reset()		__read_32bit_c0_register($22, 5)
#define write_c0_brcm_reset(val)	__write_32bit_c0_register($22, 5, val)

1475
/* BMIPS43xx */
1476 1477 1478 1479 1480 1481 1482 1483 1484 1485 1486 1487 1488 1489 1490 1491 1492 1493 1494 1495 1496 1497 1498 1499 1500 1501 1502 1503 1504 1505 1506 1507 1508 1509
#define read_c0_brcm_cmt_intr()		__read_32bit_c0_register($22, 1)
#define write_c0_brcm_cmt_intr(val)	__write_32bit_c0_register($22, 1, val)

#define read_c0_brcm_cmt_ctrl()		__read_32bit_c0_register($22, 2)
#define write_c0_brcm_cmt_ctrl(val)	__write_32bit_c0_register($22, 2, val)

#define read_c0_brcm_cmt_local()	__read_32bit_c0_register($22, 3)
#define write_c0_brcm_cmt_local(val)	__write_32bit_c0_register($22, 3, val)

#define read_c0_brcm_config_1()		__read_32bit_c0_register($22, 5)
#define write_c0_brcm_config_1(val)	__write_32bit_c0_register($22, 5, val)

#define read_c0_brcm_cbr()		__read_32bit_c0_register($22, 6)
#define write_c0_brcm_cbr(val)		__write_32bit_c0_register($22, 6, val)

/* BMIPS5000 */
#define read_c0_brcm_config()		__read_32bit_c0_register($22, 0)
#define write_c0_brcm_config(val)	__write_32bit_c0_register($22, 0, val)

#define read_c0_brcm_mode()		__read_32bit_c0_register($22, 1)
#define write_c0_brcm_mode(val)		__write_32bit_c0_register($22, 1, val)

#define read_c0_brcm_action()		__read_32bit_c0_register($22, 2)
#define write_c0_brcm_action(val)	__write_32bit_c0_register($22, 2, val)

#define read_c0_brcm_edsp()		__read_32bit_c0_register($22, 3)
#define write_c0_brcm_edsp(val)		__write_32bit_c0_register($22, 3, val)

#define read_c0_brcm_bootvec()		__read_32bit_c0_register($22, 4)
#define write_c0_brcm_bootvec(val)	__write_32bit_c0_register($22, 4, val)

#define read_c0_brcm_sleepcount()	__read_32bit_c0_register($22, 7)
#define write_c0_brcm_sleepcount(val)	__write_32bit_c0_register($22, 7, val)

L
Linus Torvalds 已提交
1510 1511 1512
/*
 * Macros to access the floating point coprocessor control registers
 */
1513
#define _read_32bit_cp1_register(source, gas_hardfloat)			\
1514
({									\
1515
	unsigned int __res;						\
1516 1517 1518 1519 1520 1521 1522
									\
	__asm__ __volatile__(						\
	"	.set	push					\n"	\
	"	.set	reorder					\n"	\
	"	# gas fails to assemble cfc1 for some archs,	\n"	\
	"	# like Octeon.					\n"	\
	"	.set	mips1					\n"	\
1523
	"	"STR(gas_hardfloat)"				\n"	\
1524 1525 1526 1527 1528
	"	cfc1	%0,"STR(source)"			\n"	\
	"	.set	pop					\n"	\
	: "=r" (__res));						\
	__res;								\
})
L
Linus Torvalds 已提交
1529

1530 1531 1532 1533 1534 1535 1536 1537 1538 1539 1540
#define _write_32bit_cp1_register(dest, val, gas_hardfloat)		\
do {									\
	__asm__ __volatile__(						\
	"	.set	push					\n"	\
	"	.set	reorder					\n"	\
	"	"STR(gas_hardfloat)"				\n"	\
	"	ctc1	%0,"STR(dest)"				\n"	\
	"	.set	pop					\n"	\
	: : "r" (val));							\
} while (0)

1541 1542 1543
#ifdef GAS_HAS_SET_HARDFLOAT
#define read_32bit_cp1_register(source)					\
	_read_32bit_cp1_register(source, .set hardfloat)
1544 1545
#define write_32bit_cp1_register(dest, val)				\
	_write_32bit_cp1_register(dest, val, .set hardfloat)
1546 1547 1548
#else
#define read_32bit_cp1_register(source)					\
	_read_32bit_cp1_register(source, )
1549 1550
#define write_32bit_cp1_register(dest, val)				\
	_write_32bit_cp1_register(dest, val, )
1551 1552
#endif

1553
#ifdef HAVE_AS_DSP
1554 1555
#define rddsp(mask)							\
({									\
1556
	unsigned int __dspctl;						\
1557 1558
									\
	__asm__ __volatile__(						\
1559 1560
	"	.set push					\n"	\
	"	.set dsp					\n"	\
1561
	"	rddsp	%0, %x1					\n"	\
1562
	"	.set pop					\n"	\
1563
	: "=r" (__dspctl)						\
1564
	: "i" (mask));							\
1565
	__dspctl;							\
1566 1567 1568 1569 1570
})

#define wrdsp(val, mask)						\
do {									\
	__asm__ __volatile__(						\
1571 1572
	"	.set push					\n"	\
	"	.set dsp					\n"	\
1573
	"	wrdsp	%0, %x1					\n"	\
1574
	"	.set pop					\n"	\
R
Ralf Baechle 已提交
1575
	:								\
1576 1577 1578
	: "r" (val), "i" (mask));					\
} while (0)

1579 1580 1581 1582 1583 1584 1585 1586 1587 1588 1589 1590 1591 1592 1593 1594 1595 1596 1597 1598 1599 1600 1601 1602 1603 1604 1605 1606 1607 1608 1609 1610 1611 1612 1613 1614 1615 1616 1617 1618 1619 1620 1621 1622 1623 1624 1625 1626 1627 1628 1629 1630 1631 1632 1633 1634 1635 1636 1637 1638 1639 1640 1641 1642 1643 1644 1645 1646 1647 1648 1649 1650 1651 1652 1653 1654 1655 1656 1657 1658 1659 1660 1661 1662 1663 1664 1665 1666 1667 1668 1669 1670 1671 1672 1673 1674 1675 1676 1677 1678 1679 1680 1681 1682 1683 1684 1685 1686 1687 1688 1689 1690 1691 1692 1693 1694 1695 1696 1697 1698 1699 1700 1701 1702 1703 1704 1705 1706 1707 1708 1709 1710 1711 1712 1713 1714 1715 1716 1717 1718 1719 1720 1721 1722 1723 1724 1725 1726 1727 1728 1729 1730 1731 1732 1733 1734 1735 1736 1737 1738 1739 1740 1741 1742 1743 1744 1745 1746 1747 1748 1749 1750 1751 1752 1753 1754 1755 1756 1757 1758 1759 1760 1761 1762
#define mflo0()								\
({									\
	long mflo0;							\
	__asm__(							\
	"	.set push					\n"	\
	"	.set dsp					\n"	\
	"	mflo %0, $ac0					\n"	\
	"	.set pop					\n" 	\
	: "=r" (mflo0)); 						\
	mflo0;								\
})

#define mflo1()								\
({									\
	long mflo1;							\
	__asm__(							\
	"	.set push					\n"	\
	"	.set dsp					\n"	\
	"	mflo %0, $ac1					\n"	\
	"	.set pop					\n" 	\
	: "=r" (mflo1)); 						\
	mflo1;								\
})

#define mflo2()								\
({									\
	long mflo2;							\
	__asm__(							\
	"	.set push					\n"	\
	"	.set dsp					\n"	\
	"	mflo %0, $ac2					\n"	\
	"	.set pop					\n" 	\
	: "=r" (mflo2)); 						\
	mflo2;								\
})

#define mflo3()								\
({									\
	long mflo3;							\
	__asm__(							\
	"	.set push					\n"	\
	"	.set dsp					\n"	\
	"	mflo %0, $ac3					\n"	\
	"	.set pop					\n" 	\
	: "=r" (mflo3)); 						\
	mflo3;								\
})

#define mfhi0()								\
({									\
	long mfhi0;							\
	__asm__(							\
	"	.set push					\n"	\
	"	.set dsp					\n"	\
	"	mfhi %0, $ac0					\n"	\
	"	.set pop					\n" 	\
	: "=r" (mfhi0)); 						\
	mfhi0;								\
})

#define mfhi1()								\
({									\
	long mfhi1;							\
	__asm__(							\
	"	.set push					\n"	\
	"	.set dsp					\n"	\
	"	mfhi %0, $ac1					\n"	\
	"	.set pop					\n" 	\
	: "=r" (mfhi1)); 						\
	mfhi1;								\
})

#define mfhi2()								\
({									\
	long mfhi2;							\
	__asm__(							\
	"	.set push					\n"	\
	"	.set dsp					\n"	\
	"	mfhi %0, $ac2					\n"	\
	"	.set pop					\n" 	\
	: "=r" (mfhi2)); 						\
	mfhi2;								\
})

#define mfhi3()								\
({									\
	long mfhi3;							\
	__asm__(							\
	"	.set push					\n"	\
	"	.set dsp					\n"	\
	"	mfhi %0, $ac3					\n"	\
	"	.set pop					\n" 	\
	: "=r" (mfhi3)); 						\
	mfhi3;								\
})


#define mtlo0(x)							\
({									\
	__asm__(							\
	"	.set push					\n"	\
	"	.set dsp					\n"	\
	"	mtlo %0, $ac0					\n"	\
	"	.set pop					\n"	\
	:								\
	: "r" (x));							\
})

#define mtlo1(x)							\
({									\
	__asm__(							\
	"	.set push					\n"	\
	"	.set dsp					\n"	\
	"	mtlo %0, $ac1					\n"	\
	"	.set pop					\n"	\
	:								\
	: "r" (x));							\
})

#define mtlo2(x)							\
({									\
	__asm__(							\
	"	.set push					\n"	\
	"	.set dsp					\n"	\
	"	mtlo %0, $ac2					\n"	\
	"	.set pop					\n"	\
	:								\
	: "r" (x));							\
})

#define mtlo3(x)							\
({									\
	__asm__(							\
	"	.set push					\n"	\
	"	.set dsp					\n"	\
	"	mtlo %0, $ac3					\n"	\
	"	.set pop					\n"	\
	:								\
	: "r" (x));							\
})

#define mthi0(x)							\
({									\
	__asm__(							\
	"	.set push					\n"	\
	"	.set dsp					\n"	\
	"	mthi %0, $ac0					\n"	\
	"	.set pop					\n"	\
	:								\
	: "r" (x));							\
})

#define mthi1(x)							\
({									\
	__asm__(							\
	"	.set push					\n"	\
	"	.set dsp					\n"	\
	"	mthi %0, $ac1					\n"	\
	"	.set pop					\n"	\
	:								\
	: "r" (x));							\
})

#define mthi2(x)							\
({									\
	__asm__(							\
	"	.set push					\n"	\
	"	.set dsp					\n"	\
	"	mthi %0, $ac2					\n"	\
	"	.set pop					\n"	\
	:								\
	: "r" (x));							\
})

#define mthi3(x)							\
({									\
	__asm__(							\
	"	.set push					\n"	\
	"	.set dsp					\n"	\
	"	mthi %0, $ac3					\n"	\
	"	.set pop					\n"	\
	:								\
	: "r" (x));							\
})
1763 1764 1765

#else

1766 1767
#ifdef CONFIG_CPU_MICROMIPS
#define rddsp(mask)							\
1768
({									\
1769
	unsigned int __res;						\
1770 1771 1772 1773
									\
	__asm__ __volatile__(						\
	"	.set	push					\n"	\
	"	.set	noat					\n"	\
1774 1775 1776 1777
	"	# rddsp $1, %x1					\n"	\
	"	.hword	((0x0020067c | (%x1 << 14)) >> 16)	\n"	\
	"	.hword	((0x0020067c | (%x1 << 14)) & 0xffff)	\n"	\
	"	move	%0, $1					\n"	\
1778
	"	.set	pop					\n"	\
1779 1780 1781 1782
	: "=r" (__res)							\
	: "i" (mask));							\
	__res;								\
})
1783

1784
#define wrdsp(val, mask)						\
1785 1786 1787 1788 1789
do {									\
	__asm__ __volatile__(						\
	"	.set	push					\n"	\
	"	.set	noat					\n"	\
	"	move	$1, %0					\n"	\
1790 1791 1792
	"	# wrdsp $1, %x1					\n"	\
	"	.hword	((0x0020167c | (%x1 << 14)) >> 16)	\n"	\
	"	.hword	((0x0020167c | (%x1 << 14)) & 0xffff)	\n"	\
1793 1794
	"	.set	pop					\n"	\
	:								\
1795
	: "r" (val), "i" (mask));					\
1796 1797
} while (0)

1798 1799 1800 1801
#define _umips_dsp_mfxxx(ins)						\
({									\
	unsigned long __treg;						\
									\
1802 1803 1804
	__asm__ __volatile__(						\
	"	.set	push					\n"	\
	"	.set	noat					\n"	\
1805 1806 1807
	"	.hword	0x0001					\n"	\
	"	.hword	%x1					\n"	\
	"	move	%0, $1					\n"	\
1808
	"	.set	pop					\n"	\
1809 1810 1811 1812
	: "=r" (__treg)							\
	: "i" (ins));							\
	__treg;								\
})
1813

1814
#define _umips_dsp_mtxxx(val, ins)					\
1815 1816 1817 1818 1819
do {									\
	__asm__ __volatile__(						\
	"	.set	push					\n"	\
	"	.set	noat					\n"	\
	"	move	$1, %0					\n"	\
1820 1821
	"	.hword	0x0001					\n"	\
	"	.hword	%x1					\n"	\
1822 1823
	"	.set	pop					\n"	\
	:								\
1824
	: "r" (val), "i" (ins));					\
1825 1826
} while (0)

1827 1828 1829 1830 1831 1832 1833 1834 1835 1836 1837 1838 1839 1840 1841 1842 1843 1844 1845 1846 1847 1848 1849 1850 1851 1852 1853
#define _umips_dsp_mflo(reg) _umips_dsp_mfxxx((reg << 14) | 0x107c)
#define _umips_dsp_mfhi(reg) _umips_dsp_mfxxx((reg << 14) | 0x007c)

#define _umips_dsp_mtlo(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x307c))
#define _umips_dsp_mthi(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x207c))

#define mflo0() _umips_dsp_mflo(0)
#define mflo1() _umips_dsp_mflo(1)
#define mflo2() _umips_dsp_mflo(2)
#define mflo3() _umips_dsp_mflo(3)

#define mfhi0() _umips_dsp_mfhi(0)
#define mfhi1() _umips_dsp_mfhi(1)
#define mfhi2() _umips_dsp_mfhi(2)
#define mfhi3() _umips_dsp_mfhi(3)

#define mtlo0(x) _umips_dsp_mtlo(x, 0)
#define mtlo1(x) _umips_dsp_mtlo(x, 1)
#define mtlo2(x) _umips_dsp_mtlo(x, 2)
#define mtlo3(x) _umips_dsp_mtlo(x, 3)

#define mthi0(x) _umips_dsp_mthi(x, 0)
#define mthi1(x) _umips_dsp_mthi(x, 1)
#define mthi2(x) _umips_dsp_mthi(x, 2)
#define mthi3(x) _umips_dsp_mthi(x, 3)

#else  /* !CONFIG_CPU_MICROMIPS */
1854 1855 1856 1857
#define rddsp(mask)							\
({									\
	unsigned int __res;						\
									\
1858
	__asm__ __volatile__(						\
1859 1860 1861 1862 1863 1864 1865 1866 1867 1868
	"	.set	push				\n"		\
	"	.set	noat				\n"		\
	"	# rddsp $1, %x1				\n"		\
	"	.word	0x7c000cb8 | (%x1 << 16)	\n"		\
	"	move	%0, $1				\n"		\
	"	.set	pop				\n"		\
	: "=r" (__res)							\
	: "i" (mask));							\
	__res;								\
})
1869

1870
#define wrdsp(val, mask)						\
1871 1872 1873 1874 1875
do {									\
	__asm__ __volatile__(						\
	"	.set	push					\n"	\
	"	.set	noat					\n"	\
	"	move	$1, %0					\n"	\
1876 1877
	"	# wrdsp $1, %x1					\n"	\
	"	.word	0x7c2004f8 | (%x1 << 11)		\n"	\
1878
	"	.set	pop					\n"	\
1879 1880
        :								\
	: "r" (val), "i" (mask));					\
1881 1882
} while (0)

1883
#define _dsp_mfxxx(ins)							\
1884 1885 1886 1887 1888 1889
({									\
	unsigned long __treg;						\
									\
	__asm__ __volatile__(						\
	"	.set	push					\n"	\
	"	.set	noat					\n"	\
1890 1891
	"	.word	(0x00000810 | %1)			\n"	\
	"	move	%0, $1					\n"	\
1892
	"	.set	pop					\n"	\
1893 1894 1895 1896
	: "=r" (__treg)							\
	: "i" (ins));							\
	__treg;								\
})
1897

1898
#define _dsp_mtxxx(val, ins)						\
1899 1900 1901 1902 1903
do {									\
	__asm__ __volatile__(						\
	"	.set	push					\n"	\
	"	.set	noat					\n"	\
	"	move	$1, %0					\n"	\
1904
	"	.word	(0x00200011 | %1)			\n"	\
1905 1906
	"	.set	pop					\n"	\
	:								\
1907
	: "r" (val), "i" (ins));					\
1908 1909
} while (0)

1910 1911
#define _dsp_mflo(reg) _dsp_mfxxx((reg << 21) | 0x0002)
#define _dsp_mfhi(reg) _dsp_mfxxx((reg << 21) | 0x0000)
1912

1913 1914
#define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0002))
#define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0000))
1915

1916 1917 1918 1919
#define mflo0() _dsp_mflo(0)
#define mflo1() _dsp_mflo(1)
#define mflo2() _dsp_mflo(2)
#define mflo3() _dsp_mflo(3)
1920

1921 1922 1923 1924
#define mfhi0() _dsp_mfhi(0)
#define mfhi1() _dsp_mfhi(1)
#define mfhi2() _dsp_mfhi(2)
#define mfhi3() _dsp_mfhi(3)
1925

1926 1927 1928 1929
#define mtlo0(x) _dsp_mtlo(x, 0)
#define mtlo1(x) _dsp_mtlo(x, 1)
#define mtlo2(x) _dsp_mtlo(x, 2)
#define mtlo3(x) _dsp_mtlo(x, 3)
1930

1931 1932 1933 1934
#define mthi0(x) _dsp_mthi(x, 0)
#define mthi1(x) _dsp_mthi(x, 1)
#define mthi2(x) _dsp_mthi(x, 2)
#define mthi3(x) _dsp_mthi(x, 3)
1935

1936
#endif /* CONFIG_CPU_MICROMIPS */
1937 1938
#endif

L
Linus Torvalds 已提交
1939 1940 1941 1942 1943 1944 1945 1946 1947 1948 1949 1950 1951 1952 1953
/*
 * TLB operations.
 *
 * It is responsibility of the caller to take care of any TLB hazards.
 */
static inline void tlb_probe(void)
{
	__asm__ __volatile__(
		".set noreorder\n\t"
		"tlbp\n\t"
		".set reorder");
}

static inline void tlb_read(void)
{
M
Marc St-Jean 已提交
1954 1955 1956 1957 1958 1959 1960 1961 1962 1963 1964 1965 1966 1967 1968 1969 1970
#if MIPS34K_MISSED_ITLB_WAR
	int res = 0;

	__asm__ __volatile__(
	"	.set	push					\n"
	"	.set	noreorder				\n"
	"	.set	noat					\n"
	"	.set	mips32r2				\n"
	"	.word	0x41610001		# dvpe $1	\n"
	"	move	%0, $1					\n"
	"	ehb						\n"
	"	.set	pop					\n"
	: "=r" (res));

	instruction_hazard();
#endif

L
Linus Torvalds 已提交
1971 1972 1973 1974
	__asm__ __volatile__(
		".set noreorder\n\t"
		"tlbr\n\t"
		".set reorder");
M
Marc St-Jean 已提交
1975 1976 1977 1978 1979 1980 1981 1982 1983 1984 1985 1986

#if MIPS34K_MISSED_ITLB_WAR
	if ((res & _ULCAST_(1)))
		__asm__ __volatile__(
		"	.set	push				\n"
		"	.set	noreorder			\n"
		"	.set	noat				\n"
		"	.set	mips32r2			\n"
		"	.word	0x41600021	# evpe		\n"
		"	ehb					\n"
		"	.set	pop				\n");
#endif
L
Linus Torvalds 已提交
1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011
}

static inline void tlb_write_indexed(void)
{
	__asm__ __volatile__(
		".set noreorder\n\t"
		"tlbwi\n\t"
		".set reorder");
}

static inline void tlb_write_random(void)
{
	__asm__ __volatile__(
		".set noreorder\n\t"
		"tlbwr\n\t"
		".set reorder");
}

/*
 * Manipulate bits in a c0 register.
 */
#define __BUILD_SET_C0(name)					\
static inline unsigned int					\
set_c0_##name(unsigned int set)					\
{								\
2012
	unsigned int res, new;					\
L
Linus Torvalds 已提交
2013 2014
								\
	res = read_c0_##name();					\
2015 2016
	new = res | set;					\
	write_c0_##name(new);					\
L
Linus Torvalds 已提交
2017 2018 2019 2020 2021 2022 2023
								\
	return res;						\
}								\
								\
static inline unsigned int					\
clear_c0_##name(unsigned int clear)				\
{								\
2024
	unsigned int res, new;					\
L
Linus Torvalds 已提交
2025 2026
								\
	res = read_c0_##name();					\
2027 2028
	new = res & ~clear;					\
	write_c0_##name(new);					\
L
Linus Torvalds 已提交
2029 2030 2031 2032 2033
								\
	return res;						\
}								\
								\
static inline unsigned int					\
2034
change_c0_##name(unsigned int change, unsigned int val)		\
L
Linus Torvalds 已提交
2035
{								\
2036
	unsigned int res, new;					\
L
Linus Torvalds 已提交
2037 2038
								\
	res = read_c0_##name();					\
2039 2040 2041
	new = res & ~change;					\
	new |= (val & change);					\
	write_c0_##name(new);					\
L
Linus Torvalds 已提交
2042 2043 2044 2045 2046 2047 2048
								\
	return res;						\
}

__BUILD_SET_C0(status)
__BUILD_SET_C0(cause)
__BUILD_SET_C0(config)
2049
__BUILD_SET_C0(config5)
L
Linus Torvalds 已提交
2050
__BUILD_SET_C0(intcontrol)
2051 2052
__BUILD_SET_C0(intctl)
__BUILD_SET_C0(srsmap)
2053
__BUILD_SET_C0(pagegrain)
2054 2055 2056 2057 2058 2059 2060
__BUILD_SET_C0(brcm_config_0)
__BUILD_SET_C0(brcm_bus_pll)
__BUILD_SET_C0(brcm_reset)
__BUILD_SET_C0(brcm_cmt_intr)
__BUILD_SET_C0(brcm_cmt_ctrl)
__BUILD_SET_C0(brcm_config)
__BUILD_SET_C0(brcm_mode)
L
Linus Torvalds 已提交
2061

2062 2063 2064 2065 2066 2067 2068 2069 2070
/*
 * Return low 10 bits of ebase.
 * Note that under KVM (MIPSVZ) this returns vcpu id.
 */
static inline unsigned int get_ebase_cpunum(void)
{
	return read_c0_ebase() & 0x3ff;
}

L
Linus Torvalds 已提交
2071 2072 2073
#endif /* !__ASSEMBLY__ */

#endif /* _ASM_MIPSREGS_H */