diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f0/uart_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f0/uart_config.h index 44cbe3003939cab4f7aaa9a91e39e4bdb52b6b25..64ad12adf4e3bead150462621c08659d15bfb931 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/f0/uart_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/f0/uart_config.h @@ -15,34 +15,46 @@ #if defined(BSP_USING_UART1) #ifndef UART1_CONFIG -#define UART1_CONFIG \ - { \ - .name = "uart1", \ - .Instance = USART1, \ - .irq_type = USART1_IRQn, \ - .dma.Instance = DMA1_Channel3, \ - .dma_rcc = RCC_AHBENR_DMA1EN, \ - .dma_irq = DMA1_Ch2_3_DMA2_Ch1_2_IRQn, \ +#define UART1_CONFIG \ + { \ + .name = "uart1", \ + .Instance = USART1, \ + .irq_type = USART1_IRQn, \ } - -#define USART1_RX_DMA_ISR DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler #endif /* UART1_CONFIG */ #endif /* BSP_USING_UART1 */ +#if defined(BSP_UART1_RX_USING_DMA) +#ifndef UART1_DMA_CONFIG +#define UART1_DMA_CONFIG \ + { \ + .Instance = USART1_RX_DMA_INSTANCE, \ + .dma_rcc = USART1_RX_DMA_RCC, \ + .dma_irq = USART1_RX_DMA_IRQ, \ + } +#endif /* UART1_DMA_CONFIG */ +#endif /* BSP_UART1_RX_USING_DMA */ + #if defined(BSP_USING_UART2) #ifndef UART2_CONFIG -#define UART2_CONFIG \ - { \ - .name = "uart2", \ - .Instance = USART2, \ - .irq_type = USART2_IRQn, \ - .dma.Instance = DMA1_Channel3, \ - .dma_rcc = RCC_AHBENR_DMA1EN, \ - .dma_irq = DMA1_Ch2_3_DMA2_Ch1_2_IRQn, \ +#define UART2_CONFIG \ + { \ + .name = "uart2", \ + .Instance = USART2, \ + .irq_type = USART2_IRQn, \ } - -#define USART2_RX_DMA_ISR DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler #endif /* UART2_CONFIG */ #endif /* BSP_USING_UART2 */ + +#if defined(BSP_UART2_RX_USING_DMA) +#ifndef UART2_DMA_CONFIG +#define UART2_DMA_CONFIG \ + { \ + .Instance = USART2_RX_DMA_INSTANCE, \ + .dma_rcc = USART2_RX_DMA_RCC, \ + .dma_irq = USART2_RX_DMA_IRQ, \ + } +#endif /* UART2_DMA_CONFIG */ +#endif /* BSP_UART2_RX_USING_DMA */ #endif /* __UART_CONFIG_H__ */ diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f1/spi_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f1/spi_config.h index a910847e3971e605b37d2545207627088813b459..b77ce5ef3b85e51f988fa68152488eab09ad4488 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/f1/spi_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/f1/spi_config.h @@ -5,7 +5,8 @@ * * Change Logs: * Date Author Notes - * 2018-11-06 SummerGift change to new framework + * 2018-11-06 SummerGift first version + * 2019-01-05 SummerGift modify DMA support */ #ifndef __SPI_CONFIG_H__ @@ -14,55 +15,101 @@ #include #ifdef BSP_USING_SPI1 -#define SPI1_BUS_CONFIG \ - { \ - .Instance = SPI1, \ - .bus_name = "spi1", \ - .dma_rx.dma_rcc = RCC_AHBENR_DMA1EN, \ - .dma_tx.dma_rcc = RCC_AHBENR_DMA1EN, \ - .dma_rx.Instance = DMA1_Channel2, \ - .dma_rx.dma_irq = DMA1_Channel2_IRQn, \ - .dma_tx.Instance = DMA1_Channel3, \ - .dma_tx.dma_irq = DMA1_Channel3_IRQn, \ +#ifndef SPI1_BUS_CONFIG +#define SPI1_BUS_CONFIG \ + { \ + .Instance = SPI1, \ + .bus_name = "spi1", \ } +#endif /* SPI1_BUS_CONFIG */ +#endif /* BSP_USING_SPI1 */ + +#ifdef BSP_SPI1_TX_USING_DMA +#ifndef SPI1_TX_DMA_CONFIG +#define SPI1_TX_DMA_CONFIG \ + { \ + .dma_rcc = SPI1_TX_DMA_RCC, \ + .Instance = SPI1_TX_DMA_INSTANCE, \ + .dma_irq = SPI1_TX_DMA_IRQ, \ + } +#endif /* SPI1_TX_DMA_CONFIG */ +#endif /* BSP_SPI1_TX_USING_DMA */ -#define SPI1_DMA_RX_IRQHandler DMA1_Channel2_IRQHandler -#define SPI1_DMA_TX_IRQHandler DMA1_Channel3_IRQHandler -#endif +#ifdef BSP_SPI1_RX_USING_DMA +#ifndef SPI1_RX_DMA_CONFIG +#define SPI1_RX_DMA_CONFIG \ + { \ + .dma_rcc = SPI1_RX_DMA_RCC, \ + .Instance = SPI1_RX_DMA_INSTANCE, \ + .dma_irq = SPI1_RX_DMA_IRQ, \ + } +#endif /* SPI1_RX_DMA_CONFIG */ +#endif /* BSP_SPI1_RX_USING_DMA */ #ifdef BSP_USING_SPI2 -#define SPI2_BUS_CONFIG \ - { \ - .Instance = SPI2, \ - .bus_name = "spi2", \ - .dma_rx.dma_rcc = RCC_AHBENR_DMA1EN, \ - .dma_tx.dma_rcc = RCC_AHBENR_DMA1EN, \ - .dma_rx.Instance = DMA1_Channel4, \ - .dma_rx.dma_irq = DMA1_Channel4_IRQn, \ - .dma_tx.Instance = DMA1_Channel5, \ - .dma_tx.dma_irq = DMA1_Channel5_IRQn, \ +#ifndef SPI2_BUS_CONFIG +#define SPI2_BUS_CONFIG \ + { \ + .Instance = SPI2, \ + .bus_name = "spi2", \ } +#endif /* SPI2_BUS_CONFIG */ +#endif /* BSP_USING_SPI2 */ -#define SPI2_DMA_RX_IRQHandler DMA1_Channel4_IRQHandler -#define SPI2_DMA_TX_IRQHandler DMA1_Channel5_IRQHandler -#endif +#ifdef BSP_SPI2_TX_USING_DMA +#ifndef SPI2_TX_DMA_CONFIG +#define SPI2_TX_DMA_CONFIG \ + { \ + .dma_rcc = SPI2_TX_DMA_RCC, \ + .Instance = SPI2_TX_DMA_INSTANCE, \ + .dma_irq = SPI2_TX_DMA_IRQ, \ + } +#endif /* SPI2_TX_DMA_CONFIG */ +#endif /* BSP_SPI2_TX_USING_DMA */ + +#ifdef BSP_SPI2_RX_USING_DMA +#ifndef SPI2_RX_DMA_CONFIG +#define SPI2_RX_DMA_CONFIG \ + { \ + .dma_rcc = SPI2_RX_DMA_RCC, \ + .Instance = SPI2_RX_DMA_INSTANCE, \ + .dma_irq = SPI2_RX_DMA_IRQ, \ + } +#endif /* SPI2_RX_DMA_CONFIG */ +#endif /* BSP_SPI2_RX_USING_DMA */ #ifdef BSP_USING_SPI3 -#define SPI3_BUS_CONFIG \ - { \ - .Instance = SPI3, \ - .bus_name = "spi3", \ - .dma_rx.dma_rcc = RCC_AHBENR_DMA2EN, \ - .dma_tx.dma_rcc = RCC_AHBENR_DMA2EN, \ - .dma_rx.Instance = DMA2_Channel1, \ - .dma_rx.dma_irq = DMA2_Channel1_IRQn, \ - .dma_tx.Instance = DMA2_Channel2, \ - .dma_tx.dma_irq = DMA2_Channel2_IRQn, \ +#ifndef SPI3_BUS_CONFIG +#define SPI3_BUS_CONFIG \ + { \ + .Instance = SPI3, \ + .bus_name = "spi3", \ } +#endif /* SPI3_BUS_CONFIG */ +#endif /* BSP_USING_SPI3 */ -#define SPI3_DMA_RX_IRQHandler DMA2_Channel1_IRQHandler -#define SPI3_DMA_TX_IRQHandler DMA2_Channel2_IRQHandler -#endif +#ifdef BSP_SPI3_TX_USING_DMA +#ifndef SPI3_TX_DMA_CONFIG +#define SPI3_TX_DMA_CONFIG \ + { \ + .dma_rcc = SPI3_TX_DMA_RCC, \ + .Instance = SPI3_TX_DMA_INSTANCE, \ + .dma_irq = SPI3_TX_DMA_IRQ, \ + } +#endif /* SPI3_TX_DMA_CONFIG */ +#endif /* BSP_SPI3_TX_USING_DMA */ + +#ifdef BSP_SPI3_RX_USING_DMA +#ifndef SPI3_RX_DMA_CONFIG +#define SPI3_RX_DMA_CONFIG \ + { \ + .dma_rcc = SPI3_RX_DMA_RCC, \ + .Instance = SPI3_RX_DMA_INSTANCE, \ + .dma_irq = SPI3_RX_DMA_IRQ, \ + } +#endif /* SPI3_RX_DMA_CONFIG */ +#endif /* BSP_SPI3_RX_USING_DMA */ + #endif /*__SPI_CONFIG_H__ */ diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f1/uart_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f1/uart_config.h index fd7482f4e6b6036d4ddf1f3c72877e0cb09a2fa8..f7c5f41f9b748e59a72d8e15845dc31c88b86c92 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/f1/uart_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/f1/uart_config.h @@ -5,81 +5,122 @@ * * Change Logs: * Date Author Notes - * 2018-10-30 BalanceTWK change to new framework + * 2018-10-30 BalanceTWK first version + * 2019-01-05 SummerGift modify DMA support */ #ifndef __UART_CONFIG_H__ #define __UART_CONFIG_H__ #include +#include "dma_config.h" #if defined(BSP_USING_UART1) -#define UART1_CONFIG \ - { \ - .name = "uart1", \ - .Instance = USART1, \ - .irq_type = USART1_IRQn, \ - .dma.channel.Instance = DMA1_Channel5, \ - .dma_rcc = RCC_AHBENR_DMA1EN, \ - .dma_irq = DMA1_Channel5_IRQn, \ +#ifndef UART1_CONFIG +#define UART1_CONFIG \ + { \ + .name = "uart1", \ + .Instance = USART1, \ + .irq_type = USART1_IRQn, \ } +#endif /* UART1_CONFIG */ +#endif /* BSP_USING_UART1 */ -#define USART1_RX_DMA_ISR DMA1_Channel5_IRQHandler -#endif +#if defined(BSP_UART1_RX_USING_DMA) +#ifndef UART1_DMA_CONFIG +#define UART1_DMA_CONFIG \ + { \ + .Instance = USART1_RX_DMA_INSTANCE, \ + .dma_rcc = USART1_RX_DMA_RCC, \ + .dma_irq = USART1_RX_DMA_IRQ, \ + } +#endif /* UART1_DMA_CONFIG */ +#endif /* BSP_UART1_RX_USING_DMA */ #if defined(BSP_USING_UART2) +#ifndef UART2_CONFIG +#define UART2_CONFIG \ + { \ + .name = "uart2", \ + .Instance = USART2, \ + .irq_type = USART2_IRQn, \ + } +#endif /* UART2_CONFIG */ +#endif /* BSP_USING_UART2 */ -#define UART2_CONFIG \ - { \ - .name = "uart2", \ - .Instance = USART2, \ - .irq_type = USART2_IRQn, \ - .dma.channel.Instance = DMA1_Channel6, \ - .dma_rcc = RCC_AHBENR_DMA1EN, \ - .dma_irq = DMA1_Channel6_IRQn, \ +#if defined(BSP_UART2_RX_USING_DMA) +#ifndef UART2_DMA_CONFIG +#define UART2_DMA_CONFIG \ + { \ + .Instance = USART2_RX_DMA_INSTANCE, \ + .dma_rcc = USART2_RX_DMA_RCC, \ + .dma_irq = USART2_RX_DMA_IRQ, \ } +#endif /* UART2_DMA_CONFIG */ +#endif /* BSP_UART2_RX_USING_DMA */ -#define USART2_RX_DMA_ISR DMA1_Channel6_IRQHandler -#endif - #if defined(BSP_USING_UART3) - -#define UART3_CONFIG \ - { \ - .name = "uart3", \ - .Instance = USART3, \ - .irq_type = USART3_IRQn, \ - .dma.channel.Instance = DMA1_Channel3, \ - .dma_rcc = RCC_AHBENR_DMA1EN, \ - .dma_irq = DMA1_Channel3_IRQn, \ +#ifndef UART3_CONFIG +#define UART3_CONFIG \ + { \ + .name = "uart3", \ + .Instance = USART3, \ + .irq_type = USART3_IRQn, \ } +#endif /* UART3_CONFIG */ +#endif /* BSP_USING_UART3 */ -#define USART3_RX_DMA_ISR DMA1_Channel3_IRQHandler -#endif +#if defined(BSP_UART3_RX_USING_DMA) +#ifndef UART3_DMA_CONFIG +#define UART3_DMA_CONFIG \ + { \ + .Instance = USART3_RX_DMA_INSTANCE, \ + .dma_rcc = USART3_RX_DMA_RCC, \ + .dma_irq = USART3_RX_DMA_IRQ, \ + } +#endif /* UART3_DMA_CONFIG */ +#endif /* BSP_UART3_RX_USING_DMA */ #if defined(BSP_USING_UART4) - -#define UART4_CONFIG \ - { \ - .name = "uart4", \ - .Instance = UART4, \ - .irq_type = UART4_IRQn, \ - .dma.channel.Instance = DMA2_Channel3, \ - .dma_rcc = RCC_AHBENR_DMA2EN, \ - .dma_irq = DMA2_Channel3_IRQn, \ +#ifndef UART4_CONFIG +#define UART4_CONFIG \ + { \ + .name = "uart4", \ + .Instance = UART4, \ + .irq_type = UART4_IRQn, \ } +#endif /* UART4_CONFIG */ +#endif /* BSP_USING_UART4 */ -#define USART4_RX_DMA_ISR DMA2_Channel3_IRQHandler -#endif +#if defined(BSP_UART4_RX_USING_DMA) +#ifndef UART4_DMA_CONFIG +#define UART4_DMA_CONFIG \ + { \ + .Instance = USART4_RX_DMA_INSTANCE, \ + .dma_rcc = USART4_RX_DMA_RCC, \ + .dma_irq = USART4_RX_DMA_IRQ, \ + } +#endif /* UART4_DMA_CONFIG */ +#endif /* BSP_UART4_RX_USING_DMA */ #if defined(BSP_USING_UART5) +#ifndef UART5_CONFIG +#define UART5_CONFIG \ + { \ + .name = "uart5", \ + .Instance = UART5, \ + .irq_type = UART5_IRQn, \ + } +#endif /* UART5_CONFIG */ +#endif /* BSP_USING_UART5 */ -#define UART5_CONFIG \ - { \ - .name = "uart5", \ - .Instance = UART5, \ - .irq_type = UART5_IRQn, \ - .dma.channel.Instance = DMA_NOT_AVAILABLE, \ +#if defined(BSP_UART5_RX_USING_DMA) +#ifndef UART5_DMA_CONFIG +#define UART5_DMA_CONFIG \ + { \ + .Instance = DMA_NOT_AVAILABLE, \ } -#endif +#endif /* UART5_DMA_CONFIG */ +#endif /* BSP_UART5_RX_USING_DMA */ + #endif diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f4/spi_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f4/spi_config.h index abeecd71546cccf2b613ecbaf1fc418988475ef9..3cd3f69884584d17f9d4e753359ac8c64f8d840f 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/f4/spi_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/f4/spi_config.h @@ -5,7 +5,8 @@ * * Change Logs: * Date Author Notes - * 2018-11-06 SummerGift change to new framework + * 2018-11-06 SummerGift first version + * 2019-01-03 zylx modify DMA support */ #ifndef __SPI_CONFIG_H__ @@ -14,101 +15,173 @@ #include #ifdef BSP_USING_SPI1 -#define SPI1_BUS_CONFIG \ - { \ - .Instance = SPI1, \ - .bus_name = "spi1", \ - .dma_rx.dma_rcc = RCC_AHB1ENR_DMA2EN, \ - .dma_tx.dma_rcc = RCC_AHB1ENR_DMA2EN, \ - .dma_rx.Instance = DMA2_Stream2, \ - .dma_rx.channel = DMA_CHANNEL_3, \ - .dma_rx.dma_irq = DMA2_Stream2_IRQn, \ - .dma_tx.Instance = DMA2_Stream3, \ - .dma_tx.channel = DMA_CHANNEL_3, \ - .dma_tx.dma_irq = DMA2_Stream3_IRQn, \ +#ifndef SPI1_BUS_CONFIG +#define SPI1_BUS_CONFIG \ + { \ + .Instance = SPI1, \ + .bus_name = "spi1", \ } - -#define SPI1_DMA_RX_IRQHandler DMA2_Stream2_IRQHandler -#define SPI1_DMA_TX_IRQHandler DMA2_Stream3_IRQHandler -#endif +#endif /* SPI1_BUS_CONFIG */ +#endif /* BSP_USING_SPI1 */ + +#ifdef BSP_SPI1_TX_USING_DMA +#ifndef SPI1_TX_DMA_CONFIG +#define SPI1_TX_DMA_CONFIG \ + { \ + .dma_rcc = SPI1_TX_DMA_RCC, \ + .Instance = SPI1_TX_DMA_INSTANCE, \ + .channel = SPI1_TX_DMA_CHANNEL, \ + .dma_irq = SPI1_TX_DMA_IRQ, \ + } +#endif /* SPI1_TX_DMA_CONFIG */ +#endif /* BSP_SPI1_TX_USING_DMA */ + +#ifdef BSP_SPI1_RX_USING_DMA +#ifndef SPI1_RX_DMA_CONFIG +#define SPI1_RX_DMA_CONFIG \ + { \ + .dma_rcc = SPI1_RX_DMA_RCC, \ + .Instance = SPI1_RX_DMA_INSTANCE, \ + .channel = SPI1_RX_DMA_CHANNEL, \ + .dma_irq = SPI1_RX_DMA_IRQ, \ + } +#endif /* SPI1_RX_DMA_CONFIG */ +#endif /* BSP_SPI1_RX_USING_DMA */ #ifdef BSP_USING_SPI2 -#define SPI2_BUS_CONFIG \ - { \ - .Instance = SPI2, \ - .bus_name = "spi2", \ - .dma_rx.dma_rcc = RCC_AHB1ENR_DMA1EN, \ - .dma_tx.dma_rcc = RCC_AHB1ENR_DMA1EN, \ - .dma_rx.Instance = DMA1_Stream3, \ - .dma_rx.channel = DMA_CHANNEL_0, \ - .dma_rx.dma_irq = DMA1_Stream3_IRQn, \ - .dma_tx.Instance = DMA1_Stream4, \ - .dma_tx.channel = DMA_CHANNEL_0, \ - .dma_tx.dma_irq = DMA1_Stream4_IRQn, \ +#ifndef SPI2_BUS_CONFIG +#define SPI2_BUS_CONFIG \ + { \ + .Instance = SPI2, \ + .bus_name = "spi2", \ } - -#define SPI2_DMA_RX_IRQHandler DMA1_Stream3_IRQHandler -#define SPI2_DMA_TX_IRQHandler DMA1_Stream4_IRQHandler -#endif +#endif /* SPI2_BUS_CONFIG */ +#endif /* BSP_USING_SPI2 */ + +#ifdef BSP_SPI2_TX_USING_DMA +#ifndef SPI2_TX_DMA_CONFIG +#define SPI2_TX_DMA_CONFIG \ + { \ + .dma_rcc = SPI2_TX_DMA_RCC, \ + .Instance = SPI2_TX_DMA_INSTANCE, \ + .channel = SPI2_TX_DMA_CHANNEL, \ + .dma_irq = SPI2_TX_DMA_IRQ, \ + } +#endif /* SPI2_TX_DMA_CONFIG */ +#endif /* BSP_SPI2_TX_USING_DMA */ + +#ifdef BSP_SPI2_RX_USING_DMA +#ifndef SPI2_RX_DMA_CONFIG +#define SPI2_RX_DMA_CONFIG \ + { \ + .dma_rcc = SPI2_RX_DMA_RCC, \ + .Instance = SPI2_RX_DMA_INSTANCE, \ + .channel = SPI2_RX_DMA_CHANNEL, \ + .dma_irq = SPI2_RX_DMA_IRQ, \ + } +#endif /* SPI2_RX_DMA_CONFIG */ +#endif /* BSP_SPI2_RX_USING_DMA */ #ifdef BSP_USING_SPI3 -#define SPI3_BUS_CONFIG \ - { \ - .Instance = SPI3, \ - .bus_name = "spi3", \ - .dma_rx.dma_rcc = RCC_AHB1ENR_DMA1EN, \ - .dma_tx.dma_rcc = RCC_AHB1ENR_DMA1EN, \ - .dma_rx.Instance = DMA1_Stream0, \ - .dma_rx.channel = DMA_CHANNEL_0, \ - .dma_rx.dma_irq = DMA1_Stream0_IRQn, \ - .dma_tx.Instance = DMA1_Stream5, \ - .dma_tx.channel = DMA_CHANNEL_0, \ - .dma_tx.dma_irq = DMA1_Stream5_IRQn, \ +#ifndef SPI3_BUS_CONFIG +#define SPI3_BUS_CONFIG \ + { \ + .Instance = SPI3, \ + .bus_name = "spi3", \ } - -#define SPI3_DMA_RX_IRQHandler DMA1_Stream0_IRQHandler -#define SPI3_DMA_TX_IRQHandler DMA1_Stream5_IRQHandler -#endif +#endif /* SPI3_BUS_CONFIG */ +#endif /* BSP_USING_SPI3 */ + +#ifdef BSP_SPI3_TX_USING_DMA +#ifndef SPI3_TX_DMA_CONFIG +#define SPI3_TX_DMA_CONFIG \ + { \ + .dma_rcc = SPI3_TX_DMA_RCC, \ + .Instance = SPI3_TX_DMA_INSTANCE, \ + .channel = SPI3_TX_DMA_CHANNEL, \ + .dma_irq = SPI3_TX_DMA_IRQ, \ + } +#endif /* SPI3_TX_DMA_CONFIG */ +#endif /* BSP_SPI3_TX_USING_DMA */ + +#ifdef BSP_SPI3_RX_USING_DMA +#ifndef SPI3_RX_DMA_CONFIG +#define SPI3_RX_DMA_CONFIG \ + { \ + .dma_rcc = SPI3_RX_DMA_RCC, \ + .Instance = SPI3_RX_DMA_INSTANCE, \ + .channel = SPI3_RX_DMA_CHANNEL, \ + .dma_irq = SPI3_RX_DMA_IRQ, \ + } +#endif /* SPI3_RX_DMA_CONFIG */ +#endif /* BSP_SPI3_RX_USING_DMA */ #ifdef BSP_USING_SPI4 -#define SPI4_BUS_CONFIG \ - { \ - .Instance = SPI4, \ - .bus_name = "spi4", \ - .dma_rx.dma_rcc = RCC_AHB1ENR_DMA2EN, \ - .dma_tx.dma_rcc = RCC_AHB1ENR_DMA2EN, \ - .dma_rx.Instance = DMA2_Stream0, \ - .dma_rx.channel = DMA_CHANNEL_4, \ - .dma_rx.dma_irq = DMA2_Stream0_IRQn, \ - .dma_tx.Instance = DMA2_Stream1, \ - .dma_tx.channel = DMA_CHANNEL_4, \ - .dma_tx.dma_irq = DMA2_Stream1_IRQn, \ +#ifndef SPI4_BUS_CONFIG +#define SPI4_BUS_CONFIG \ + { \ + .Instance = SPI4, \ + .bus_name = "spi4", \ } - -#define SPI4_DMA_RX_IRQHandler DMA2_Stream0_IRQHandler -#define SPI4_DMA_TX_IRQHandler DMA2_Stream1_IRQHandler -#endif +#endif /* SPI4_BUS_CONFIG */ +#endif /* BSP_USING_SPI4 */ + +#ifdef BSP_SPI4_TX_USING_DMA +#ifndef SPI4_TX_DMA_CONFIG +#define SPI4_TX_DMA_CONFIG \ + { \ + .dma_rcc = SPI4_TX_DMA_RCC, \ + .Instance = SPI4_TX_DMA_INSTANCE, \ + .channel = SPI4_TX_DMA_CHANNEL, \ + .dma_irq = SPI4_TX_DMA_IRQ, \ + } +#endif /* SPI4_TX_DMA_CONFIG */ +#endif /* BSP_SPI4_TX_USING_DMA */ + +#ifdef BSP_SPI4_RX_USING_DMA +#ifndef SPI4_RX_DMA_CONFIG +#define SPI4_RX_DMA_CONFIG \ + { \ + .dma_rcc = SPI4_RX_DMA_RCC, \ + .Instance = SPI4_RX_DMA_INSTANCE, \ + .channel = SPI4_RX_DMA_CHANNEL, \ + .dma_irq = SPI4_RX_DMA_IRQ, \ + } +#endif /* SPI4_RX_DMA_CONFIG */ +#endif /* BSP_SPI4_RX_USING_DMA */ #ifdef BSP_USING_SPI5 -#define SPI5_BUS_CONFIG \ - { \ - .Instance = SPI5, \ - .bus_name = "spi5", \ - .dma_rx.dma_rcc = RCC_AHB1ENR_DMA2EN, \ - .dma_tx.dma_rcc = RCC_AHB1ENR_DMA2EN, \ - .dma_rx.Instance = DMA2_Stream3, \ - .dma_rx.channel = DMA_CHANNEL_2, \ - .dma_rx.dma_irq = DMA2_Stream3_IRQn, \ - .dma_tx.Instance = DMA2_Stream4, \ - .dma_tx.channel = DMA_CHANNEL_2, \ - .dma_tx.dma_irq = DMA2_Stream4_IRQn, \ +#ifndef SPI5_BUS_CONFIG +#define SPI5_BUS_CONFIG \ + { \ + .Instance = SPI5, \ + .bus_name = "spi5", \ } - -#define SPI5_DMA_RX_IRQHandler DMA2_Stream3_IRQHandler -#define SPI5_DMA_TX_IRQHandler DMA2_Stream4_IRQHandler -#endif +#endif /* SPI5_BUS_CONFIG */ +#endif /* BSP_USING_SPI5 */ + +#ifdef BSP_SPI5_TX_USING_DMA +#ifndef SPI5_TX_DMA_CONFIG +#define SPI5_TX_DMA_CONFIG \ + { \ + .dma_rcc = SPI5_TX_DMA_RCC, \ + .Instance = SPI5_TX_DMA_INSTANCE, \ + .channel = SPI5_TX_DMA_CHANNEL, \ + .dma_irq = SPI5_TX_DMA_IRQ, \ + } +#endif /* SPI5_TX_DMA_CONFIG */ +#endif /* BSP_SPI5_TX_USING_DMA */ + +#ifdef BSP_SPI5_RX_USING_DMA +#ifndef SPI5_RX_DMA_CONFIG +#define SPI5_RX_DMA_CONFIG \ + { \ + .dma_rcc = SPI5_RX_DMA_RCC, \ + .Instance = SPI5_RX_DMA_INSTANCE, \ + .channel = SPI5_RX_DMA_CHANNEL, \ + .dma_irq = SPI5_RX_DMA_IRQ, \ + } +#endif /* SPI5_RX_DMA_CONFIG */ +#endif /* BSP_SPI5_RX_USING_DMA */ #endif /*__SPI_CONFIG_H__ */ - - - diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f4/uart_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f4/uart_config.h index d8fab2c3613054554088aea6909e4c5bf1ca1d88..20dca9cee253e9aa01c271f8877794f0290bf0c3 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/f4/uart_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/f4/uart_config.h @@ -5,7 +5,8 @@ * * Change Logs: * Date Author Notes - * 2018-10-30 SummerGift change to new framework + * 2018-10-30 SummerGift first version + * 2019-01-03 zylx modify dma support */ #ifndef __UART_CONFIG_H__ @@ -14,78 +15,118 @@ #include #if defined(BSP_USING_UART1) -#define UART1_CONFIG \ - { \ - .name = "uart1", \ - .Instance = USART1, \ - .irq_type = USART1_IRQn, \ - .dma.stream_channel.Instance = DMA2_Stream5, \ - .dma.stream_channel.channel = DMA_CHANNEL_4, \ - .dma_rcc = RCC_AHB1ENR_DMA2EN, \ - .dma_irq = DMA2_Stream5_IRQn, \ +#ifndef UART1_CONFIG +#define UART1_CONFIG \ + { \ + .name = "uart1", \ + .Instance = USART1, \ + .irq_type = USART1_IRQn, \ } +#endif /* UART1_CONFIG */ +#endif /* BSP_USING_UART1 */ -#define USART1_RX_DMA_ISR DMA2_Stream5_IRQHandler -#endif +#if defined(BSP_UART1_RX_USING_DMA) +#ifndef UART1_DMA_CONFIG +#define UART1_DMA_CONFIG \ + { \ + .Instance = USART1_RX_DMA_INSTANCE, \ + .channel = USART1_RX_DMA_CHANNEL, \ + .dma_rcc = USART1_RX_DMA_RCC, \ + .dma_irq = USART1_RX_DMA_IRQ, \ + } +#endif /* UART1_DMA_CONFIG */ +#endif /* BSP_UART1_RX_USING_DMA */ #if defined(BSP_USING_UART2) -#define UART2_CONFIG \ - { \ - .name = "uart2", \ - .Instance = USART2, \ - .irq_type = USART2_IRQn, \ - .dma.stream_channel.Instance = DMA1_Stream5, \ - .dma.stream_channel.channel = DMA_CHANNEL_4, \ - .dma_rcc = RCC_AHB1ENR_DMA1EN, \ - .dma_irq = DMA1_Stream5_IRQn, \ +#ifndef UART2_CONFIG +#define UART2_CONFIG \ + { \ + .name = "uart2", \ + .Instance = USART2, \ + .irq_type = USART2_IRQn, \ } +#endif /* UART2_CONFIG */ +#endif /* BSP_USING_UART2 */ -#define USART2_RX_DMA_ISR DMA1_Stream5_IRQHandler -#endif +#if defined(BSP_UART2_RX_USING_DMA) +#ifndef UART2_DMA_CONFIG +#define UART2_DMA_CONFIG \ + { \ + .Instance = USART2_RX_DMA_INSTANCE, \ + .channel = USART2_RX_DMA_CHANNEL, \ + .dma_rcc = USART2_RX_DMA_RCC, \ + .dma_irq = USART2_RX_DMA_IRQ, \ + } +#endif /* UART2_DMA_CONFIG */ +#endif /* BSP_UART2_RX_USING_DMA */ #if defined(BSP_USING_UART3) -#define UART3_CONFIG \ - { \ - .name = "uart3", \ - .Instance = USART3, \ - .irq_type = USART3_IRQn, \ - .dma.stream_channel.Instance = DMA1_Stream1, \ - .dma.stream_channel.channel = DMA_CHANNEL_4, \ - .dma_rcc = RCC_AHB1ENR_DMA1EN, \ - .dma_irq = DMA1_Stream1_IRQn, \ +#ifndef UART3_CONFIG +#define UART3_CONFIG \ + { \ + .name = "uart3", \ + .Instance = USART3, \ + .irq_type = USART3_IRQn, \ } +#endif /* UART3_CONFIG */ +#endif /* BSP_USING_UART3 */ -#define USART3_RX_DMA_ISR DMA1_Stream1_IRQHandler -#endif +#if defined(BSP_UART3_RX_USING_DMA) +#ifndef UART3_DMA_CONFIG +#define UART3_DMA_CONFIG \ + { \ + .Instance = USART3_RX_DMA_INSTANCE, \ + .channel = USART3_RX_DMA_CHANNEL, \ + .dma_rcc = USART3_RX_DMA_RCC, \ + .dma_irq = USART3_RX_DMA_IRQ, \ + } +#endif /* UART3_DMA_CONFIG */ +#endif /* BSP_UART3_RX_USING_DMA */ #if defined(BSP_USING_UART4) -#define UART4_CONFIG \ - { \ - .name = "uart4", \ - .Instance = UART4, \ - .irq_type = UART4_IRQn, \ - .dma.stream_channel.Instance = DMA1_Stream2, \ - .dma.stream_channel.channel = DMA_CHANNEL_4, \ - .dma_rcc = RCC_AHB1ENR_DMA1EN, \ - .dma_irq = DMA1_Stream2_IRQn, \ +#ifndef UART4_CONFIG +#define UART4_CONFIG \ + { \ + .name = "uart4", \ + .Instance = UART4, \ + .irq_type = UART4_IRQn, \ } +#endif /* UART4_CONFIG */ +#endif /* BSP_USING_UART4 */ -#define USART4_RX_DMA_ISR DMA1_Stream2_IRQHandler -#endif +#if defined(BSP_UART4_RX_USING_DMA) +#ifndef UART4_DMA_CONFIG +#define UART4_DMA_CONFIG \ + { \ + .Instance = USART4_RX_DMA_INSTANCE, \ + .channel = USART4_RX_DMA_CHANNEL, \ + .dma_rcc = USART4_RX_DMA_RCC, \ + .dma_irq = USART4_RX_DMA_IRQ, \ + } +#endif /* UART4_DMA_CONFIG */ +#endif /* BSP_UART4_RX_USING_DMA */ #if defined(BSP_USING_UART5) -#define UART5_CONFIG \ - { \ - .name = "uart5", \ - .Instance = UART5, \ - .irq_type = UART5_IRQn, \ - .dma.stream_channel.Instance = DMA1_Stream0, \ - .dma.stream_channel.channel = DMA_CHANNEL_4, \ - .dma_rcc = RCC_AHB1ENR_DMA1EN, \ - .dma_irq = DMA1_Stream0_IRQn, \ +#ifndef UART5_CONFIG +#define UART5_CONFIG \ + { \ + .name = "uart5", \ + .Instance = UART5, \ + .irq_type = UART5_IRQn, \ } +#endif /* UART5_CONFIG */ +#endif /* BSP_USING_UART5 */ -#define USART5_RX_DMA_ISR DMA1_Stream0_IRQHandler -#endif +#if defined(BSP_UART5_RX_USING_DMA) +#ifndef UART5_DMA_CONFIG +#define UART5_DMA_CONFIG \ + { \ + .Instance = USART5_RX_DMA_INSTANCE, \ + .channel = USART5_RX_DMA_CHANNEL, \ + .dma_rcc = USART5_RX_DMA_RCC, \ + .dma_irq = USART5_RX_DMA_IRQ, \ + } +#endif /* UART5_DMA_CONFIG */ +#endif /* BSP_UART5_RX_USING_DMA */ #endif diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f7/qspi_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f7/qspi_config.h index 5e148aa2507df9ec4d605f99b8ca93693c4ff1f0..d69ab7aff9ea4bcaad23160cfe9171073856d998 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/f7/qspi_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/f7/qspi_config.h @@ -24,13 +24,13 @@ } #endif /* QSPI_BUS_CONFIG */ #endif /* BSP_USING_QSPI */ - + #ifdef BSP_QSPI_USING_DMA #ifndef QSPI_DMA_CONFIG #define QSPI_DMA_CONFIG \ { \ - .Instance = DMA2_Stream7, \ - .Init.Channel = DMA_CHANNEL_3, \ + .Instance = QSPI_DMA_INSTANCE, \ + .Init.Channel = QSPI_DMA_CHANNEL, \ .Init.Direction = DMA_PERIPH_TO_MEMORY, \ .Init.PeriphInc = DMA_PINC_DISABLE, \ .Init.MemInc = DMA_MINC_ENABLE, \ @@ -42,10 +42,7 @@ #endif /* QSPI_DMA_CONFIG */ #endif /* BSP_QSPI_USING_DMA */ -#define QSPI_DMA_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE() #define QSPI_IRQn QUADSPI_IRQn -#define QSPI_DMA_IRQn DMA2_Stream7_IRQn #define QSPI_IRQHandler QUADSPI_IRQHandler -#define QSPI_DMA_IRQHandler DMA2_Stream7_IRQHandler #endif /* __QSPI_CONFIG_H__ */ diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f7/spi_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f7/spi_config.h index 41c10756a06a3ba20fca10dab7e8b73fc4753144..ac18fcd015fae23c0daa0ccf634de3f267d34a08 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/f7/spi_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/f7/spi_config.h @@ -14,120 +14,173 @@ #include #ifdef BSP_USING_SPI1 -#define SPI1_BUS_CONFIG \ - { \ - .Instance = SPI1, \ - .bus_name = "spi1", \ - .dma_rx.dma_rcc = RCC_AHB1ENR_DMA2EN, \ - .dma_tx.dma_rcc = RCC_AHB1ENR_DMA2EN, \ - .dma_rx.Instance = DMA2_Stream2, \ - .dma_rx.channel = DMA_CHANNEL_3, \ - .dma_rx.dma_irq = DMA2_Stream2_IRQn, \ - .dma_tx.Instance = DMA2_Stream3, \ - .dma_tx.channel = DMA_CHANNEL_3, \ - .dma_tx.dma_irq = DMA2_Stream3_IRQn, \ +#ifndef SPI1_BUS_CONFIG +#define SPI1_BUS_CONFIG \ + { \ + .Instance = SPI1, \ + .bus_name = "spi1", \ } - -#define SPI1_DMA_RX_IRQHandler DMA2_Stream2_IRQHandler -#define SPI1_DMA_TX_IRQHandler DMA2_Stream3_IRQHandler -#endif +#endif /* SPI1_BUS_CONFIG */ +#endif /* BSP_USING_SPI1 */ + +#ifdef BSP_SPI1_TX_USING_DMA +#ifndef SPI1_TX_DMA_CONFIG +#define SPI1_TX_DMA_CONFIG \ + { \ + .dma_rcc = SPI1_TX_DMA_RCC, \ + .Instance = SPI1_TX_DMA_INSTANCE, \ + .channel = SPI1_TX_DMA_CHANNEL, \ + .dma_irq = SPI1_TX_DMA_IRQ, \ + } +#endif /* SPI1_TX_DMA_CONFIG */ +#endif /* BSP_SPI1_TX_USING_DMA */ + +#ifdef BSP_SPI1_RX_USING_DMA +#ifndef SPI1_RX_DMA_CONFIG +#define SPI1_RX_DMA_CONFIG \ + { \ + .dma_rcc = SPI1_RX_DMA_RCC, \ + .Instance = SPI1_RX_DMA_INSTANCE, \ + .channel = SPI1_RX_DMA_CHANNEL, \ + .dma_irq = SPI1_RX_DMA_IRQ, \ + } +#endif /* SPI1_RX_DMA_CONFIG */ +#endif /* BSP_SPI1_RX_USING_DMA */ #ifdef BSP_USING_SPI2 -#define SPI2_BUS_CONFIG \ - { \ - .Instance = SPI2, \ - .bus_name = "spi2", \ - .dma_rx.dma_rcc = RCC_AHB1ENR_DMA1EN, \ - .dma_tx.dma_rcc = RCC_AHB1ENR_DMA1EN, \ - .dma_rx.Instance = DMA1_Stream3, \ - .dma_rx.channel = DMA_CHANNEL_0, \ - .dma_rx.dma_irq = DMA1_Stream3_IRQn, \ - .dma_tx.Instance = DMA1_Stream4, \ - .dma_tx.channel = DMA_CHANNEL_0, \ - .dma_tx.dma_irq = DMA1_Stream4_IRQn, \ +#ifndef SPI2_BUS_CONFIG +#define SPI2_BUS_CONFIG \ + { \ + .Instance = SPI2, \ + .bus_name = "spi2", \ } - -#define SPI2_DMA_RX_IRQHandler DMA1_Stream3_IRQHandler -#define SPI2_DMA_TX_IRQHandler DMA1_Stream4_IRQHandler -#endif +#endif /* SPI2_BUS_CONFIG */ +#endif /* BSP_USING_SPI2 */ + +#ifdef BSP_SPI2_TX_USING_DMA +#ifndef SPI2_TX_DMA_CONFIG +#define SPI2_TX_DMA_CONFIG \ + { \ + .dma_rcc = SPI2_TX_DMA_RCC, \ + .Instance = SPI2_TX_DMA_INSTANCE, \ + .channel = SPI2_TX_DMA_CHANNEL, \ + .dma_irq = SPI2_TX_DMA_IRQ, \ + } +#endif /* SPI2_TX_DMA_CONFIG */ +#endif /* BSP_SPI2_TX_USING_DMA */ + +#ifdef BSP_SPI2_RX_USING_DMA +#ifndef SPI2_RX_DMA_CONFIG +#define SPI2_RX_DMA_CONFIG \ + { \ + .dma_rcc = SPI2_RX_DMA_RCC, \ + .Instance = SPI2_RX_DMA_INSTANCE, \ + .channel = SPI2_RX_DMA_CHANNEL, \ + .dma_irq = SPI2_RX_DMA_IRQ, \ + } +#endif /* SPI2_RX_DMA_CONFIG */ +#endif /* BSP_SPI2_RX_USING_DMA */ #ifdef BSP_USING_SPI3 -#define SPI3_BUS_CONFIG \ - { \ - .Instance = SPI3, \ - .bus_name = "spi3", \ - .dma_rx.dma_rcc = RCC_AHB1ENR_DMA1EN, \ - .dma_tx.dma_rcc = RCC_AHB1ENR_DMA1EN, \ - .dma_rx.Instance = DMA1_Stream0, \ - .dma_rx.channel = DMA_CHANNEL_0, \ - .dma_rx.dma_irq = DMA1_Stream0_IRQn, \ - .dma_tx.Instance = DMA1_Stream7, \ - .dma_tx.channel = DMA_CHANNEL_0, \ - .dma_tx.dma_irq = DMA1_Stream7_IRQn, \ +#ifndef SPI3_BUS_CONFIG +#define SPI3_BUS_CONFIG \ + { \ + .Instance = SPI3, \ + .bus_name = "spi3", \ } - -#define SPI3_DMA_RX_IRQHandler DMA1_Stream0_IRQHandler -#define SPI3_DMA_TX_IRQHandler DMA1_Stream7_IRQHandler -#endif +#endif /* SPI3_BUS_CONFIG */ +#endif /* BSP_USING_SPI3 */ + +#ifdef BSP_SPI3_TX_USING_DMA +#ifndef SPI3_TX_DMA_CONFIG +#define SPI3_TX_DMA_CONFIG \ + { \ + .dma_rcc = SPI3_TX_DMA_RCC, \ + .Instance = SPI3_TX_DMA_INSTANCE, \ + .channel = SPI3_TX_DMA_CHANNEL, \ + .dma_irq = SPI3_TX_DMA_IRQ, \ + } +#endif /* SPI3_TX_DMA_CONFIG */ +#endif /* BSP_SPI3_TX_USING_DMA */ + +#ifdef BSP_SPI3_RX_USING_DMA +#ifndef SPI3_RX_DMA_CONFIG +#define SPI3_RX_DMA_CONFIG \ + { \ + .dma_rcc = SPI3_RX_DMA_RCC, \ + .Instance = SPI3_RX_DMA_INSTANCE, \ + .channel = SPI3_RX_DMA_CHANNEL, \ + .dma_irq = SPI3_RX_DMA_IRQ, \ + } +#endif /* SPI3_RX_DMA_CONFIG */ +#endif /* BSP_SPI3_RX_USING_DMA */ #ifdef BSP_USING_SPI4 -#define SPI4_BUS_CONFIG \ - { \ - .Instance = SPI4, \ - .bus_name = "spi4", \ - .dma_rx.dma_rcc = RCC_AHB1ENR_DMA2EN, \ - .dma_tx.dma_rcc = RCC_AHB1ENR_DMA2EN, \ - .dma_rx.Instance = DMA2_Stream0, \ - .dma_rx.channel = DMA_CHANNEL_4, \ - .dma_rx.dma_irq = DMA2_Stream0_IRQn, \ - .dma_tx.Instance = DMA2_Stream1, \ - .dma_tx.channel = DMA_CHANNEL_4, \ - .dma_tx.dma_irq = DMA2_Stream1_IRQn, \ +#ifndef SPI4_BUS_CONFIG +#define SPI4_BUS_CONFIG \ + { \ + .Instance = SPI4, \ + .bus_name = "spi4", \ } - -#define SPI4_DMA_RX_IRQHandler DMA2_Stream0_IRQHandler -#define SPI4_DMA_TX_IRQHandler DMA2_Stream1_IRQHandler -#endif +#endif /* SPI4_BUS_CONFIG */ +#endif /* BSP_USING_SPI4 */ + +#ifdef BSP_SPI4_TX_USING_DMA +#ifndef SPI4_TX_DMA_CONFIG +#define SPI4_TX_DMA_CONFIG \ + { \ + .dma_rcc = SPI4_TX_DMA_RCC, \ + .Instance = SPI4_TX_DMA_INSTANCE, \ + .channel = SPI4_TX_DMA_CHANNEL, \ + .dma_irq = SPI4_TX_DMA_IRQ, \ + } +#endif /* SPI4_TX_DMA_CONFIG */ +#endif /* BSP_SPI4_TX_USING_DMA */ + +#ifdef BSP_SPI4_RX_USING_DMA +#ifndef SPI4_RX_DMA_CONFIG +#define SPI4_RX_DMA_CONFIG \ + { \ + .dma_rcc = SPI4_RX_DMA_RCC, \ + .Instance = SPI4_RX_DMA_INSTANCE, \ + .channel = SPI4_RX_DMA_CHANNEL, \ + .dma_irq = SPI4_RX_DMA_IRQ, \ + } +#endif /* SPI4_RX_DMA_CONFIG */ +#endif /* BSP_SPI4_RX_USING_DMA */ #ifdef BSP_USING_SPI5 -#define SPI5_BUS_CONFIG \ - { \ - .Instance = SPI5, \ - .bus_name = "spi5", \ - .dma_rx.dma_rcc = RCC_AHB1ENR_DMA2EN, \ - .dma_tx.dma_rcc = RCC_AHB1ENR_DMA2EN, \ - .dma_rx.Instance = DMA2_Stream3, \ - .dma_rx.channel = DMA_CHANNEL_2, \ - .dma_rx.dma_irq = DMA2_Stream3_IRQn, \ - .dma_tx.Instance = DMA2_Stream4, \ - .dma_tx.channel = DMA_CHANNEL_2, \ - .dma_tx.dma_irq = DMA2_Stream4_IRQn, \ +#ifndef SPI5_BUS_CONFIG +#define SPI5_BUS_CONFIG \ + { \ + .Instance = SPI5, \ + .bus_name = "spi5", \ } - -#define SPI5_DMA_RX_IRQHandler DMA2_Stream3_IRQHandler -#define SPI5_DMA_TX_IRQHandler DMA2_Stream4_IRQHandler -#endif - -#ifdef BSP_USING_SPI6 -#define SPI5_BUS_CONFIG \ - { \ - .Instance = SPI6, \ - .bus_name = "spi6", \ - .dma_rx.dma_rcc = RCC_AHB1ENR_DMA2EN, \ - .dma_tx.dma_rcc = RCC_AHB1ENR_DMA2EN, \ - .dma_rx.Instance = DMA2_Stream6, \ - .dma_rx.channel = DMA_CHANNEL_1, \ - .dma_rx.dma_irq = DMA2_Stream6_IRQn, \ - .dma_tx.Instance = DMA2_Stream5, \ - .dma_tx.channel = DMA_CHANNEL_1, \ - .dma_tx.dma_irq = DMA2_Stream5_IRQn, \ +#endif /* SPI5_BUS_CONFIG */ +#endif /* BSP_USING_SPI5 */ + +#ifdef BSP_SPI5_TX_USING_DMA +#ifndef SPI5_TX_DMA_CONFIG +#define SPI5_TX_DMA_CONFIG \ + { \ + .dma_rcc = SPI5_TX_DMA_RCC, \ + .Instance = SPI5_TX_DMA_INSTANCE, \ + .channel = SPI5_TX_DMA_CHANNEL, \ + .dma_irq = SPI5_TX_DMA_IRQ, \ } - -#define SPI6_DMA_RX_IRQHandler DMA2_Stream6_IRQHandler -#define SPI6_DMA_TX_IRQHandler DMA2_Stream5_IRQHandler -#endif +#endif /* SPI5_TX_DMA_CONFIG */ +#endif /* BSP_SPI5_TX_USING_DMA */ + +#ifdef BSP_SPI5_RX_USING_DMA +#ifndef SPI5_RX_DMA_CONFIG +#define SPI5_RX_DMA_CONFIG \ + { \ + .dma_rcc = SPI5_RX_DMA_RCC, \ + .Instance = SPI5_RX_DMA_INSTANCE, \ + .channel = SPI5_RX_DMA_CHANNEL, \ + .dma_irq = SPI5_RX_DMA_IRQ, \ + } +#endif /* SPI5_RX_DMA_CONFIG */ +#endif /* BSP_SPI5_RX_USING_DMA */ #endif /*__SPI_CONFIG_H__ */ - - - diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f7/uart_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f7/uart_config.h index d8fab2c3613054554088aea6909e4c5bf1ca1d88..ae343a1621fefa344c1811938e83a5fad938cc99 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/f7/uart_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/f7/uart_config.h @@ -5,7 +5,8 @@ * * Change Logs: * Date Author Notes - * 2018-10-30 SummerGift change to new framework + * 2018-10-30 SummerGift first version + * 2019-01-05 zylx modify dma support */ #ifndef __UART_CONFIG_H__ @@ -14,78 +15,118 @@ #include #if defined(BSP_USING_UART1) -#define UART1_CONFIG \ - { \ - .name = "uart1", \ - .Instance = USART1, \ - .irq_type = USART1_IRQn, \ - .dma.stream_channel.Instance = DMA2_Stream5, \ - .dma.stream_channel.channel = DMA_CHANNEL_4, \ - .dma_rcc = RCC_AHB1ENR_DMA2EN, \ - .dma_irq = DMA2_Stream5_IRQn, \ +#ifndef UART1_CONFIG +#define UART1_CONFIG \ + { \ + .name = "uart1", \ + .Instance = USART1, \ + .irq_type = USART1_IRQn, \ } +#endif /* UART1_CONFIG */ +#endif /* BSP_USING_UART1 */ -#define USART1_RX_DMA_ISR DMA2_Stream5_IRQHandler -#endif +#if defined(BSP_UART1_RX_USING_DMA) +#ifndef UART1_DMA_CONFIG +#define UART1_DMA_CONFIG \ + { \ + .Instance = USART1_RX_DMA_INSTANCE, \ + .channel = USART1_RX_DMA_CHANNEL, \ + .dma_rcc = USART1_RX_DMA_RCC, \ + .dma_irq = USART1_RX_DMA_IRQ, \ + } +#endif /* UART1_DMA_CONFIG */ +#endif /* BSP_UART1_RX_USING_DMA */ #if defined(BSP_USING_UART2) -#define UART2_CONFIG \ - { \ - .name = "uart2", \ - .Instance = USART2, \ - .irq_type = USART2_IRQn, \ - .dma.stream_channel.Instance = DMA1_Stream5, \ - .dma.stream_channel.channel = DMA_CHANNEL_4, \ - .dma_rcc = RCC_AHB1ENR_DMA1EN, \ - .dma_irq = DMA1_Stream5_IRQn, \ +#ifndef UART2_CONFIG +#define UART2_CONFIG \ + { \ + .name = "uart2", \ + .Instance = USART2, \ + .irq_type = USART2_IRQn, \ } +#endif /* UART2_CONFIG */ +#endif /* BSP_USING_UART2 */ -#define USART2_RX_DMA_ISR DMA1_Stream5_IRQHandler -#endif +#if defined(BSP_UART2_RX_USING_DMA) +#ifndef UART2_DMA_CONFIG +#define UART2_DMA_CONFIG \ + { \ + .Instance = USART2_RX_DMA_INSTANCE, \ + .channel = USART2_RX_DMA_CHANNEL, \ + .dma_rcc = USART2_RX_DMA_RCC, \ + .dma_irq = USART2_RX_DMA_IRQ, \ + } +#endif /* UART2_DMA_CONFIG */ +#endif /* BSP_UART2_RX_USING_DMA */ #if defined(BSP_USING_UART3) -#define UART3_CONFIG \ - { \ - .name = "uart3", \ - .Instance = USART3, \ - .irq_type = USART3_IRQn, \ - .dma.stream_channel.Instance = DMA1_Stream1, \ - .dma.stream_channel.channel = DMA_CHANNEL_4, \ - .dma_rcc = RCC_AHB1ENR_DMA1EN, \ - .dma_irq = DMA1_Stream1_IRQn, \ +#ifndef UART3_CONFIG +#define UART3_CONFIG \ + { \ + .name = "uart3", \ + .Instance = USART3, \ + .irq_type = USART3_IRQn, \ } +#endif /* UART3_CONFIG */ +#endif /* BSP_USING_UART3 */ -#define USART3_RX_DMA_ISR DMA1_Stream1_IRQHandler -#endif +#if defined(BSP_UART3_RX_USING_DMA) +#ifndef UART3_DMA_CONFIG +#define UART3_DMA_CONFIG \ + { \ + .Instance = USART3_RX_DMA_INSTANCE, \ + .channel = USART3_RX_DMA_CHANNEL, \ + .dma_rcc = USART3_RX_DMA_RCC, \ + .dma_irq = USART3_RX_DMA_IRQ, \ + } +#endif /* UART3_DMA_CONFIG */ +#endif /* BSP_UART3_RX_USING_DMA */ #if defined(BSP_USING_UART4) -#define UART4_CONFIG \ - { \ - .name = "uart4", \ - .Instance = UART4, \ - .irq_type = UART4_IRQn, \ - .dma.stream_channel.Instance = DMA1_Stream2, \ - .dma.stream_channel.channel = DMA_CHANNEL_4, \ - .dma_rcc = RCC_AHB1ENR_DMA1EN, \ - .dma_irq = DMA1_Stream2_IRQn, \ +#ifndef UART4_CONFIG +#define UART4_CONFIG \ + { \ + .name = "uart4", \ + .Instance = UART4, \ + .irq_type = UART4_IRQn, \ } +#endif /* UART4_CONFIG */ +#endif /* BSP_USING_UART4 */ -#define USART4_RX_DMA_ISR DMA1_Stream2_IRQHandler -#endif +#if defined(BSP_UART4_RX_USING_DMA) +#ifndef UART4_DMA_CONFIG +#define UART4_DMA_CONFIG \ + { \ + .Instance = USART4_RX_DMA_INSTANCE, \ + .channel = USART4_RX_DMA_CHANNEL, \ + .dma_rcc = USART4_RX_DMA_RCC, \ + .dma_irq = USART4_RX_DMA_IRQ, \ + } +#endif /* UART4_DMA_CONFIG */ +#endif /* BSP_UART4_RX_USING_DMA */ #if defined(BSP_USING_UART5) -#define UART5_CONFIG \ - { \ - .name = "uart5", \ - .Instance = UART5, \ - .irq_type = UART5_IRQn, \ - .dma.stream_channel.Instance = DMA1_Stream0, \ - .dma.stream_channel.channel = DMA_CHANNEL_4, \ - .dma_rcc = RCC_AHB1ENR_DMA1EN, \ - .dma_irq = DMA1_Stream0_IRQn, \ +#ifndef UART5_CONFIG +#define UART5_CONFIG \ + { \ + .name = "uart5", \ + .Instance = UART5, \ + .irq_type = UART5_IRQn, \ } +#endif /* UART5_CONFIG */ +#endif /* BSP_USING_UART5 */ -#define USART5_RX_DMA_ISR DMA1_Stream0_IRQHandler -#endif +#if defined(BSP_UART5_RX_USING_DMA) +#ifndef UART5_DMA_CONFIG +#define UART5_DMA_CONFIG \ + { \ + .Instance = USART5_RX_DMA_INSTANCE, \ + .channel = USART5_RX_DMA_CHANNEL, \ + .dma_rcc = USART5_RX_DMA_RCC, \ + .dma_irq = USART5_RX_DMA_IRQ, \ + } +#endif /* UART5_DMA_CONFIG */ +#endif /* BSP_UART5_RX_USING_DMA */ #endif diff --git a/bsp/stm32/libraries/HAL_Drivers/config/l4/qspi_config.h b/bsp/stm32/libraries/HAL_Drivers/config/l4/qspi_config.h index 93a018ac85acb5ded895c539f5c05901c265c134..ae968c0cfc71647577fe6c462188b8e77dd4a8a2 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/l4/qspi_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/l4/qspi_config.h @@ -29,8 +29,8 @@ #ifndef QSPI_DMA_CONFIG #define QSPI_DMA_CONFIG \ { \ - .Instance = DMA1_Channel5, \ - .Init.Request = DMA_REQUEST_5, \ + .Instance = QSPI_DMA_INSTANCE, \ + .Init.Request = QSPI_DMA_CHANNEL, \ .Init.Direction = DMA_PERIPH_TO_MEMORY, \ .Init.PeriphInc = DMA_PINC_DISABLE, \ .Init.MemInc = DMA_MINC_ENABLE, \ @@ -42,10 +42,7 @@ #endif /* QSPI_DMA_CONFIG */ #endif /* BSP_QSPI_USING_DMA */ -#define QSPI_DMA_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE() #define QSPI_IRQn QUADSPI_IRQn -#define QSPI_DMA_IRQn DMA1_Channel5_IRQn #define QSPI_IRQHandler QUADSPI_IRQHandler -#define QSPI_DMA_IRQHandler DMA1_Channel5_IRQHandler #endif /* __QSPI_CONFIG_H__ */ diff --git a/bsp/stm32/libraries/HAL_Drivers/config/l4/spi_config.h b/bsp/stm32/libraries/HAL_Drivers/config/l4/spi_config.h index 054f55ff7792571c903616b3f34ced1470844996..4a595cd9ff7f51e2afb57f09d63aa603621de9d1 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/l4/spi_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/l4/spi_config.h @@ -14,22 +14,38 @@ #include #ifdef BSP_USING_SPI1 -#define SPI1_BUS_CONFIG \ - { \ - .Instance = SPI1, \ - .bus_name = "spi1", \ - .dma_rx.dma_rcc = RCC_AHB1ENR_DMA1EN, \ - .dma_tx.dma_rcc = RCC_AHB1ENR_DMA1EN, \ - .dma_rx.Instance = DMA1_Channel2, \ - .dma_rx.request = DMA_REQUEST_1, \ - .dma_rx.dma_irq = DMA1_Channel2_IRQn, \ - .dma_tx.Instance = DMA1_Channel3, \ - .dma_tx.request = DMA_REQUEST_1, \ - .dma_tx.dma_irq = DMA1_Channel3_IRQn, \ +#ifndef SPI1_BUS_CONFIG +#define SPI1_BUS_CONFIG \ + { \ + .Instance = SPI1, \ + .bus_name = "spi1", \ } -#define SPI1_DMA_RX_IRQHandler DMA1_Channel2_IRQHandler -#define SPI1_DMA_TX_IRQHandler DMA1_Channel3_IRQHandler -#endif +#endif /* SPI1_BUS_CONFIG */ +#endif /* BSP_USING_SPI1 */ + +#ifdef BSP_SPI1_TX_USING_DMA +#ifndef SPI1_TX_DMA_CONFIG +#define SPI1_TX_DMA_CONFIG \ + { \ + .dma_rcc = SPI1_TX_DMA_RCC, \ + .Instance = SPI1_TX_DMA_INSTANCE, \ + .request = SPI1_TX_DMA_REQUEST, \ + .dma_irq = SPI1_TX_DMA_IRQ, \ + } +#endif /* SPI1_TX_DMA_CONFIG */ +#endif /* BSP_SPI1_TX_USING_DMA */ + +#ifdef BSP_SPI1_RX_USING_DMA +#ifndef SPI1_RX_DMA_CONFIG +#define SPI1_RX_DMA_CONFIG \ + { \ + .dma_rcc = SPI1_RX_DMA_RCC, \ + .Instance = SPI1_RX_DMA_INSTANCE, \ + .request = SPI1_RX_DMA_REQUEST, \ + .dma_irq = SPI1_RX_DMA_IRQ, \ + } +#endif /* SPI1_RX_DMA_CONFIG */ +#endif /* BSP_SPI1_RX_USING_DMA */ #ifdef BSP_USING_SPI2 #define SPI2_BUS_CONFIG \ @@ -45,8 +61,7 @@ .dma_tx.request = DMA_REQUEST_1, \ .dma_tx.dma_irq = DMA1_Channel5_IRQn, \ } -#define SPI2_DMA_RX_IRQHandler DMA1_Channel4_IRQHandler -#define SPI2_DMA_TX_IRQHandler DMA1_Channel5_IRQHandler + #endif #ifdef BSP_USING_SPI3 @@ -63,8 +78,7 @@ .dma_tx.request = DMA_REQUEST_3, \ .dma_tx.dma_irq = DMA2_Channel2_IRQn, \ } -#define SPI3_DMA_RX_IRQHandler DMA2_Channel1_IRQHandler -#define SPI3_DMA_TX_IRQHandler DMA2_Channel2_IRQHandler + #endif #endif /*__SPI_CONFIG_H__ */ diff --git a/bsp/stm32/libraries/HAL_Drivers/config/l4/uart_config.h b/bsp/stm32/libraries/HAL_Drivers/config/l4/uart_config.h index 46d5414f55ab017f6382c65108ca130651d44cf4..0b27ff77c80c8d4a0d4b06f234efeec7f767d15a 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/l4/uart_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/l4/uart_config.h @@ -14,35 +14,49 @@ #include #if defined(BSP_USING_UART1) - -#define UART1_CONFIG \ - { \ - .name = "uart1", \ - .Instance = USART1, \ - .irq_type = USART1_IRQn, \ - .dma.channel_request.Instance = DMA2_Channel7, \ - .dma.channel_request.request = DMA_REQUEST_2, \ - .dma_rcc = RCC_AHB1ENR_DMA2EN, \ - .dma_irq = DMA2_Channel7_IRQn, \ +#ifndef UART1_CONFIG +#define UART1_CONFIG \ + { \ + .name = "uart1", \ + .Instance = USART1, \ + .irq_type = USART1_IRQn, \ } - -#define USART1_RX_DMA_ISR DMA2_Channel7_IRQHandler -#endif - +#endif /* UART1_CONFIG */ +#endif /* BSP_USING_UART1 */ + +#if defined(BSP_UART1_RX_USING_DMA) +#ifndef UART1_DMA_CONFIG +#define UART1_DMA_CONFIG \ + { \ + .Instance = USART1_RX_DMA_INSTANCE, \ + .request = USART1_RX_DMA_REQUEST, \ + .dma_rcc = USART1_RX_DMA_RCC, \ + .dma_irq = USART1_RX_DMA_IRQ, \ + } +#endif /* UART1_DMA_CONFIG */ +#endif /* BSP_UART1_RX_USING_DMA */ + #if defined(BSP_USING_UART2) - -#define UART2_CONFIG \ - { \ - .name = "uart2", \ - .Instance = USART2, \ - .irq_type = USART2_IRQn, \ - .dma.channel_request.Instance = DMA1_Channel6, \ - .dma.channel_request.request = DMA_REQUEST_2, \ - .dma_rcc = RCC_AHB1SMENR_DMA1SMEN, \ - .dma_irq = DMA1_Channel6_IRQn, \ +#ifndef UART2_CONFIG +#define UART2_CONFIG \ + { \ + .name = "uart2", \ + .Instance = USART2, \ + .irq_type = USART2_IRQn, \ } - -#define USART2_RX_DMA_ISR DMA1_Channel6_IRQHandler -#endif +#endif /* UART2_CONFIG */ +#endif /* BSP_USING_UART2 */ + +#if defined(BSP_UART2_RX_USING_DMA) +#ifndef UART2_DMA_CONFIG +#define UART2_DMA_CONFIG \ + { \ + .Instance = USART2_RX_DMA_INSTANCE, \ + .request = USART2_RX_DMA_REQUEST, \ + .dma_rcc = USART2_RX_DMA_RCC, \ + .dma_irq = USART2_RX_DMA_IRQ, \ + } +#endif /* UART2_DMA_CONFIG */ +#endif /* BSP_UART2_RX_USING_DMA */ #endif diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_config.h b/bsp/stm32/libraries/HAL_Drivers/drv_config.h index 1046b44c0947574e6c1eeb944a6abdc53ff89eef..214552398ed50d9ed86a5fa959684cb79e8e5201 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/drv_config.h @@ -15,12 +15,14 @@ #include #if defined(SOC_SERIES_STM32F0) +#include "f0/dma_config.h" #include "f0/uart_config.h" #include "f0/spi_config.h" #include "f0/tim_config.h" #include "f0/pwm_config.h" #include "f0/adc_config.h" #elif defined(SOC_SERIES_STM32F1) +#include "f1/dma_config.h" #include "f1/uart_config.h" #include "f1/spi_config.h" #include "f1/adc_config.h" @@ -28,6 +30,7 @@ #include "f1/sdio_config.h" #include "f1/pwm_config.h" #elif defined(SOC_SERIES_STM32F4) +#include "f4/dma_config.h" #include "f4/uart_config.h" #include "f4/spi_config.h" #include "f4/adc_config.h" @@ -35,6 +38,7 @@ #include "f4/sdio_config.h" #include "f4/pwm_config.h" #elif defined(SOC_SERIES_STM32F7) +#include "f7/dma_config.h" #include "f7/uart_config.h" #include "f7/spi_config.h" #include "f7/qspi_config.h" @@ -43,6 +47,7 @@ #include "f7/sdio_config.h" #include "f7/pwm_config.h" #elif defined(SOC_SERIES_STM32L4) +#include "l4/dma_config.h" #include "l4/uart_config.h" #include "l4/spi_config.h" #include "l4/qspi_config.h" diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_dma.h b/bsp/stm32/libraries/HAL_Drivers/drv_dma.h index 4c266eafce4f05ac56196296a8c162e4cbb6df6a..b56cb1e94115ec38a1829fcb98921c5d7d1bda24 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_dma.h +++ b/bsp/stm32/libraries/HAL_Drivers/drv_dma.h @@ -5,7 +5,7 @@ * * Change Logs: * Date Author Notes - * 2018-11-10 SummerGift change to new framework + * 2018-11-10 SummerGift first version */ #ifndef __DRV_DMA_H_ @@ -16,7 +16,7 @@ #include #include -#if defined(SOC_SERIES_STM32F0) || (SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L4) +#if defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L4) #define DMA_INSTANCE_TYPE DMA_Channel_TypeDef #elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) #define DMA_INSTANCE_TYPE DMA_Stream_TypeDef @@ -36,5 +36,4 @@ struct dma_config { #endif }; - #endif /*__DRV_DMA_H_ */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_qspi.c b/bsp/stm32/libraries/HAL_Drivers/drv_qspi.c index 95b7cf10ad55517fac4a6662ae770ae67bad6b3b..6b54ad2c7aef4d7cac5ff45ff54f745ed8413a2c 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_qspi.c +++ b/bsp/stm32/libraries/HAL_Drivers/drv_qspi.c @@ -92,11 +92,19 @@ static int stm32_qspi_init(struct rt_qspi_device *device, struct rt_qspi_configu /* QSPI interrupts must be enabled when using the HAL_QSPI_Receive_DMA */ HAL_NVIC_SetPriority(QSPI_IRQn, 0, 0); HAL_NVIC_EnableIRQ(QSPI_IRQn); - HAL_NVIC_SetPriority(QSPI_DMA_IRQn, 0, 0); - HAL_NVIC_EnableIRQ(QSPI_DMA_IRQn); + HAL_NVIC_SetPriority(QSPI_DMA_IRQ, 0, 0); + HAL_NVIC_EnableIRQ(QSPI_DMA_IRQ); /* init QSPI DMA */ - QSPI_DMA_CLK_ENABLE; + if(QSPI_DMA_RCC == RCC_AHB1ENR_DMA1EN) + { + __HAL_RCC_DMA1_CLK_ENABLE(); + } + else + { + __HAL_RCC_DMA2_CLK_ENABLE(); + } + HAL_DMA_DeInit(qspi_bus->QSPI_Handler.hdma); DMA_HandleTypeDef hdma_quadspi_config = QSPI_DMA_CONFIG; qspi_bus->hdma_quadspi = hdma_quadspi_config; diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_spi.c b/bsp/stm32/libraries/HAL_Drivers/drv_spi.c index fd70be7d2b43a05d845d1a03c636e3b5f21ca92e..033cd2859fd17e60ba16f641f06008fea0f3a358 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_spi.c +++ b/bsp/stm32/libraries/HAL_Drivers/drv_spi.c @@ -5,15 +5,16 @@ * * Change Logs: * Date Author Notes - * 2018-11-5 SummerGift change to new framework + * 2018-11-5 SummerGift first version * 2018-12-11 greedyhao Porting for stm32f7xx + * 2019-01-03 zylx modify DMA initialization and spixfer function */ #include "board.h" #ifdef RT_USING_SPI -#if defined(BSP_USING_SPI1) || defined(BSP_USING_SPI2) || defined(BSP_USING_SPI3) || defined(BSP_USING_SPI4) || defined(BSP_USING_SPI5) || defined(BSP_USING_SPI6) +#if defined(BSP_USING_SPI1) || defined(BSP_USING_SPI2) || defined(BSP_USING_SPI3) || defined(BSP_USING_SPI4) || defined(BSP_USING_SPI5) || defined(BSP_USING_SPI6) /* this driver can be disabled at menuconfig → RT-Thread Components → Device Drivers */ #include "drv_spi.h" @@ -72,7 +73,7 @@ static struct stm32_spi_config spi_config[] = #endif }; -static struct stm32_spi spi_bus_obj[sizeof(spi_config) / sizeof(spi_config[0])]; +static struct stm32_spi spi_bus_obj[sizeof(spi_config) / sizeof(spi_config[0])] = {0}; static rt_err_t stm32_spi_init(struct stm32_spi *spi_drv, struct rt_spi_configuration *cfg) { @@ -201,6 +202,10 @@ static rt_err_t stm32_spi_init(struct stm32_spi *spi_drv, struct rt_spi_configur spi_handle->Init.TIMode = SPI_TIMODE_DISABLE; spi_handle->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; spi_handle->State = HAL_SPI_STATE_RESET; +#ifdef SOC_SERIES_STM32L4 + spi_handle->Init.NSSPMode = SPI_NSS_PULSE_DISABLE; +#endif + if (HAL_SPI_Init(spi_handle) != HAL_OK) { return RT_EIO; @@ -210,204 +215,112 @@ static rt_err_t stm32_spi_init(struct stm32_spi *spi_drv, struct rt_spi_configur SET_BIT(spi_handle->Instance->CR2, SPI_RXFIFO_THRESHOLD_HF); #endif - __HAL_SPI_ENABLE(spi_handle); - - LOG_D("%s init done", spi_drv->config->bus_name); - return RT_EOK; -} - -#ifdef BSP_SPI_USING_DMA -static uint8_t dummy = 0xFF; -static void spi_dma_transfer_prepare(struct rt_spi_bus * spi_bus, struct rt_spi_message* message) -{ - struct stm32_spi *spi_drv = rt_container_of(spi_bus, struct stm32_spi, spi_bus); - - DMA_HandleTypeDef * hdma_tx = (DMA_HandleTypeDef *)&spi_drv->dma.handle_tx; - DMA_HandleTypeDef * hdma_rx = (DMA_HandleTypeDef *)&spi_drv->dma.handle_rx; - - HAL_DMA_DeInit(hdma_tx); - HAL_DMA_DeInit(hdma_rx); - - /* - * Check if the DMA Stream is disabled before enabling it. - * Note that this step is useful when the same Stream is used multiple times. - */ -#if defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) - while (hdma_tx->Instance->CR & DMA_SxCR_EN); - while (hdma_rx->Instance->CR & DMA_SxCR_EN); -#endif - - if(message->recv_buf != RT_NULL) + /* DMA configuration */ + if (spi_drv->spi_dma_flag & SPI_USING_RX_DMA_FLAG) { - hdma_rx->Init.MemInc = DMA_MINC_ENABLE; - } - else - { - message->recv_buf = &dummy; - hdma_rx->Init.MemInc = DMA_MINC_DISABLE; - } - HAL_DMA_Init(hdma_rx); + HAL_DMA_Init(&spi_drv->dma.handle_rx); - __HAL_LINKDMA(&spi_drv->handle, hdmarx, spi_drv->dma.handle_rx); + __HAL_LINKDMA(&spi_drv->handle, hdmarx, spi_drv->dma.handle_rx); - if(message->send_buf != RT_NULL) - { - hdma_tx->Init.MemInc = DMA_MINC_ENABLE; + /* NVIC configuration for DMA transfer complete interrupt */ + HAL_NVIC_SetPriority(spi_drv->config->dma_rx->dma_irq, 0, 0); + HAL_NVIC_EnableIRQ(spi_drv->config->dma_rx->dma_irq); } - else + + if (spi_drv->spi_dma_flag & SPI_USING_TX_DMA_FLAG) { - dummy = 0xFF; - message->send_buf = &dummy; - hdma_tx->Init.MemInc = DMA_MINC_DISABLE; - } - HAL_DMA_Init(hdma_tx); + HAL_DMA_Init(&spi_drv->dma.handle_tx); - /* link DMA with SPI */ - __HAL_LINKDMA(&spi_drv->handle, hdmatx, spi_drv->dma.handle_tx); + __HAL_LINKDMA(&spi_drv->handle, hdmatx, spi_drv->dma.handle_tx); - LOG_D("%s RX Instance: %x, TX Instance: %x", spi_drv->config->bus_name, hdma_rx->Instance, hdma_tx->Instance); - LOG_D("%s dma config done, TX dma_irq number: %d, RX dma_irq number: %d", - spi_drv->config->bus_name, - spi_drv->config->dma_tx.dma_irq, - spi_drv->config->dma_rx.dma_irq); + /* NVIC configuration for DMA transfer complete interrupt */ + HAL_NVIC_SetPriority(spi_drv->config->dma_tx->dma_irq, 0, 1); + HAL_NVIC_EnableIRQ(spi_drv->config->dma_tx->dma_irq); + } - /* NVIC configuration for DMA transfer complete interrupt*/ - HAL_NVIC_SetPriority(spi_drv->config->dma_tx.dma_irq, 0, 1); - HAL_NVIC_EnableIRQ(spi_drv->config->dma_tx.dma_irq); + __HAL_SPI_ENABLE(spi_handle); - /* NVIC configuration for DMA transfer complete interrupt*/ - HAL_NVIC_SetPriority(spi_drv->config->dma_rx.dma_irq, 0, 0); - HAL_NVIC_EnableIRQ(spi_drv->config->dma_rx.dma_irq); + LOG_D("%s init done", spi_drv->config->bus_name); + return RT_EOK; } -#endif static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message *message) { + HAL_StatusTypeDef state; + RT_ASSERT(device != RT_NULL); RT_ASSERT(device->bus != RT_NULL); RT_ASSERT(device->bus->parent.user_data != RT_NULL); RT_ASSERT(message != RT_NULL); struct stm32_spi *spi_drv = rt_container_of(device->bus, struct stm32_spi, spi_bus); - SPI_HandleTypeDef * spi_handle = &spi_drv->handle; + SPI_HandleTypeDef *spi_handle = &spi_drv->handle; struct stm32_hw_spi_cs *cs = device->parent.user_data; - rt_int32_t length = message->length; - rt_int32_t data_width = spi_drv->cfg->data_width; if (message->cs_take) { HAL_GPIO_WritePin(cs->GPIOx, cs->GPIO_Pin, GPIO_PIN_RESET); } -#ifdef BSP_SPI_USING_DMA - if(message->length > 32) + LOG_D("%s transfer prepare and start", spi_drv->config->bus_name); + LOG_D("%s sendbuf: %X, recvbuf: %X, length: %d", + spi_drv->config->bus_name, + (uint32_t)message->send_buf, + (uint32_t)message->recv_buf, message->length); + + if (message->length) { - if(data_width <= 8) + /* start once data exchange in DMA mode */ + if (message->send_buf && message->recv_buf) + { + if ((spi_drv->spi_dma_flag & SPI_USING_TX_DMA_FLAG) && (spi_drv->spi_dma_flag & SPI_USING_RX_DMA_FLAG)) + { + state = HAL_SPI_TransmitReceive_DMA(spi_handle, (uint8_t *)message->send_buf, (uint8_t *)message->recv_buf, message->length); + }else + { + state = HAL_SPI_TransmitReceive(spi_handle, (uint8_t *)message->send_buf, (uint8_t *)message->recv_buf, message->length, 1000); + } + } + else if (message->send_buf) { - HAL_StatusTypeDef state; - LOG_D("%s dma transfer prepare and start", spi_drv->config->bus_name); - LOG_D("%s sendbuf: %X, recvbuf: %X, length: %d", - spi_drv->config->bus_name, - (uint32_t)message->send_buf, - (uint32_t)message->recv_buf, message->length); - - spi_dma_transfer_prepare(device->bus, message); - /* start once data exchange in DMA mode */ - state = HAL_SPI_TransmitReceive_DMA(spi_handle, - (uint8_t*)message->send_buf, - (uint8_t*)message->recv_buf, - message->length); - if (state != HAL_OK) + if (spi_drv->spi_dma_flag & SPI_USING_TX_DMA_FLAG) { - LOG_D("spi flash configuration error : %d", state); - message->length = 0; - //while(1); + state = HAL_SPI_Transmit_DMA(spi_handle, (uint8_t *)message->send_buf, message->length); } else { - LOG_D("%s dma transfer done", spi_drv->config->bus_name); + state = HAL_SPI_Transmit(spi_handle, (uint8_t *)message->send_buf, message->length, 1000); } - - /* For simplicity reasons, this example is just waiting till the end of the - transfer, but application may perform other tasks while transfer operation - is ongoing. */ - while (HAL_SPI_GetState(spi_handle) != HAL_SPI_STATE_READY); - LOG_D("%s get state done", spi_drv->config->bus_name); } else { - // TODO - } - } else -#endif - { - if (data_width == 8) - { - const rt_uint8_t * send_ptr = message->send_buf; - rt_uint8_t * recv_ptr = message->recv_buf; - - while (length--) + if (spi_drv->spi_dma_flag & SPI_USING_RX_DMA_FLAG) { - rt_uint8_t data = ~0; - - if(send_ptr != RT_NULL) - { - data = *send_ptr++; - } - - /* send data once */ - while (__HAL_SPI_GET_FLAG(spi_handle, SPI_FLAG_TXE) == RESET); - *(volatile rt_uint8_t *)(&spi_handle->Instance->DR) = data; - - /* receive data once */ -#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32F7) - SET_BIT(spi_handle->Instance->CR2, SPI_RXFIFO_THRESHOLD_HF); -#endif - while (__HAL_SPI_GET_FLAG(spi_handle, SPI_FLAG_RXNE) == RESET); - data = *(volatile rt_uint8_t *)(&spi_handle->Instance->DR); - - if(recv_ptr != RT_NULL) - { - *recv_ptr++ = data; - } + state = HAL_SPI_Receive_DMA(spi_handle, (uint8_t *)message->recv_buf, message->length); } - - } else - { - const rt_uint16_t * send_ptr = message->send_buf; - rt_uint16_t * recv_ptr = message->recv_buf; - - while (length--) + else { - rt_uint16_t data = ~0; - - if(send_ptr != RT_NULL) - { - data = *send_ptr++; - } - - /* send data once */ - while (__HAL_SPI_GET_FLAG(spi_handle, SPI_FLAG_TXE) == RESET); - *(volatile rt_uint16_t *)(&spi_handle->Instance->DR) = data; - - /* receive data once */ -#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32F7) - SET_BIT(spi_handle->Instance->CR2, SPI_RXFIFO_THRESHOLD_HF); -#endif - while (__HAL_SPI_GET_FLAG(spi_handle, SPI_FLAG_RXNE) == RESET); - data = *(volatile rt_uint16_t *)(&spi_handle->Instance->DR); - - if(recv_ptr != RT_NULL) - { - *recv_ptr++ = data; - } + state = HAL_SPI_Receive(spi_handle, (uint8_t *)message->recv_buf, message->length, 1000); } } - } - - /* Wait until Busy flag is reset before disabling SPI */ - while (__HAL_SPI_GET_FLAG(spi_handle, SPI_FLAG_BSY) == SET); + + if (state != HAL_OK) + { + LOG_I("spi transfer error : %d", state); + message->length = 0; + spi_handle->State = HAL_SPI_STATE_READY; + } + else + { + LOG_D("%s transfer done", spi_drv->config->bus_name); + } + /* For simplicity reasons, this example is just waiting till the end of the + transfer, but application may perform other tasks while transfer operation + is ongoing. */ + while (HAL_SPI_GetState(spi_handle) != HAL_SPI_STATE_READY); + } + if (message->cs_release) { HAL_GPIO_WritePin(cs->GPIOx, cs->GPIO_Pin, GPIO_PIN_SET); @@ -443,61 +356,81 @@ static int rt_hw_spi_bus_init(void) spi_bus_obj[i].spi_bus.parent.user_data = &spi_config[i]; spi_bus_obj[i].handle.Instance = spi_config[i].Instance; -#ifdef BSP_SPI_USING_DMA - /* Configure the DMA handler for Transmission process */ - spi_bus_obj[i].dma.handle_tx.Instance = spi_config[i].dma_tx.Instance; + if (spi_bus_obj[i].spi_dma_flag & SPI_USING_RX_DMA_FLAG) + { + /* Configure the DMA handler for Transmission process */ + spi_bus_obj[i].dma.handle_rx.Instance = spi_config[i].dma_rx->Instance; #if defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) - spi_bus_obj[i].dma.handle_tx.Init.Channel = spi_config[i].dma_tx.channel; + spi_bus_obj[i].dma.handle_rx.Init.Channel = spi_config[i].dma_rx->channel; #elif defined(SOC_SERIES_STM32L4) - spi_bus_obj[i].dma.handle_tx.Init.Request = spi_config[i].dma_tx.request; -#endif - spi_bus_obj[i].dma.handle_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; - spi_bus_obj[i].dma.handle_tx.Init.PeriphInc = DMA_PINC_DISABLE; - spi_bus_obj[i].dma.handle_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; - spi_bus_obj[i].dma.handle_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; - spi_bus_obj[i].dma.handle_tx.Init.Mode = DMA_NORMAL; - spi_bus_obj[i].dma.handle_tx.Init.Priority = DMA_PRIORITY_LOW; + spi_bus_obj[i].dma.handle_rx.Init.Request = spi_config[i].dma_rx->request; +#endif + spi_bus_obj[i].dma.handle_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; + spi_bus_obj[i].dma.handle_rx.Init.PeriphInc = DMA_PINC_DISABLE; + spi_bus_obj[i].dma.handle_rx.Init.MemInc = DMA_MINC_ENABLE; + spi_bus_obj[i].dma.handle_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; + spi_bus_obj[i].dma.handle_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; + spi_bus_obj[i].dma.handle_rx.Init.Mode = DMA_NORMAL; + spi_bus_obj[i].dma.handle_rx.Init.Priority = DMA_PRIORITY_HIGH; #if defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) - spi_bus_obj[i].dma.handle_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; - spi_bus_obj[i].dma.handle_tx.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL; - spi_bus_obj[i].dma.handle_tx.Init.MemBurst = DMA_MBURST_INC4; - spi_bus_obj[i].dma.handle_tx.Init.PeriphBurst = DMA_PBURST_INC4; + spi_bus_obj[i].dma.handle_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; + spi_bus_obj[i].dma.handle_rx.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL; + spi_bus_obj[i].dma.handle_rx.Init.MemBurst = DMA_MBURST_INC4; + spi_bus_obj[i].dma.handle_rx.Init.PeriphBurst = DMA_PBURST_INC4; #endif - spi_bus_obj[i].dma.handle_rx.Instance = spi_config[i].dma_rx.Instance; + { + rt_uint32_t tmpreg = 0x00U; +#if defined(SOC_SERIES_STM32F1) + /* enable DMA clock && Delay after an RCC peripheral clock enabling*/ + SET_BIT(RCC->AHBENR, spi_config[i].dma_rx->dma_rcc); + tmpreg = READ_BIT(RCC->AHBENR, spi_config[i].dma_rx->dma_rcc); +#elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4) + SET_BIT(RCC->AHB1ENR, spi_config[i].dma_rx->dma_rcc); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB1ENR, spi_config[i].dma_rx->dma_rcc); +#endif + UNUSED(tmpreg); /* To avoid compiler warnings */ + } + } + + if (spi_bus_obj[i].spi_dma_flag & SPI_USING_TX_DMA_FLAG) + { + /* Configure the DMA handler for Transmission process */ + spi_bus_obj[i].dma.handle_tx.Instance = spi_config[i].dma_tx->Instance; #if defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) - spi_bus_obj[i].dma.handle_rx.Init.Channel = spi_config[i].dma_rx.channel; + spi_bus_obj[i].dma.handle_tx.Init.Channel = spi_config[i].dma_tx->channel; #elif defined(SOC_SERIES_STM32L4) - spi_bus_obj[i].dma.handle_rx.Init.Request = spi_config[i].dma_rx.request; -#endif - spi_bus_obj[i].dma.handle_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; - spi_bus_obj[i].dma.handle_rx.Init.PeriphInc = DMA_PINC_DISABLE; - spi_bus_obj[i].dma.handle_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; - spi_bus_obj[i].dma.handle_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; - spi_bus_obj[i].dma.handle_rx.Init.Mode = DMA_NORMAL; - spi_bus_obj[i].dma.handle_rx.Init.Priority = DMA_PRIORITY_HIGH; + spi_bus_obj[i].dma.handle_tx.Init.Request = spi_config[i].dma_tx->request; +#endif + spi_bus_obj[i].dma.handle_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; + spi_bus_obj[i].dma.handle_tx.Init.PeriphInc = DMA_PINC_DISABLE; + spi_bus_obj[i].dma.handle_tx.Init.MemInc = DMA_MINC_ENABLE; + spi_bus_obj[i].dma.handle_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; + spi_bus_obj[i].dma.handle_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; + spi_bus_obj[i].dma.handle_tx.Init.Mode = DMA_NORMAL; + spi_bus_obj[i].dma.handle_tx.Init.Priority = DMA_PRIORITY_LOW; #if defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) - spi_bus_obj[i].dma.handle_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; - spi_bus_obj[i].dma.handle_rx.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL; - spi_bus_obj[i].dma.handle_rx.Init.MemBurst = DMA_MBURST_INC4; - spi_bus_obj[i].dma.handle_rx.Init.PeriphBurst = DMA_PBURST_INC4; + spi_bus_obj[i].dma.handle_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; + spi_bus_obj[i].dma.handle_tx.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL; + spi_bus_obj[i].dma.handle_tx.Init.MemBurst = DMA_MBURST_INC4; + spi_bus_obj[i].dma.handle_tx.Init.PeriphBurst = DMA_PBURST_INC4; #endif + { rt_uint32_t tmpreg = 0x00U; #if defined(SOC_SERIES_STM32F1) /* enable DMA clock && Delay after an RCC peripheral clock enabling*/ - SET_BIT(RCC->AHBENR, spi_config[i].dma_rx.dma_rcc); - tmpreg = READ_BIT(RCC->AHBENR, spi_config[i].dma_rx.dma_rcc); + SET_BIT(RCC->AHBENR, spi_config[i].dma_rx->dma_rcc); + tmpreg = READ_BIT(RCC->AHBENR, spi_config[i].dma_rx->dma_rcc); #elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4) - SET_BIT(RCC->AHB1ENR, spi_config[i].dma_rx.dma_rcc); - /* Delay after an RCC peripheral clock enabling */ - tmpreg = READ_BIT(RCC->AHB1ENR, spi_config[i].dma_rx.dma_rcc); + SET_BIT(RCC->AHB1ENR, spi_config[i].dma_tx->dma_rcc); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB1ENR, spi_config[i].dma_tx->dma_rcc); #endif UNUSED(tmpreg); /* To avoid compiler warnings */ } - - LOG_D("%s DMA clock init done", spi_config[i].bus_name); -#endif /* BSP_SPI_USING_DMA */ + } result = rt_spi_bus_register(&spi_bus_obj[i].spi_bus, spi_config[i].bus_name, &stm_spi_ops); RT_ASSERT(result == RT_EOK); @@ -511,7 +444,7 @@ static int rt_hw_spi_bus_init(void) /** * Attach the spi device to SPI bus, this function must be used after initialization. */ -rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, GPIO_TypeDef* cs_gpiox, uint16_t cs_gpio_pin) +rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, GPIO_TypeDef *cs_gpiox, uint16_t cs_gpio_pin) { RT_ASSERT(bus_name != RT_NULL); RT_ASSERT(device_name != RT_NULL); @@ -550,7 +483,20 @@ rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, return result; } -#if defined(BSP_USING_SPI1) && defined(BSP_SPI_USING_DMA) +#if defined(BSP_SPI1_TX_USING_DMA) || defined(BSP_SPI1_RX_USING_DMA) +void SPI1_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + HAL_SPI_IRQHandler(&spi_bus_obj[SPI1_INDEX].handle); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +#if defined(BSP_USING_SPI1) && defined(BSP_SPI1_RX_USING_DMA) /** * @brief This function handles DMA Rx interrupt request. * @param None @@ -566,7 +512,9 @@ void SPI1_DMA_RX_IRQHandler(void) /* leave interrupt */ rt_interrupt_leave(); } +#endif +#if defined(BSP_USING_SPI1) && defined(BSP_SPI1_TX_USING_DMA) /** * @brief This function handles DMA Tx interrupt request. * @param None @@ -584,7 +532,20 @@ void SPI1_DMA_TX_IRQHandler(void) } #endif /* defined(BSP_USING_SPI1) && defined(BSP_SPI_USING_DMA) */ -#if defined(BSP_USING_SPI2) && defined(BSP_SPI_USING_DMA) +#if defined(BSP_SPI2_TX_USING_DMA) || defined(BSP_SPI2_RX_USING_DMA) +void SPI2_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + HAL_SPI_IRQHandler(&spi_bus_obj[SPI2_INDEX].handle); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +#if defined(BSP_USING_SPI2) && defined(BSP_SPI2_RX_USING_DMA) /** * @brief This function handles DMA Rx interrupt request. * @param None @@ -600,7 +561,9 @@ void SPI2_DMA_RX_IRQHandler(void) /* leave interrupt */ rt_interrupt_leave(); } +#endif +#if defined(BSP_USING_SPI2) && defined(BSP_SPI2_TX_USING_DMA) /** * @brief This function handles DMA Tx interrupt request. * @param None @@ -618,7 +581,20 @@ void SPI2_DMA_TX_IRQHandler(void) } #endif /* defined(BSP_USING_SPI2) && defined(BSP_SPI_USING_DMA) */ -#if defined(BSP_USING_SPI3) && defined(BSP_SPI_USING_DMA) +#if defined(BSP_SPI3_TX_USING_DMA) || defined(BSP_SPI3_RX_USING_DMA) +void SPI3_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + HAL_SPI_IRQHandler(&spi_bus_obj[SPI3_INDEX].handle); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +#if defined(BSP_USING_SPI3) && defined(BSP_SPI3_RX_USING_DMA) /** * @brief This function handles DMA Rx interrupt request. * @param None @@ -634,7 +610,9 @@ void SPI3_DMA_RX_IRQHandler(void) /* leave interrupt */ rt_interrupt_leave(); } +#endif +#if defined(BSP_USING_SPI3) && defined(BSP_SPI3_TX_USING_DMA) /** * @brief This function handles DMA Tx interrupt request. * @param None @@ -652,8 +630,20 @@ void SPI3_DMA_TX_IRQHandler(void) } #endif /* defined(BSP_USING_SPI3) && defined(BSP_SPI_USING_DMA) */ +#if defined(BSP_SPI4_TX_USING_DMA) || defined(BSP_SPI4_RX_USING_DMA) +void SPI4_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + HAL_SPI_IRQHandler(&spi_bus_obj[SPI4_INDEX].handle); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif -#if defined(BSP_USING_SPI4) && defined(BSP_SPI_USING_DMA) +#if defined(BSP_USING_SPI4) && defined(BSP_SPI4_RX_USING_DMA) /** * @brief This function handles DMA Rx interrupt request. * @param None @@ -669,7 +659,9 @@ void SPI4_DMA_RX_IRQHandler(void) /* leave interrupt */ rt_interrupt_leave(); } +#endif +#if defined(BSP_USING_SPI4) && defined(BSP_SPI4_TX_USING_DMA) /** * @brief This function handles DMA Tx interrupt request. * @param None @@ -687,7 +679,20 @@ void SPI4_DMA_TX_IRQHandler(void) } #endif /* defined(BSP_USING_SPI4) && defined(BSP_SPI_USING_DMA) */ -#if defined(BSP_USING_SPI5) && defined(BSP_SPI_USING_DMA) +#if defined(BSP_SPI5_TX_USING_DMA) || defined(BSP_SPI5_RX_USING_DMA) +void SPI5_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + HAL_SPI_IRQHandler(&spi_bus_obj[SPI5_INDEX].handle); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +#if defined(BSP_USING_SPI5) && defined(BSP_SPI5_RX_USING_DMA) /** * @brief This function handles DMA Rx interrupt request. * @param None @@ -703,7 +708,9 @@ void SPI5_DMA_RX_IRQHandler(void) /* leave interrupt */ rt_interrupt_leave(); } +#endif +#if defined(BSP_USING_SPI5) && defined(BSP_SPI5_TX_USING_DMA) /** * @brief This function handles DMA Tx interrupt request. * @param None @@ -721,7 +728,7 @@ void SPI5_DMA_TX_IRQHandler(void) } #endif /* defined(BSP_USING_SPI5) && defined(BSP_SPI_USING_DMA) */ -#if defined(BSP_USING_SPI6) && defined(BSP_SPI_USING_DMA) +#if defined(BSP_USING_SPI6) && defined(BSP_SPI6_RX_USING_DMA) /** * @brief This function handles DMA Rx interrupt request. * @param None @@ -737,7 +744,9 @@ void SPI6_DMA_RX_IRQHandler(void) /* leave interrupt */ rt_interrupt_leave(); } +#endif +#if defined(BSP_USING_SPI6) && defined(BSP_SPI6_TX_USING_DMA) /** * @brief This function handles DMA Tx interrupt request. * @param None @@ -755,8 +764,78 @@ void SPI6_DMA_TX_IRQHandler(void) } #endif /* defined(BSP_USING_SPI6) && defined(BSP_SPI_USING_DMA) */ +static void stm32_get_dma_info(void) +{ +#ifdef BSP_SPI1_RX_USING_DMA + spi_bus_obj[SPI1_INDEX].spi_dma_flag |= SPI_USING_RX_DMA_FLAG; + static struct dma_config spi1_dma_rx = SPI1_RX_DMA_CONFIG; + spi_config[SPI1_INDEX].dma_rx = &spi1_dma_rx; +#endif +#ifdef BSP_SPI1_TX_USING_DMA + spi_bus_obj[SPI1_INDEX].spi_dma_flag |= SPI_USING_TX_DMA_FLAG; + static struct dma_config spi1_dma_tx = SPI1_TX_DMA_CONFIG; + spi_config[SPI1_INDEX].dma_tx = &spi1_dma_tx; +#endif + +#ifdef BSP_SPI2_RX_USING_DMA + spi_bus_obj[SPI2_INDEX].spi_dma_flag |= SPI_USING_RX_DMA_FLAG; + static struct dma_config spi2_dma_rx = SPI2_RX_DMA_CONFIG; + spi_config[SPI2_INDEX].dma_rx = &spi2_dma_rx; +#endif +#ifdef BSP_SPI2_TX_USING_DMA + spi_bus_obj[SPI2_INDEX].spi_dma_flag |= SPI_USING_TX_DMA_FLAG; + static struct dma_config spi2_dma_tx = SPI2_TX_DMA_CONFIG; + spi_config[SPI2_INDEX].dma_tx = &spi2_dma_tx; +#endif + +#ifdef BSP_SPI3_RX_USING_DMA + spi_bus_obj[SPI3_INDEX].spi_dma_flag |= SPI_USING_RX_DMA_FLAG; + static struct dma_config spi3_dma_rx = SPI3_RX_DMA_CONFIG; + spi_config[SPI3_INDEX].dma_rx = &spi3_dma_rx; +#endif +#ifdef BSP_SPI3_TX_USING_DMA + spi_bus_obj[SPI3_INDEX].spi_dma_flag |= SPI_USING_TX_DMA_FLAG; + static struct dma_config spi3_dma_tx = SPI3_TX_DMA_CONFIG; + spi_config[SPI3_INDEX].dma_tx = &spi3_dma_tx; +#endif + +#ifdef BSP_SPI4_RX_USING_DMA + spi_bus_obj[SPI4_INDEX].spi_dma_flag |= SPI_USING_RX_DMA_FLAG; + static struct dma_config spi4_dma_rx = SPI4_RX_DMA_CONFIG; + spi_config[SPI4_INDEX].dma_rx = &spi4_dma_rx; +#endif +#ifdef BSP_SPI4_TX_USING_DMA + spi_bus_obj[SPI4_INDEX].spi_dma_flag |= SPI_USING_TX_DMA_FLAG; + static struct dma_config spi4_dma_tx = SPI4_TX_DMA_CONFIG; + spi_config[SPI4_INDEX].dma_tx = &spi4_dma_tx; +#endif + +#ifdef BSP_SPI5_RX_USING_DMA + spi_bus_obj[SPI5_INDEX].spi_dma_flag |= SPI_USING_RX_DMA_FLAG; + static struct dma_config spi5_dma_rx = SPI5_RX_DMA_CONFIG; + spi_config[SPI5_INDEX].dma_rx = &spi5_dma_rx; +#endif +#ifdef BSP_SPI5_TX_USING_DMA + spi_bus_obj[SPI5_INDEX].spi_dma_flag |= SPI_USING_TX_DMA_FLAG; + static struct dma_config spi5_dma_tx = SPI5_TX_DMA_CONFIG; + spi_config[SPI5_INDEX].dma_tx = &spi5_dma_tx; +#endif + +#ifdef BSP_SPI6_RX_USING_DMA + spi_bus_obj[SPI6_INDEX].spi_dma_flag |= SPI_USING_RX_DMA_FLAG; + static struct dma_config spi6_dma_rx = SPI6_RX_DMA_CONFIG; + spi_config[SPI6_INDEX].dma_rx = &spi6_dma_rx; +#endif +#ifdef BSP_SPI6_TX_USING_DMA + spi_bus_obj[SPI6_INDEX].spi_dma_flag |= SPI_USING_TX_DMA_FLAG; + static struct dma_config spi6_dma_tx = SPI6_TX_DMA_CONFIG; + spi_config[SPI6_INDEX].dma_tx = &spi6_dma_tx; +#endif +} + int rt_hw_spi_init(void) { + stm32_get_dma_info(); return rt_hw_spi_bus_init(); } INIT_BOARD_EXPORT(rt_hw_spi_init); diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_spi.h b/bsp/stm32/libraries/HAL_Drivers/drv_spi.h index 710f3fa59c5eee3c00641aef32249395d2addfb0..763a44dfdf43fa4f81143a5efd64150152640263 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_spi.h +++ b/bsp/stm32/libraries/HAL_Drivers/drv_spi.h @@ -5,7 +5,7 @@ * * Change Logs: * Date Author Notes - * 2018-11-5 SummerGift change to new framework + * 2018-11-5 SummerGift first version */ #ifndef __DRV_SPI_H_ @@ -29,7 +29,7 @@ struct stm32_spi_config { SPI_TypeDef *Instance; char *bus_name; - struct dma_config dma_rx, dma_tx; + struct dma_config *dma_rx, *dma_tx; }; struct stm32_spi_device @@ -39,21 +39,23 @@ struct stm32_spi_device char *device_name; }; +#define SPI_USING_RX_DMA_FLAG (1<<0) +#define SPI_USING_TX_DMA_FLAG (1<<1) + /* stm32 spi dirver class */ struct stm32_spi { SPI_HandleTypeDef handle; - const struct stm32_spi_config *config; + struct stm32_spi_config *config; struct rt_spi_configuration *cfg; - -#ifdef BSP_SPI_USING_DMA + struct { DMA_HandleTypeDef handle_rx; DMA_HandleTypeDef handle_tx; } dma; -#endif + rt_uint8_t spi_dma_flag; struct rt_spi_bus spi_bus; }; diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_usart.c b/bsp/stm32/libraries/HAL_Drivers/drv_usart.c index 916d0ed2d2a53b026e3faed37b170d8e192985d0..87543442b644a4e85359aa15af9d3821f907eb97 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_usart.c +++ b/bsp/stm32/libraries/HAL_Drivers/drv_usart.c @@ -46,7 +46,7 @@ enum #endif }; -static const struct stm32_uart_config uart_config[] = +static struct stm32_uart_config uart_config[] = { #ifdef BSP_USING_UART1 UART1_CONFIG, @@ -65,7 +65,7 @@ static const struct stm32_uart_config uart_config[] = #endif }; -static struct stm32_uart uart_obj[sizeof(uart_config) / sizeof(uart_config[0])]; +static struct stm32_uart uart_obj[sizeof(uart_config) / sizeof(uart_config[0])] = {0}; static rt_err_t stm32_configure(struct rt_serial_device *serial, struct serial_configure *cfg) { @@ -239,7 +239,7 @@ static void uart_isr(struct rt_serial_device *serial) UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_RXNE); } #ifdef RT_SERIAL_USING_DMA - else if ((__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_IDLE) != RESET) && + else if ((uart->uart_dma_flag) && (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_IDLE) != RESET) && (__HAL_UART_GET_IT_SOURCE(&(uart->handle), UART_IT_IDLE) != RESET)) { level = rt_hw_interrupt_disable(); @@ -309,8 +309,8 @@ void USART1_IRQHandler(void) /* leave interrupt */ rt_interrupt_leave(); } -#if defined(RT_SERIAL_USING_DMA) && defined(USART1_RX_DMA_ISR) -void USART1_RX_DMA_ISR(void) +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_RX_USING_DMA) +void USART1_DMA_RX_IRQHandler(void) { /* enter interrupt */ rt_interrupt_enter(); @@ -320,7 +320,7 @@ void USART1_RX_DMA_ISR(void) /* leave interrupt */ rt_interrupt_leave(); } -#endif /* defined(RT_SERIAL_USING_DMA) && defined(USART1_RX_DMA_ISR) */ +#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_RX_USING_DMA) */ #endif /* BSP_USING_UART1 */ #if defined(BSP_USING_UART2) @@ -334,8 +334,8 @@ void USART2_IRQHandler(void) /* leave interrupt */ rt_interrupt_leave(); } -#if defined(RT_SERIAL_USING_DMA) && defined(USART2_RX_DMA_ISR) -void USART2_RX_DMA_ISR(void) +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART2_RX_USING_DMA) +void USART2_DMA_RX_IRQHandler(void) { /* enter interrupt */ rt_interrupt_enter(); @@ -345,7 +345,7 @@ void USART2_RX_DMA_ISR(void) /* leave interrupt */ rt_interrupt_leave(); } -#endif /* defined(RT_SERIAL_USING_DMA) && defined(USART2_RX_DMA_ISR) */ +#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART2_RX_USING_DMA) */ #endif /* BSP_USING_UART2 */ #if defined(BSP_USING_UART3) @@ -359,8 +359,8 @@ void USART3_IRQHandler(void) /* leave interrupt */ rt_interrupt_leave(); } -#if defined(RT_SERIAL_USING_DMA) && defined(USART3_RX_DMA_ISR) -void USART3_RX_DMA_ISR(void) +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART3_RX_USING_DMA) +void USART3_DMA_RX_IRQHandler(void) { /* enter interrupt */ rt_interrupt_enter(); @@ -370,7 +370,7 @@ void USART3_RX_DMA_ISR(void) /* leave interrupt */ rt_interrupt_leave(); } -#endif /* defined(BSP_UART_USING_DMA_RX) && defined(USART3_RX_DMA_ISR) */ +#endif /* defined(BSP_UART_USING_DMA_RX) && defined(BSP_UART3_RX_USING_DMA) */ #endif /* BSP_USING_UART3*/ #if defined(BSP_USING_UART4) @@ -384,8 +384,8 @@ void UART4_IRQHandler(void) /* leave interrupt */ rt_interrupt_leave(); } -#if defined(RT_SERIAL_USING_DMA) && defined(USART1_RX_DMA_ISR) -void USART4_RX_DMA_ISR(void) +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART4_RX_USING_DMA) +void USART4_DMA_RX_IRQHandler(void) { /* enter interrupt */ rt_interrupt_enter(); @@ -395,7 +395,7 @@ void USART4_RX_DMA_ISR(void) /* leave interrupt */ rt_interrupt_leave(); } -#endif /* defined(BSP_UART_USING_DMA_RX) && defined(USART4_RX_DMA_ISR) */ +#endif /* defined(BSP_UART_USING_DMA_RX) && defined(BSP_UART4_RX_USING_DMA) */ #endif /* BSP_USING_UART4*/ #if defined(BSP_USING_UART5) @@ -409,8 +409,8 @@ void UART5_IRQHandler(void) /* leave interrupt */ rt_interrupt_leave(); } -#if defined(RT_SERIAL_USING_DMA) && defined(USART5_RX_DMA_ISR) -void USART5_RX_DMA_ISR(void) +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART5_RX_USING_DMA) +void USART5_DMA_RX_IRQHandler(void) { /* enter interrupt */ rt_interrupt_enter(); @@ -420,7 +420,7 @@ void USART5_RX_DMA_ISR(void) /* leave interrupt */ rt_interrupt_leave(); } -#endif /* defined(RT_SERIAL_USING_DMA) && defined(USART5_RX_DMA_ISR) */ +#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART5_RX_USING_DMA) */ #endif /* BSP_USING_UART5*/ #ifdef RT_SERIAL_USING_DMA @@ -437,12 +437,12 @@ static void stm32_dma_config(struct rt_serial_device *serial) rt_uint32_t tmpreg= 0x00U; #if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F0) /* enable DMA clock && Delay after an RCC peripheral clock enabling*/ - SET_BIT(RCC->AHBENR, uart->config->dma_rcc); - tmpreg = READ_BIT(RCC->AHBENR, uart->config->dma_rcc); + SET_BIT(RCC->AHBENR, uart->config->dma_rx->dma_rcc); + tmpreg = READ_BIT(RCC->AHBENR, uart->config->dma_rx->dma_rcc); #elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4) /* enable DMA clock && Delay after an RCC peripheral clock enabling*/ - SET_BIT(RCC->AHB1ENR, uart->config->dma_rcc); - tmpreg = READ_BIT(RCC->AHB1ENR, uart->config->dma_rcc); + SET_BIT(RCC->AHB1ENR, uart->config->dma_rx->dma_rcc); + tmpreg = READ_BIT(RCC->AHB1ENR, uart->config->dma_rx->dma_rcc); #endif UNUSED(tmpreg); /* To avoid compiler warnings */ } @@ -450,13 +450,13 @@ static void stm32_dma_config(struct rt_serial_device *serial) __HAL_LINKDMA(&(uart->handle), hdmarx, uart->dma.handle); #if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F0) - uart->dma.handle.Instance = uart->config->dma.Instance; + uart->dma.handle.Instance = uart->config->dma_rx->Instance; #elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) - uart->dma.handle.Instance = uart->config->dma.Instance; - uart->dma.handle.Init.Channel = uart->config->dma.stream_channel.channel; + uart->dma.handle.Instance = uart->config->dma_rx->Instance; + uart->dma.handle.Init.Channel = uart->config->dma_rx->channel; #elif defined(SOC_SERIES_STM32L4) - uart->dma.handle.Instance = uart->config->dma.Instance; - uart->dma.handle.Init.Request = uart->config->dma.channel_request.request; + uart->dma.handle.Instance = uart->config->dma_rx->Instance; + uart->dma.handle.Init.Request = uart->config->dma_rx->request; #endif uart->dma.handle.Init.Direction = DMA_PERIPH_TO_MEMORY; uart->dma.handle.Init.PeriphInc = DMA_PINC_DISABLE; @@ -491,8 +491,8 @@ static void stm32_dma_config(struct rt_serial_device *serial) __HAL_UART_ENABLE_IT(&(uart->handle), UART_IT_IDLE); /* enable rx irq */ - HAL_NVIC_SetPriority(uart->config->dma_irq, 0, 0); - HAL_NVIC_EnableIRQ(uart->config->dma_irq); + HAL_NVIC_SetPriority(uart->config->dma_rx->dma_irq, 0, 0); + HAL_NVIC_EnableIRQ(uart->config->dma_rx->dma_irq); HAL_NVIC_SetPriority(uart->config->irq_type, 1, 0); HAL_NVIC_EnableIRQ(uart->config->irq_type); @@ -547,31 +547,59 @@ void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) } #endif /* RT_SERIAL_USING_DMA */ +static void stm32_uart_get_dma_config(void) +{ +#ifdef BSP_UART1_RX_USING_DMA + uart_obj[UART1_INDEX].uart_dma_flag = 1; + static struct dma_config uart1_dma_rx = UART1_DMA_CONFIG; + uart_config[UART1_INDEX].dma_rx = &uart1_dma_rx; +#endif +#ifdef BSP_UART2_RX_USING_DMA + uart_obj[UART2_INDEX].uart_dma_flag = 1; + static struct dma_config uart2_dma_rx = UART2_DMA_CONFIG; + uart_config[UART2_INDEX].dma_rx = &uart2_dma_rx; +#endif +#ifdef BSP_UART3_RX_USING_DMA + uart_obj[UART3_INDEX].uart_dma_flag = 1; + static struct dma_config uart3_dma_rx = UART3_DMA_CONFIG; + uart_config[UART3_INDEX].dma_rx = &uart3_dma_rx; +#endif +#ifdef BSP_UART4_RX_USING_DMA + uart_obj[UART4_INDEX].uart_dma_flag = 1; + static struct dma_config uart4_dma_rx = UART4_DMA_CONFIG; + uart_config[UART4_INDEX].dma_rx = &uart4_dma_rx; +#endif +#ifdef BSP_UART5_RX_USING_DMA + uart_obj[UART5_INDEX].uart_dma_flag = 1; + static struct dma_config uart5_dma_rx = UART5_DMA_CONFIG; + uart_config[UART5_INDEX].dma_rx = &uart5_dma_rx; +#endif +} + int rt_hw_usart_init(void) { rt_size_t obj_num = sizeof(uart_obj) / sizeof(struct stm32_uart); struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; - rt_err_t result = 0; + stm32_uart_get_dma_config(); + for (int i = 0; i < obj_num; i++) { uart_obj[i].config = &uart_config[i]; uart_obj[i].serial.ops = &stm32_uart_ops; uart_obj[i].serial.config = config; - /* Determines whether a serial instance supports DMA */ - if(uart_obj[i].config->dma.Instance != DMA_NOT_AVAILABLE) +#if defined(RT_SERIAL_USING_DMA) + if(uart_obj[i].uart_dma_flag) { /* register UART device */ result = rt_hw_serial_register(&uart_obj[i].serial,uart_obj[i].config->name, - RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX -#if defined(RT_SERIAL_USING_DMA) - | RT_DEVICE_FLAG_DMA_RX -#endif + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX| RT_DEVICE_FLAG_DMA_RX ,&uart_obj[i]); } else +#endif { /* register UART device */ result = rt_hw_serial_register(&uart_obj[i].serial,uart_obj[i].config->name, diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_usart.h b/bsp/stm32/libraries/HAL_Drivers/drv_usart.h index 7f6a3598267f54273bce09ddf35dc6e4733af727..80716933fee7a8dcebd0db7fbc5b617350202a0c 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_usart.h +++ b/bsp/stm32/libraries/HAL_Drivers/drv_usart.h @@ -15,10 +15,10 @@ #include "rtdevice.h" #include #include +#include "drv_dma.h" int rt_hw_usart_init(void); - #if defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L4) #define DMA_INSTANCE_TYPE DMA_Channel_TypeDef #elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) @@ -37,45 +37,15 @@ struct stm32_uart_config const char *name; USART_TypeDef *Instance; IRQn_Type irq_type; - - union { - DMA_INSTANCE_TYPE *Instance; - -#if defined(SOC_SERIES_STM32F1) - /* the DMA config has channel only, such as on STM32F1xx */ - struct { - DMA_INSTANCE_TYPE *Instance; - } channel; -#endif - -#if defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) - /* the DMA config has stream and channel, such as on STM32F4xx */ - struct { - DMA_INSTANCE_TYPE *Instance; - rt_uint32_t channel; - } stream_channel; -#endif - -#if defined(SOC_SERIES_STM32L4) - /* the DMA config has channel and request, such as on STM32L4xx */ - struct { - DMA_INSTANCE_TYPE *Instance; - rt_uint32_t request; - } channel_request; -#endif - } dma; - - rt_uint32_t dma_rcc; - IRQn_Type dma_irq; + struct dma_config *dma_rx; }; /* stm32 uart dirver class */ struct stm32_uart { UART_HandleTypeDef handle; - const struct stm32_uart_config *config; + struct stm32_uart_config *config; - #ifdef RT_SERIAL_USING_DMA struct { @@ -83,7 +53,7 @@ struct stm32_uart rt_size_t last_index; } dma; #endif - + rt_uint8_t uart_dma_flag; struct rt_serial_device serial; };