diff --git a/bsp/lpc176x/CMSIS/LPC17xx.h b/bsp/lpc176x/CMSIS/LPC17xx.h
deleted file mode 100644
index 0ce43ba1a0171096f278cc483f861c28fc9992ff..0000000000000000000000000000000000000000
--- a/bsp/lpc176x/CMSIS/LPC17xx.h
+++ /dev/null
@@ -1,970 +0,0 @@
-/******************************************************************************
- * @file:    LPC17xx.h
- * @purpose: CMSIS Cortex-M3 Core Peripheral Access Layer Header File for 
- *           NXP LPC17xx Device Series 
- * @version: V1.04
- * @date:    2. July 2009
- *----------------------------------------------------------------------------
- *
- * Copyright (C) 2008 ARM Limited. All rights reserved.
- *
- * ARM Limited (ARM) is supplying this software for use with Cortex-M3 
- * processor based microcontrollers.  This file can be freely distributed 
- * within development tools that are supporting such ARM based processors. 
- *
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-
-
-#ifndef __LPC17xx_H__
-#define __LPC17xx_H__
-
-/*
- * ==========================================================================
- * ---------- Interrupt Number Definition -----------------------------------
- * ==========================================================================
- */
-
-typedef enum IRQn
-{
-/******  Cortex-M3 Processor Exceptions Numbers ***************************************************/
-  NonMaskableInt_IRQn           = -14,      /*!< 2 Non Maskable Interrupt                         */
-  MemoryManagement_IRQn         = -12,      /*!< 4 Cortex-M3 Memory Management Interrupt          */
-  BusFault_IRQn                 = -11,      /*!< 5 Cortex-M3 Bus Fault Interrupt                  */
-  UsageFault_IRQn               = -10,      /*!< 6 Cortex-M3 Usage Fault Interrupt                */
-  SVCall_IRQn                   = -5,       /*!< 11 Cortex-M3 SV Call Interrupt                   */
-  DebugMonitor_IRQn             = -4,       /*!< 12 Cortex-M3 Debug Monitor Interrupt             */
-  PendSV_IRQn                   = -2,       /*!< 14 Cortex-M3 Pend SV Interrupt                   */
-  SysTick_IRQn                  = -1,       /*!< 15 Cortex-M3 System Tick Interrupt               */
-
-/******  LPC17xx Specific Interrupt Numbers *******************************************************/
-  WDT_IRQn                      = 0,        /*!< Watchdog Timer Interrupt                         */
-  TIMER0_IRQn                   = 1,        /*!< Timer0 Interrupt                                 */
-  TIMER1_IRQn                   = 2,        /*!< Timer1 Interrupt                                 */
-  TIMER2_IRQn                   = 3,        /*!< Timer2 Interrupt                                 */
-  TIMER3_IRQn                   = 4,        /*!< Timer3 Interrupt                                 */
-  UART0_IRQn                    = 5,        /*!< UART0 Interrupt                                  */
-  UART1_IRQn                    = 6,        /*!< UART1 Interrupt                                  */
-  UART2_IRQn                    = 7,        /*!< UART2 Interrupt                                  */
-  UART3_IRQn                    = 8,        /*!< UART3 Interrupt                                  */
-  PWM1_IRQn                     = 9,        /*!< PWM1 Interrupt                                   */
-  I2C0_IRQn                     = 10,       /*!< I2C0 Interrupt                                   */
-  I2C1_IRQn                     = 11,       /*!< I2C1 Interrupt                                   */
-  I2C2_IRQn                     = 12,       /*!< I2C2 Interrupt                                   */
-  SPI_IRQn                      = 13,       /*!< SPI Interrupt                                    */
-  SSP0_IRQn                     = 14,       /*!< SSP0 Interrupt                                   */
-  SSP1_IRQn                     = 15,       /*!< SSP1 Interrupt                                   */
-  PLL0_IRQn                     = 16,       /*!< PLL0 Lock (Main PLL) Interrupt                   */
-  RTC_IRQn                      = 17,       /*!< Real Time Clock Interrupt                        */
-  EINT0_IRQn                    = 18,       /*!< External Interrupt 0 Interrupt                   */
-  EINT1_IRQn                    = 19,       /*!< External Interrupt 1 Interrupt                   */
-  EINT2_IRQn                    = 20,       /*!< External Interrupt 2 Interrupt                   */
-  EINT3_IRQn                    = 21,       /*!< External Interrupt 3 Interrupt                   */
-  ADC_IRQn                      = 22,       /*!< A/D Converter Interrupt                          */
-  BOD_IRQn                      = 23,       /*!< Brown-Out Detect Interrupt                       */
-  USB_IRQn                      = 24,       /*!< USB Interrupt                                    */
-  CAN_IRQn                      = 25,       /*!< CAN Interrupt                                    */
-  DMA_IRQn                      = 26,       /*!< General Purpose DMA Interrupt                    */
-  I2S_IRQn                      = 27,       /*!< I2S Interrupt                                    */
-  ENET_IRQn                     = 28,       /*!< Ethernet Interrupt                               */
-  RIT_IRQn                      = 29,       /*!< Repetitive Interrupt Timer Interrupt             */
-  MCPWM_IRQn                    = 30,       /*!< Motor Control PWM Interrupt                      */
-  QEI_IRQn                      = 31,       /*!< Quadrature Encoder Interface Interrupt           */
-  PLL1_IRQn                     = 32,       /*!< PLL1 Lock (USB PLL) Interrupt                    */
-  USBActivity_IRQn              = 33,       /* USB Activity interrupt                             */
-  CANActivity_IRQn              = 34,       /* CAN Activity interrupt                             */
-} IRQn_Type;
-
-
-/*
- * ==========================================================================
- * ----------- Processor and Core Peripheral Section ------------------------
- * ==========================================================================
- */
-
-/* Configuration of the Cortex-M3 Processor and Core Peripherals */
-#define __MPU_PRESENT             1         /*!< MPU present or not                               */
-#define __NVIC_PRIO_BITS          5         /*!< Number of Bits used for Priority Levels          */
-#define __Vendor_SysTickConfig    0         /*!< Set to 1 if different SysTick Config is used     */
-
-
-#include <core_cm3.h>                       /* Cortex-M3 processor and core peripherals           */
-#include "system_LPC17xx.h"                 /* System Header                                      */
-
-
-/******************************************************************************/
-/*                Device Specific Peripheral registers structures             */
-/******************************************************************************/
-
-#pragma anon_unions
-
-/*------------- System Control (SC) ------------------------------------------*/
-typedef struct
-{
-  __IO uint32_t FLASHCFG;               /* Flash Accelerator Module           */
-       uint32_t RESERVED0[31];
-  __IO uint32_t PLL0CON;                /* Clocking and Power Control         */
-  __IO uint32_t PLL0CFG;
-  __I  uint32_t PLL0STAT;
-  __O  uint32_t PLL0FEED;
-       uint32_t RESERVED1[4];
-  __IO uint32_t PLL1CON;
-  __IO uint32_t PLL1CFG;
-  __I  uint32_t PLL1STAT;
-  __O  uint32_t PLL1FEED;
-       uint32_t RESERVED2[4];
-  __IO uint32_t PCON;
-  __IO uint32_t PCONP;
-       uint32_t RESERVED3[15];
-  __IO uint32_t CCLKCFG;
-  __IO uint32_t USBCLKCFG;
-  __IO uint32_t CLKSRCSEL;
-  __IO uint32_t	CANSLEEPCLR;
-  __IO uint32_t	CANWAKEFLAGS;
-       uint32_t RESERVED4[10];
-  __IO uint32_t EXTINT;                 /* External Interrupts                */
-       uint32_t RESERVED5;
-  __IO uint32_t EXTMODE;
-  __IO uint32_t EXTPOLAR;
-       uint32_t RESERVED6[12];
-  __IO uint32_t RSID;                   /* Reset                              */
-       uint32_t RESERVED7[7];
-  __IO uint32_t SCS;                    /* Syscon Miscellaneous Registers     */
-  __IO uint32_t IRCTRIM;                /* Clock Dividers                     */
-  __IO uint32_t PCLKSEL0;
-  __IO uint32_t PCLKSEL1;
-       uint32_t RESERVED8[4];
-  __IO uint32_t USBIntSt;               /* USB Device/OTG Interrupt Register  */
-       uint32_t RESERVED9;
-  __IO uint32_t CLKOUTCFG;              /* Clock Output Configuration         */
- } LPC_SC_TypeDef;
-
-/*------------- Pin Connect Block (PINCON) -----------------------------------*/
-typedef struct
-{
-  __IO uint32_t PINSEL0;
-  __IO uint32_t PINSEL1;
-  __IO uint32_t PINSEL2;
-  __IO uint32_t PINSEL3;
-  __IO uint32_t PINSEL4;
-  __IO uint32_t PINSEL5;
-  __IO uint32_t PINSEL6;
-  __IO uint32_t PINSEL7;
-  __IO uint32_t PINSEL8;
-  __IO uint32_t PINSEL9;
-  __IO uint32_t PINSEL10;
-       uint32_t RESERVED0[5];
-  __IO uint32_t PINMODE0;
-  __IO uint32_t PINMODE1;
-  __IO uint32_t PINMODE2;
-  __IO uint32_t PINMODE3;
-  __IO uint32_t PINMODE4;
-  __IO uint32_t PINMODE5;
-  __IO uint32_t PINMODE6;
-  __IO uint32_t PINMODE7;
-  __IO uint32_t PINMODE8;
-  __IO uint32_t PINMODE9;
-  __IO uint32_t PINMODE_OD0;
-  __IO uint32_t PINMODE_OD1;
-  __IO uint32_t PINMODE_OD2;
-  __IO uint32_t PINMODE_OD3;
-  __IO uint32_t PINMODE_OD4;
-  __IO uint32_t I2CPADCFG;
-} LPC_PINCON_TypeDef;
-
-/*------------- General Purpose Input/Output (GPIO) --------------------------*/
-typedef struct
-{
-  __IO uint32_t FIODIR;
-       uint32_t RESERVED0[3];
-  __IO uint32_t FIOMASK;
-  __IO uint32_t FIOPIN;
-  __IO uint32_t FIOSET;
-  __O  uint32_t FIOCLR;
-} LPC_GPIO_TypeDef;
-
-typedef struct
-{
-  __I  uint32_t IntStatus;
-  __I  uint32_t IO0IntStatR;
-  __I  uint32_t IO0IntStatF;
-  __O  uint32_t IO0IntClr;
-  __IO uint32_t IO0IntEnR;
-  __IO uint32_t IO0IntEnF;
-       uint32_t RESERVED0[3];
-  __I  uint32_t IO2IntStatR;
-  __I  uint32_t IO2IntStatF;
-  __O  uint32_t IO2IntClr;
-  __IO uint32_t IO2IntEnR;
-  __IO uint32_t IO2IntEnF;
-} LPC_GPIOINT_TypeDef;
-
-/*------------- Timer (TIM) --------------------------------------------------*/
-typedef struct
-{
-  __IO uint32_t IR;
-  __IO uint32_t TCR;
-  __IO uint32_t TC;
-  __IO uint32_t PR;
-  __IO uint32_t PC;
-  __IO uint32_t MCR;
-  __IO uint32_t MR0;
-  __IO uint32_t MR1;
-  __IO uint32_t MR2;
-  __IO uint32_t MR3;
-  __IO uint32_t CCR;
-  __I  uint32_t CR0;
-  __I  uint32_t CR1;
-       uint32_t RESERVED0[2];
-  __IO uint32_t EMR;
-       uint32_t RESERVED1[12];
-  __IO uint32_t CTCR;
-} LPC_TIM_TypeDef;
-
-/*------------- Pulse-Width Modulation (PWM) ---------------------------------*/
-typedef struct
-{
-  __IO uint32_t IR;
-  __IO uint32_t TCR;
-  __IO uint32_t TC;
-  __IO uint32_t PR;
-  __IO uint32_t PC;
-  __IO uint32_t MCR;
-  __IO uint32_t MR0;
-  __IO uint32_t MR1;
-  __IO uint32_t MR2;
-  __IO uint32_t MR3;
-  __IO uint32_t CCR;
-  __I  uint32_t CR0;
-  __I  uint32_t CR1;
-  __I  uint32_t CR2;
-  __I  uint32_t CR3;
-       uint32_t RESERVED0;
-  __IO uint32_t MR4;
-  __IO uint32_t MR5;
-  __IO uint32_t MR6;
-  __IO uint32_t PCR;
-  __IO uint32_t LER;
-       uint32_t RESERVED1[7];
-  __IO uint32_t CTCR;
-} LPC_PWM_TypeDef;
-
-/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
-typedef struct
-{
-  union {
-  __I  uint8_t  RBR;
-  __O  uint8_t  THR;
-  __IO uint8_t  DLL;
-       uint32_t RESERVED0;
-  };
-  union {
-  __IO uint8_t  DLM;
-  __IO uint32_t IER;
-  };
-  union {
-  __I  uint32_t IIR;
-  __O  uint8_t  FCR;
-  };
-  __IO uint8_t  LCR;
-       uint8_t  RESERVED1[7];
-  __I  uint8_t  LSR;
-       uint8_t  RESERVED2[7];
-  __IO uint8_t  SCR;
-       uint8_t  RESERVED3[3];
-  __IO uint32_t ACR;
-  __IO uint8_t  ICR;
-       uint8_t  RESERVED4[3];
-  __IO uint8_t  FDR;
-       uint8_t  RESERVED5[7];
-  __IO uint8_t  TER;
-       uint8_t  RESERVED6[39];
-  __I  uint8_t  FIFOLVL;
-} LPC_UART_TypeDef;
-
-typedef struct
-{
-  union {
-  __I  uint8_t  RBR;
-  __O  uint8_t  THR;
-  __IO uint8_t  DLL;
-       uint32_t RESERVED0;
-  };
-  union {
-  __IO uint8_t  DLM;
-  __IO uint32_t IER;
-  };
-  union {
-  __I  uint32_t IIR;
-  __O  uint8_t  FCR;
-  };
-  __IO uint8_t  LCR;
-       uint8_t  RESERVED1[7];
-  __I  uint8_t  LSR;
-       uint8_t  RESERVED2[7];
-  __IO uint8_t  SCR;
-       uint8_t  RESERVED3[3];
-  __IO uint32_t ACR;
-  __IO uint8_t  ICR;
-       uint8_t  RESERVED4[3];
-  __IO uint8_t  FDR;
-       uint8_t  RESERVED5[7];
-  __IO uint8_t  TER;
-       uint8_t  RESERVED6[39];
-  __I  uint8_t  FIFOLVL;
-       uint8_t  RESERVED7[363];
-  __IO uint32_t DMAREQSEL;
-} LPC_UART0_TypeDef;
-
-typedef struct
-{
-  union {
-  __I  uint8_t  RBR;
-  __O  uint8_t  THR;
-  __IO uint8_t  DLL;
-       uint32_t RESERVED0;
-  };
-  union {
-  __IO uint8_t  DLM;
-  __IO uint32_t IER;
-  };
-  union {
-  __I  uint32_t IIR;
-  __O  uint8_t  FCR;
-  };
-  __IO uint8_t  LCR;
-       uint8_t  RESERVED1[3];
-  __IO uint8_t  MCR;
-       uint8_t  RESERVED2[3];
-  __I  uint8_t  LSR;
-       uint8_t  RESERVED3[3];
-  __I  uint8_t  MSR;
-       uint8_t  RESERVED4[3];
-  __IO uint8_t  SCR;
-       uint8_t  RESERVED5[3];
-  __IO uint32_t ACR;
-       uint32_t RESERVED6;
-  __IO uint32_t FDR;
-       uint32_t RESERVED7;
-  __IO uint8_t  TER;
-       uint8_t  RESERVED8[27];
-  __IO uint8_t  RS485CTRL;
-       uint8_t  RESERVED9[3];
-  __IO uint8_t  ADRMATCH;
-       uint8_t  RESERVED10[3];
-  __IO uint8_t  RS485DLY;
-       uint8_t  RESERVED11[3];
-  __I  uint8_t  FIFOLVL;
-} LPC_UART1_TypeDef;
-
-/*------------- Serial Peripheral Interface (SPI) ----------------------------*/
-typedef struct
-{
-  __IO uint32_t SPCR;
-  __I  uint32_t SPSR;
-  __IO uint32_t SPDR;
-  __IO uint32_t SPCCR;
-       uint32_t RESERVED0[3];
-  __IO uint32_t SPINT;
-} LPC_SPI_TypeDef;
-
-/*------------- Synchronous Serial Communication (SSP) -----------------------*/
-typedef struct
-{
-  __IO uint32_t CR0;
-  __IO uint32_t CR1;
-  __IO uint32_t DR;
-  __I  uint32_t SR;
-  __IO uint32_t CPSR;
-  __IO uint32_t IMSC;
-  __IO uint32_t RIS;
-  __IO uint32_t MIS;
-  __IO uint32_t ICR;
-  __IO uint32_t DMACR;
-} LPC_SSP_TypeDef;
-
-/*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
-typedef struct
-{
-  __IO uint32_t I2CONSET;
-  __I  uint32_t I2STAT;
-  __IO uint32_t I2DAT;
-  __IO uint32_t I2ADR0;
-  __IO uint32_t I2SCLH;
-  __IO uint32_t I2SCLL;
-  __O  uint32_t I2CONCLR;
-  __IO uint32_t MMCTRL;
-  __IO uint32_t I2ADR1;
-  __IO uint32_t I2ADR2;
-  __IO uint32_t I2ADR3;
-  __I  uint32_t I2DATA_BUFFER;
-  __IO uint32_t I2MASK0;
-  __IO uint32_t I2MASK1;
-  __IO uint32_t I2MASK2;
-  __IO uint32_t I2MASK3;
-} LPC_I2C_TypeDef;
-
-/*------------- Inter IC Sound (I2S) -----------------------------------------*/
-typedef struct
-{
-  __IO uint32_t I2SDAO;
-  __IO uint32_t I2SDAI;
-  __O  uint32_t I2STXFIFO;
-  __I  uint32_t I2SRXFIFO;
-  __I  uint32_t I2SSTATE;
-  __IO uint32_t I2SDMA1;
-  __IO uint32_t I2SDMA2;
-  __IO uint32_t I2SIRQ;
-  __IO uint32_t I2STXRATE;
-  __IO uint32_t I2SRXRATE;
-  __IO uint32_t I2STXBITRATE;
-  __IO uint32_t I2SRXBITRATE;
-  __IO uint32_t I2STXMODE;
-  __IO uint32_t I2SRXMODE;
-} LPC_I2S_TypeDef;
-
-/*------------- Repetitive Interrupt Timer (RIT) -----------------------------*/
-typedef struct
-{
-  __IO uint32_t RICOMPVAL;
-  __IO uint32_t RIMASK;
-  __IO uint8_t  RICTRL;
-       uint8_t  RESERVED0[3];
-  __IO uint32_t RICOUNTER;
-} LPC_RIT_TypeDef;
-
-/*------------- Real-Time Clock (RTC) ----------------------------------------*/
-typedef struct
-{
-  __IO uint8_t  ILR;
-       uint8_t  RESERVED0[7];
-  __IO uint8_t  CCR;
-       uint8_t  RESERVED1[3];
-  __IO uint8_t  CIIR;
-       uint8_t  RESERVED2[3];
-  __IO uint8_t  AMR;
-       uint8_t  RESERVED3[3];
-  __I  uint32_t CTIME0;
-  __I  uint32_t CTIME1;
-  __I  uint32_t CTIME2;
-  __IO uint8_t  SEC;
-       uint8_t  RESERVED4[3];
-  __IO uint8_t  MIN;
-       uint8_t  RESERVED5[3];
-  __IO uint8_t  HOUR;
-       uint8_t  RESERVED6[3];
-  __IO uint8_t  DOM;
-       uint8_t  RESERVED7[3];
-  __IO uint8_t  DOW;
-       uint8_t  RESERVED8[3];
-  __IO uint16_t DOY;
-       uint16_t RESERVED9;
-  __IO uint8_t  MONTH;
-       uint8_t  RESERVED10[3];
-  __IO uint16_t YEAR;
-       uint16_t RESERVED11;
-  __IO uint32_t CALIBRATION;
-  __IO uint32_t GPREG0;
-  __IO uint32_t GPREG1;
-  __IO uint32_t GPREG2;
-  __IO uint32_t GPREG3;
-  __IO uint32_t GPREG4;
-  __IO uint8_t  RTC_AUXEN;
-       uint8_t  RESERVED12[3];
-  __IO uint8_t  RTC_AUX;
-       uint8_t  RESERVED13[3];
-  __IO uint8_t  ALSEC;
-       uint8_t  RESERVED14[3];
-  __IO uint8_t  ALMIN;
-       uint8_t  RESERVED15[3];
-  __IO uint8_t  ALHOUR;
-       uint8_t  RESERVED16[3];
-  __IO uint8_t  ALDOM;
-       uint8_t  RESERVED17[3];
-  __IO uint8_t  ALDOW;
-       uint8_t  RESERVED18[3];
-  __IO uint16_t ALDOY;
-       uint16_t RESERVED19;
-  __IO uint8_t  ALMON;
-       uint8_t  RESERVED20[3];
-  __IO uint16_t ALYEAR;
-       uint16_t RESERVED21;
-} LPC_RTC_TypeDef;
-
-/*------------- Watchdog Timer (WDT) -----------------------------------------*/
-typedef struct
-{
-  __IO uint8_t  WDMOD;
-       uint8_t  RESERVED0[3];
-  __IO uint32_t WDTC;
-  __O  uint8_t  WDFEED;
-       uint8_t  RESERVED1[3];
-  __I  uint32_t WDTV;
-  __IO uint32_t WDCLKSEL;
-} LPC_WDT_TypeDef;
-
-/*------------- Analog-to-Digital Converter (ADC) ----------------------------*/
-typedef struct
-{
-  __IO uint32_t ADCR;
-  __IO uint32_t ADGDR;
-       uint32_t RESERVED0;
-  __IO uint32_t ADINTEN;
-  __I  uint32_t ADDR0;
-  __I  uint32_t ADDR1;
-  __I  uint32_t ADDR2;
-  __I  uint32_t ADDR3;
-  __I  uint32_t ADDR4;
-  __I  uint32_t ADDR5;
-  __I  uint32_t ADDR6;
-  __I  uint32_t ADDR7;
-  __I  uint32_t ADSTAT;
-  __IO uint32_t ADTRM;
-} LPC_ADC_TypeDef;
-
-/*------------- Digital-to-Analog Converter (DAC) ----------------------------*/
-typedef struct
-{
-  __IO uint32_t DACR;
-  __IO uint32_t DACCTRL;
-  __IO uint16_t DACCNTVAL;
-} LPC_DAC_TypeDef;
-
-/*------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------*/
-typedef struct
-{
-  __I  uint32_t MCCON;
-  __O  uint32_t MCCON_SET;
-  __O  uint32_t MCCON_CLR;
-  __I  uint32_t MCCAPCON;
-  __O  uint32_t MCCAPCON_SET;
-  __O  uint32_t MCCAPCON_CLR;
-  __IO uint32_t MCTIM0;
-  __IO uint32_t MCTIM1;
-  __IO uint32_t MCTIM2;
-  __IO uint32_t MCPER0;
-  __IO uint32_t MCPER1;
-  __IO uint32_t MCPER2;
-  __IO uint32_t MCPW0;
-  __IO uint32_t MCPW1;
-  __IO uint32_t MCPW2;
-  __IO uint32_t MCDEADTIME;
-  __IO uint32_t MCCCP;
-  __IO uint32_t MCCR0;
-  __IO uint32_t MCCR1;
-  __IO uint32_t MCCR2;
-  __I  uint32_t MCINTEN;
-  __O  uint32_t MCINTEN_SET;
-  __O  uint32_t MCINTEN_CLR;
-  __I  uint32_t MCCNTCON;
-  __O  uint32_t MCCNTCON_SET;
-  __O  uint32_t MCCNTCON_CLR;
-  __I  uint32_t MCINTFLAG;
-  __O  uint32_t MCINTFLAG_SET;
-  __O  uint32_t MCINTFLAG_CLR;
-  __O  uint32_t MCCAP_CLR;
-} LPC_MCPWM_TypeDef;
-
-/*------------- Quadrature Encoder Interface (QEI) ---------------------------*/
-typedef struct
-{
-  __O  uint32_t QEICON;
-  __I  uint32_t QEISTAT;
-  __IO uint32_t QEICONF;
-  __I  uint32_t QEIPOS;
-  __IO uint32_t QEIMAXPOS;
-  __IO uint32_t CMPOS0;
-  __IO uint32_t CMPOS1;
-  __IO uint32_t CMPOS2;
-  __I  uint32_t INXCNT;
-  __IO uint32_t INXCMP;
-  __IO uint32_t QEILOAD;
-  __I  uint32_t QEITIME;
-  __I  uint32_t QEIVEL;
-  __I  uint32_t QEICAP;
-  __IO uint32_t VELCOMP;
-  __IO uint32_t FILTER;
-       uint32_t RESERVED0[998];
-  __O  uint32_t QEIIEC;
-  __O  uint32_t QEIIES;
-  __I  uint32_t QEIINTSTAT;
-  __I  uint32_t QEIIE;
-  __O  uint32_t QEICLR;
-  __O  uint32_t QEISET;
-} LPC_QEI_TypeDef;
-
-/*------------- Controller Area Network (CAN) --------------------------------*/
-typedef struct
-{
-  __IO uint32_t mask[512];              /* ID Masks                           */
-} LPC_CANAF_RAM_TypeDef;
-
-typedef struct                          /* Acceptance Filter Registers        */
-{
-  __IO uint32_t AFMR;
-  __IO uint32_t SFF_sa;
-  __IO uint32_t SFF_GRP_sa;
-  __IO uint32_t EFF_sa;
-  __IO uint32_t EFF_GRP_sa;
-  __IO uint32_t ENDofTable;
-  __I  uint32_t LUTerrAd;
-  __I  uint32_t LUTerr;
-  __IO uint32_t FCANIE;
-  __IO uint32_t FCANIC0;
-  __IO uint32_t FCANIC1;
-} LPC_CANAF_TypeDef;
-
-typedef struct                          /* Central Registers                  */
-{
-  __I  uint32_t CANTxSR;
-  __I  uint32_t CANRxSR;
-  __I  uint32_t CANMSR;
-} LPC_CANCR_TypeDef;
-
-typedef struct                          /* Controller Registers               */
-{
-  __IO uint32_t MOD;
-  __O  uint32_t CMR;
-  __IO uint32_t GSR;
-  __I  uint32_t ICR;
-  __IO uint32_t IER;
-  __IO uint32_t BTR;
-  __IO uint32_t EWL;
-  __I  uint32_t SR;
-  __IO uint32_t RFS;
-  __IO uint32_t RID;
-  __IO uint32_t RDA;
-  __IO uint32_t RDB;
-  __IO uint32_t TFI1;
-  __IO uint32_t TID1;
-  __IO uint32_t TDA1;
-  __IO uint32_t TDB1;
-  __IO uint32_t TFI2;
-  __IO uint32_t TID2;
-  __IO uint32_t TDA2;
-  __IO uint32_t TDB2;
-  __IO uint32_t TFI3;
-  __IO uint32_t TID3;
-  __IO uint32_t TDA3;
-  __IO uint32_t TDB3;
-} LPC_CAN_TypeDef;
-
-/*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/
-typedef struct                          /* Common Registers                   */
-{
-  __I  uint32_t DMACIntStat;
-  __I  uint32_t DMACIntTCStat;
-  __O  uint32_t DMACIntTCClear;
-  __I  uint32_t DMACIntErrStat;
-  __O  uint32_t DMACIntErrClr;
-  __I  uint32_t DMACRawIntTCStat;
-  __I  uint32_t DMACRawIntErrStat;
-  __I  uint32_t DMACEnbldChns;
-  __IO uint32_t DMACSoftBReq;
-  __IO uint32_t DMACSoftSReq;
-  __IO uint32_t DMACSoftLBReq;
-  __IO uint32_t DMACSoftLSReq;
-  __IO uint32_t DMACConfig;
-  __IO uint32_t DMACSync;
-} LPC_GPDMA_TypeDef;
-
-typedef struct                          /* Channel Registers                  */
-{
-  __IO uint32_t DMACCSrcAddr;
-  __IO uint32_t DMACCDestAddr;
-  __IO uint32_t DMACCLLI;
-  __IO uint32_t DMACCControl;
-  __IO uint32_t DMACCConfig;
-} LPC_GPDMACH_TypeDef;
-
-/*------------- Universal Serial Bus (USB) -----------------------------------*/
-typedef struct
-{
-  __I  uint32_t HcRevision;             /* USB Host Registers                 */
-  __IO uint32_t HcControl;
-  __IO uint32_t HcCommandStatus;
-  __IO uint32_t HcInterruptStatus;
-  __IO uint32_t HcInterruptEnable;
-  __IO uint32_t HcInterruptDisable;
-  __IO uint32_t HcHCCA;
-  __I  uint32_t HcPeriodCurrentED;
-  __IO uint32_t HcControlHeadED;
-  __IO uint32_t HcControlCurrentED;
-  __IO uint32_t HcBulkHeadED;
-  __IO uint32_t HcBulkCurrentED;
-  __I  uint32_t HcDoneHead;
-  __IO uint32_t HcFmInterval;
-  __I  uint32_t HcFmRemaining;
-  __I  uint32_t HcFmNumber;
-  __IO uint32_t HcPeriodicStart;
-  __IO uint32_t HcLSTreshold;
-  __IO uint32_t HcRhDescriptorA;
-  __IO uint32_t HcRhDescriptorB;
-  __IO uint32_t HcRhStatus;
-  __IO uint32_t HcRhPortStatus1;
-  __IO uint32_t HcRhPortStatus2;
-       uint32_t RESERVED0[40];
-  __I  uint32_t Module_ID;
-
-  __I  uint32_t OTGIntSt;               /* USB On-The-Go Registers            */
-  __IO uint32_t OTGIntEn;
-  __O  uint32_t OTGIntSet;
-  __O  uint32_t OTGIntClr;
-  __IO uint32_t OTGStCtrl;
-  __IO uint32_t OTGTmr;
-       uint32_t RESERVED1[58];
-
-  __I  uint32_t USBDevIntSt;            /* USB Device Interrupt Registers     */
-  __IO uint32_t USBDevIntEn;
-  __O  uint32_t USBDevIntClr;
-  __O  uint32_t USBDevIntSet;
-
-  __O  uint32_t USBCmdCode;             /* USB Device SIE Command Registers   */
-  __I  uint32_t USBCmdData;
-
-  __I  uint32_t USBRxData;              /* USB Device Transfer Registers      */
-  __O  uint32_t USBTxData;
-  __I  uint32_t USBRxPLen;
-  __O  uint32_t USBTxPLen;
-  __IO uint32_t USBCtrl;
-  __O  uint32_t USBDevIntPri;
-
-  __I  uint32_t USBEpIntSt;             /* USB Device Endpoint Interrupt Regs */
-  __IO uint32_t USBEpIntEn;
-  __O  uint32_t USBEpIntClr;
-  __O  uint32_t USBEpIntSet;
-  __O  uint32_t USBEpIntPri;
-
-  __IO uint32_t USBReEp;                /* USB Device Endpoint Realization Reg*/
-  __O  uint32_t USBEpInd;
-  __IO uint32_t USBMaxPSize;
-
-  __I  uint32_t USBDMARSt;              /* USB Device DMA Registers           */
-  __O  uint32_t USBDMARClr;
-  __O  uint32_t USBDMARSet;
-       uint32_t RESERVED2[9];
-  __IO uint32_t USBUDCAH;
-  __I  uint32_t USBEpDMASt;
-  __O  uint32_t USBEpDMAEn;
-  __O  uint32_t USBEpDMADis;
-  __I  uint32_t USBDMAIntSt;
-  __IO uint32_t USBDMAIntEn;
-       uint32_t RESERVED3[2];
-  __I  uint32_t USBEoTIntSt;
-  __O  uint32_t USBEoTIntClr;
-  __O  uint32_t USBEoTIntSet;
-  __I  uint32_t USBNDDRIntSt;
-  __O  uint32_t USBNDDRIntClr;
-  __O  uint32_t USBNDDRIntSet;
-  __I  uint32_t USBSysErrIntSt;
-  __O  uint32_t USBSysErrIntClr;
-  __O  uint32_t USBSysErrIntSet;
-       uint32_t RESERVED4[15];
-
-  union {
-  __I  uint32_t I2C_RX;                 /* USB OTG I2C Registers              */
-  __O  uint32_t I2C_WO;
-  };
-  __I  uint32_t I2C_STS;
-  __IO uint32_t I2C_CTL;
-  __IO uint32_t I2C_CLKHI;
-  __O  uint32_t I2C_CLKLO;
-       uint32_t RESERVED5[824];
-
-  union {
-  __IO uint32_t USBClkCtrl;             /* USB Clock Control Registers        */
-  __IO uint32_t OTGClkCtrl;
-  };
-  union {
-  __I  uint32_t USBClkSt;
-  __I  uint32_t OTGClkSt;
-  };
-} LPC_USB_TypeDef;
-
-/*------------- Ethernet Media Access Controller (EMAC) ----------------------*/
-typedef struct
-{
-  __IO uint32_t MAC1;                   /* MAC Registers                      */
-  __IO uint32_t MAC2;
-  __IO uint32_t IPGT;
-  __IO uint32_t IPGR;
-  __IO uint32_t CLRT;
-  __IO uint32_t MAXF;
-  __IO uint32_t SUPP;
-  __IO uint32_t TEST;
-  __IO uint32_t MCFG;
-  __IO uint32_t MCMD;
-  __IO uint32_t MADR;
-  __O  uint32_t MWTD;
-  __I  uint32_t MRDD;
-  __I  uint32_t MIND;
-       uint32_t RESERVED0[2];
-  __IO uint32_t SA0;
-  __IO uint32_t SA1;
-  __IO uint32_t SA2;
-       uint32_t RESERVED1[45];
-  __IO uint32_t Command;                /* Control Registers                  */
-  __I  uint32_t Status;
-  __IO uint32_t RxDescriptor;
-  __IO uint32_t RxStatus;
-  __IO uint32_t RxDescriptorNumber;
-  __I  uint32_t RxProduceIndex;
-  __IO uint32_t RxConsumeIndex;
-  __IO uint32_t TxDescriptor;
-  __IO uint32_t TxStatus;
-  __IO uint32_t TxDescriptorNumber;
-  __IO uint32_t TxProduceIndex;
-  __I  uint32_t TxConsumeIndex;
-       uint32_t RESERVED2[10];
-  __I  uint32_t TSV0;
-  __I  uint32_t TSV1;
-  __I  uint32_t RSV;
-       uint32_t RESERVED3[3];
-  __IO uint32_t FlowControlCounter;
-  __I  uint32_t FlowControlStatus;
-       uint32_t RESERVED4[34];
-  __IO uint32_t RxFilterCtrl;           /* Rx Filter Registers                */
-  __IO uint32_t RxFilterWoLStatus;
-  __IO uint32_t RxFilterWoLClear;
-       uint32_t RESERVED5;
-  __IO uint32_t HashFilterL;
-  __IO uint32_t HashFilterH;
-       uint32_t RESERVED6[882];
-  __I  uint32_t IntStatus;              /* Module Control Registers           */
-  __IO uint32_t IntEnable;
-  __O  uint32_t IntClear;
-  __O  uint32_t IntSet;
-       uint32_t RESERVED7;
-  __IO uint32_t PowerDown;
-       uint32_t RESERVED8;
-  __IO uint32_t Module_ID;
-} LPC_EMAC_TypeDef;
-
-#pragma no_anon_unions
-
-
-/******************************************************************************/
-/*                         Peripheral memory map                              */
-/******************************************************************************/
-/* Base addresses                                                             */
-#define LPC_FLASH_BASE        (0x00000000UL)
-#define LPC_RAM_BASE          (0x10000000UL)
-#define LPC_GPIO_BASE         (0x2009C000UL)
-#define LPC_APB0_BASE         (0x40000000UL)
-#define LPC_APB1_BASE         (0x40080000UL)
-#define LPC_AHB_BASE          (0x50000000UL)
-#define LPC_CM3_BASE          (0xE0000000UL)
-
-/* APB0 peripherals                                                           */
-#define LPC_WDT_BASE          (LPC_APB0_BASE + 0x00000)
-#define LPC_TIM0_BASE         (LPC_APB0_BASE + 0x04000)
-#define LPC_TIM1_BASE         (LPC_APB0_BASE + 0x08000)
-#define LPC_UART0_BASE        (LPC_APB0_BASE + 0x0C000)
-#define LPC_UART1_BASE        (LPC_APB0_BASE + 0x10000)
-#define LPC_PWM1_BASE         (LPC_APB0_BASE + 0x18000)
-#define LPC_I2C0_BASE         (LPC_APB0_BASE + 0x1C000)
-#define LPC_SPI_BASE          (LPC_APB0_BASE + 0x20000)
-#define LPC_RTC_BASE          (LPC_APB0_BASE + 0x24000)
-#define LPC_GPIOINT_BASE      (LPC_APB0_BASE + 0x28080)
-#define LPC_PINCON_BASE       (LPC_APB0_BASE + 0x2C000)
-#define LPC_SSP1_BASE         (LPC_APB0_BASE + 0x30000)
-#define LPC_ADC_BASE          (LPC_APB0_BASE + 0x34000)
-#define LPC_CANAF_RAM_BASE    (LPC_APB0_BASE + 0x38000)
-#define LPC_CANAF_BASE        (LPC_APB0_BASE + 0x3C000)
-#define LPC_CANCR_BASE        (LPC_APB0_BASE + 0x40000)
-#define LPC_CAN1_BASE         (LPC_APB0_BASE + 0x44000)
-#define LPC_CAN2_BASE         (LPC_APB0_BASE + 0x48000)
-#define LPC_I2C1_BASE         (LPC_APB0_BASE + 0x5C000)
-
-/* APB1 peripherals                                                           */
-#define LPC_SSP0_BASE         (LPC_APB1_BASE + 0x08000)
-#define LPC_DAC_BASE          (LPC_APB1_BASE + 0x0C000)
-#define LPC_TIM2_BASE         (LPC_APB1_BASE + 0x10000)
-#define LPC_TIM3_BASE         (LPC_APB1_BASE + 0x14000)
-#define LPC_UART2_BASE        (LPC_APB1_BASE + 0x18000)
-#define LPC_UART3_BASE        (LPC_APB1_BASE + 0x1C000)
-#define LPC_I2C2_BASE         (LPC_APB1_BASE + 0x20000)
-#define LPC_I2S_BASE          (LPC_APB1_BASE + 0x28000)
-#define LPC_RIT_BASE          (LPC_APB1_BASE + 0x30000)
-#define LPC_MCPWM_BASE        (LPC_APB1_BASE + 0x38000)
-#define LPC_QEI_BASE          (LPC_APB1_BASE + 0x3C000)
-#define LPC_SC_BASE           (LPC_APB1_BASE + 0x7C000)
-
-/* AHB peripherals                                                            */
-#define LPC_EMAC_BASE         (LPC_AHB_BASE  + 0x00000)
-#define LPC_GPDMA_BASE        (LPC_AHB_BASE  + 0x04000)
-#define LPC_GPDMACH0_BASE     (LPC_AHB_BASE  + 0x04100)
-#define LPC_GPDMACH1_BASE     (LPC_AHB_BASE  + 0x04120)
-#define LPC_GPDMACH2_BASE     (LPC_AHB_BASE  + 0x04140)
-#define LPC_GPDMACH3_BASE     (LPC_AHB_BASE  + 0x04160)
-#define LPC_GPDMACH4_BASE     (LPC_AHB_BASE  + 0x04180)
-#define LPC_GPDMACH5_BASE     (LPC_AHB_BASE  + 0x041A0)
-#define LPC_GPDMACH6_BASE     (LPC_AHB_BASE  + 0x041C0)
-#define LPC_GPDMACH7_BASE     (LPC_AHB_BASE  + 0x041E0)
-#define LPC_USB_BASE          (LPC_AHB_BASE  + 0x0C000)
-
-/* GPIOs                                                                      */
-#define LPC_GPIO0_BASE        (LPC_GPIO_BASE + 0x00000)
-#define LPC_GPIO1_BASE        (LPC_GPIO_BASE + 0x00020)
-#define LPC_GPIO2_BASE        (LPC_GPIO_BASE + 0x00040)
-#define LPC_GPIO3_BASE        (LPC_GPIO_BASE + 0x00060)
-#define LPC_GPIO4_BASE        (LPC_GPIO_BASE + 0x00080)
-
-
-/******************************************************************************/
-/*                         Peripheral declaration                             */
-/******************************************************************************/
-#define LPC_SC                ((LPC_SC_TypeDef        *) LPC_SC_BASE       )
-#define LPC_GPIO0             ((LPC_GPIO_TypeDef      *) LPC_GPIO0_BASE    )
-#define LPC_GPIO1             ((LPC_GPIO_TypeDef      *) LPC_GPIO1_BASE    )
-#define LPC_GPIO2             ((LPC_GPIO_TypeDef      *) LPC_GPIO2_BASE    )
-#define LPC_GPIO3             ((LPC_GPIO_TypeDef      *) LPC_GPIO3_BASE    )
-#define LPC_GPIO4             ((LPC_GPIO_TypeDef      *) LPC_GPIO4_BASE    )
-#define LPC_WDT               ((LPC_WDT_TypeDef       *) LPC_WDT_BASE      )
-#define LPC_TIM0              ((LPC_TIM_TypeDef       *) LPC_TIM0_BASE     )
-#define LPC_TIM1              ((LPC_TIM_TypeDef       *) LPC_TIM1_BASE     )
-#define LPC_TIM2              ((LPC_TIM_TypeDef       *) LPC_TIM2_BASE     )
-#define LPC_TIM3              ((LPC_TIM_TypeDef       *) LPC_TIM3_BASE     )
-#define LPC_RIT               ((LPC_RIT_TypeDef       *) LPC_RIT_BASE      )
-#define LPC_UART0             ((LPC_UART0_TypeDef     *) LPC_UART0_BASE    )
-#define LPC_UART1             ((LPC_UART1_TypeDef     *) LPC_UART1_BASE    )
-#define LPC_UART2             ((LPC_UART_TypeDef      *) LPC_UART2_BASE    )
-#define LPC_UART3             ((LPC_UART_TypeDef      *) LPC_UART3_BASE    )
-#define LPC_PWM1              ((LPC_PWM_TypeDef       *) LPC_PWM1_BASE     )
-#define LPC_I2C0              ((LPC_I2C_TypeDef       *) LPC_I2C0_BASE     )
-#define LPC_I2C1              ((LPC_I2C_TypeDef       *) LPC_I2C1_BASE     )
-#define LPC_I2C2              ((LPC_I2C_TypeDef       *) LPC_I2C2_BASE     )
-#define LPC_I2S               ((LPC_I2S_TypeDef       *) LPC_I2S_BASE      )
-#define LPC_SPI               ((LPC_SPI_TypeDef       *) LPC_SPI_BASE      )
-#define LPC_RTC               ((LPC_RTC_TypeDef       *) LPC_RTC_BASE      )
-#define LPC_GPIOINT           ((LPC_GPIOINT_TypeDef   *) LPC_GPIOINT_BASE  )
-#define LPC_PINCON            ((LPC_PINCON_TypeDef    *) LPC_PINCON_BASE   )
-#define LPC_SSP0              ((LPC_SSP_TypeDef       *) LPC_SSP0_BASE     )
-#define LPC_SSP1              ((LPC_SSP_TypeDef       *) LPC_SSP1_BASE     )
-#define LPC_ADC               ((LPC_ADC_TypeDef       *) LPC_ADC_BASE      )
-#define LPC_DAC               ((LPC_DAC_TypeDef       *) LPC_DAC_BASE      )
-#define LPC_CANAF_RAM         ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE)
-#define LPC_CANAF             ((LPC_CANAF_TypeDef     *) LPC_CANAF_BASE    )
-#define LPC_CANCR             ((LPC_CANCR_TypeDef     *) LPC_CANCR_BASE    )
-#define LPC_CAN1              ((LPC_CAN_TypeDef       *) LPC_CAN1_BASE     )
-#define LPC_CAN2              ((LPC_CAN_TypeDef       *) LPC_CAN2_BASE     )
-#define LPC_MCPWM             ((LPC_MCPWM_TypeDef     *) LPC_MCPWM_BASE    )
-#define LPC_QEI               ((LPC_QEI_TypeDef       *) LPC_QEI_BASE      )
-#define LPC_EMAC              ((LPC_EMAC_TypeDef      *) LPC_EMAC_BASE     )
-#define LPC_GPDMA             ((LPC_GPDMA_TypeDef     *) LPC_GPDMA_BASE    )
-#define LPC_GPDMACH0          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH0_BASE )
-#define LPC_GPDMACH1          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH1_BASE )
-#define LPC_GPDMACH2          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH2_BASE )
-#define LPC_GPDMACH3          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH3_BASE )
-#define LPC_GPDMACH4          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH4_BASE )
-#define LPC_GPDMACH5          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH5_BASE )
-#define LPC_GPDMACH6          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH6_BASE )
-#define LPC_GPDMACH7          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH7_BASE )
-#define LPC_USB               ((LPC_USB_TypeDef       *) LPC_USB_BASE      )
-
-#endif  // __LPC17xx_H__
diff --git a/bsp/lpc176x/CMSIS/core_cm3.c b/bsp/lpc176x/CMSIS/core_cm3.c
deleted file mode 100644
index ea8cb1ac079be1d54b816e8b729986bfac94b99c..0000000000000000000000000000000000000000
--- a/bsp/lpc176x/CMSIS/core_cm3.c
+++ /dev/null
@@ -1,829 +0,0 @@
-/******************************************************************************
- * @file:    core_cm3.c
- * @purpose: CMSIS Cortex-M3 Core Peripheral Access Layer Source File
- * @version: V1.20
- * @date:    22. May 2009
- *----------------------------------------------------------------------------
- *
- * Copyright (C) 2009 ARM Limited. All rights reserved.
- *
- * ARM Limited (ARM) is supplying this software for use with Cortex-Mx 
- * processor based microcontrollers.  This file can be freely distributed 
- * within development tools that are supporting such ARM based processors. 
- *
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-
-
-
-#include <stdint.h>
-
-
-/* define compiler specific symbols */
-#if defined   ( __CC_ARM   )
-  #define __ASM            __asm           /*!< asm keyword for armcc           */
-  #define __INLINE         __inline        /*!< inline keyword for armcc        */
-
-#elif defined ( __ICCARM__ )
-  #define __ASM           __asm            /*!< asm keyword for iarcc           */
-  #define __INLINE        inline           /*!< inline keyword for iarcc. Only avaiable in High optimization mode! */
-
-#elif defined (  __GNUC__  )
-  #define __ASM             __asm          /*!< asm keyword for gcc            */
-  #define __INLINE          inline         /*!< inline keyword for gcc         */
-
-#elif defined   (  __TASKING__  )
-  #define __ASM            __asm           /*!< asm keyword for TASKING Compiler          */
-  #define __INLINE         inline          /*!< inline keyword for TASKING Compiler       */
-
-#endif
-
-
-
-#if defined ( __CC_ARM   ) /*------------------RealView Compiler -----------------*/
-
-/**
- * @brief  Return the Process Stack Pointer
- *
- * @param  none
- * @return uint32_t ProcessStackPointer
- *
- * Return the actual process stack pointer
- */
-__ASM uint32_t __get_PSP(void)
-{
-  mrs r0, psp
-  bx lr
-}
-
-/**
- * @brief  Set the Process Stack Pointer
- *
- * @param  uint32_t Process Stack Pointer
- * @return none
- *
- * Assign the value ProcessStackPointer to the MSP 
- * (process stack pointer) Cortex processor register
- */
-__ASM void __set_PSP(uint32_t topOfProcStack)
-{
-  msr psp, r0
-  bx lr
-}
-
-/**
- * @brief  Return the Main Stack Pointer
- *
- * @param  none
- * @return uint32_t Main Stack Pointer
- *
- * Return the current value of the MSP (main stack pointer)
- * Cortex processor register
- */
-__ASM uint32_t __get_MSP(void)
-{
-  mrs r0, msp
-  bx lr
-}
-
-/**
- * @brief  Set the Main Stack Pointer
- *
- * @param  uint32_t Main Stack Pointer
- * @return none
- *
- * Assign the value mainStackPointer to the MSP 
- * (main stack pointer) Cortex processor register
- */
-__ASM void __set_MSP(uint32_t mainStackPointer)
-{
-  msr msp, r0
-  bx lr
-}
-
-/**
- * @brief  Reverse byte order in unsigned short value
- *
- * @param  uint16_t value to reverse
- * @return uint32_t reversed value
- *
- * Reverse byte order in unsigned short value
- */
-__ASM uint32_t __REV16(uint16_t value)
-{
-  rev16 r0, r0
-  bx lr
-}
-
-/**
- * @brief  Reverse byte order in signed short value with sign extension to integer
- *
- * @param  int16_t value to reverse
- * @return int32_t reversed value
- *
- * Reverse byte order in signed short value with sign extension to integer
- */
-__ASM int32_t __REVSH(int16_t value)
-{
-  revsh r0, r0
-  bx lr
-}
-
-
-#if (__ARMCC_VERSION < 400000)
-
-/**
- * @brief  Remove the exclusive lock created by ldrex
- *
- * @param  none
- * @return none
- *
- * Removes the exclusive lock which is created by ldrex.
- */
-__ASM void __CLREX(void)
-{
-  clrex
-}
-
-/**
- * @brief  Return the Base Priority value
- *
- * @param  none
- * @return uint32_t BasePriority
- *
- * Return the content of the base priority register
- */
-__ASM uint32_t  __get_BASEPRI(void)
-{
-  mrs r0, basepri
-  bx lr
-}
-
-/**
- * @brief  Set the Base Priority value
- *
- * @param  uint32_t BasePriority
- * @return none
- *
- * Set the base priority register
- */
-__ASM void __set_BASEPRI(uint32_t basePri)
-{
-  msr basepri, r0
-  bx lr
-}
-
-/**
- * @brief  Return the Priority Mask value
- *
- * @param  none
- * @return uint32_t PriMask
- *
- * Return the state of the priority mask bit from the priority mask
- * register
- */
-__ASM uint32_t __get_PRIMASK(void)
-{
-  mrs r0, primask
-  bx lr
-}
-
-/**
- * @brief  Set the Priority Mask value
- *
- * @param  uint32_t PriMask
- * @return none
- *
- * Set the priority mask bit in the priority mask register
- */
-__ASM void __set_PRIMASK(uint32_t priMask)
-{
-  msr primask, r0
-  bx lr
-}
-
-/**
- * @brief  Return the Fault Mask value
- *
- * @param  none
- * @return uint32_t FaultMask
- *
- * Return the content of the fault mask register
- */
-__ASM uint32_t  __get_FAULTMASK(void)
-{
-  mrs r0, faultmask
-  bx lr
-}
-
-/**
- * @brief  Set the Fault Mask value
- *
- * @param  uint32_t faultMask value
- * @return none
- *
- * Set the fault mask register
- */
-__ASM void __set_FAULTMASK(uint32_t faultMask)
-{
-  msr faultmask, r0
-  bx lr
-}
-
-/**
- * @brief  Return the Control Register value
- * 
- * @param  none
- * @return uint32_t Control value
- *
- * Return the content of the control register
- */
-__ASM uint32_t  __get_CONTROL(void)
-{
-  mrs r0, control
-  bx lr
-}
-
-/**
- * @brief  Set the Control Register value
- *
- * @param  uint32_t Control value
- * @return none
- *
- * Set the control register
- */
-__ASM void __set_CONTROL(uint32_t control)
-{
-  msr control, r0
-  bx lr
-}
-
-#endif /* __ARMCC_VERSION  */ 
-
-
-#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
-#pragma diag_suppress=Pe940
-
-/**
- * @brief  Return the Process Stack Pointer
- *
- * @param  none
- * @return uint32_t ProcessStackPointer
- *
- * Return the actual process stack pointer
- */
-uint32_t __get_PSP(void)
-{
-  __ASM("mrs r0, psp");
-  __ASM("bx lr");
-}
-
-/**
- * @brief  Set the Process Stack Pointer
- *
- * @param  uint32_t Process Stack Pointer
- * @return none
- *
- * Assign the value ProcessStackPointer to the MSP 
- * (process stack pointer) Cortex processor register
- */
-void __set_PSP(uint32_t topOfProcStack)
-{
-  __ASM("msr psp, r0");
-  __ASM("bx lr");
-}
-
-/**
- * @brief  Return the Main Stack Pointer
- *
- * @param  none
- * @return uint32_t Main Stack Pointer
- *
- * Return the current value of the MSP (main stack pointer)
- * Cortex processor register
- */
-uint32_t __get_MSP(void)
-{
-  __ASM("mrs r0, msp");
-  __ASM("bx lr");
-}
-
-/**
- * @brief  Set the Main Stack Pointer
- *
- * @param  uint32_t Main Stack Pointer
- * @return none
- *
- * Assign the value mainStackPointer to the MSP 
- * (main stack pointer) Cortex processor register
- */
-void __set_MSP(uint32_t topOfMainStack)
-{
-  __ASM("msr msp, r0");
-  __ASM("bx lr");
-}
-
-/**
- * @brief  Reverse byte order in unsigned short value
- *
- * @param  uint16_t value to reverse
- * @return uint32_t reversed value
- *
- * Reverse byte order in unsigned short value
- */
-uint32_t __REV16(uint16_t value)
-{
-  __ASM("rev16 r0, r0");
-  __ASM("bx lr");
-}
-
-/**
- * @brief  Reverse bit order of value
- *
- * @param  uint32_t value to reverse
- * @return uint32_t reversed value
- *
- * Reverse bit order of value
- */
-uint32_t __RBIT(uint32_t value)
-{
-  __ASM("rbit r0, r0");
-  __ASM("bx lr");
-}
-
-/**
- * @brief  LDR Exclusive
- *
- * @param  uint8_t* address
- * @return uint8_t value of (*address)
- *
- * Exclusive LDR command
- */
-uint8_t __LDREXB(uint8_t *addr)
-{
-  __ASM("ldrexb r0, [r0]");
-  __ASM("bx lr"); 
-}
-
-/**
- * @brief  LDR Exclusive
- *
- * @param  uint16_t* address
- * @return uint16_t value of (*address)
- *
- * Exclusive LDR command
- */
-uint16_t __LDREXH(uint16_t *addr)
-{
-  __ASM("ldrexh r0, [r0]");
-  __ASM("bx lr");
-}
-
-/**
- * @brief  LDR Exclusive
- *
- * @param  uint32_t* address
- * @return uint32_t value of (*address)
- *
- * Exclusive LDR command
- */
-uint32_t __LDREXW(uint32_t *addr)
-{
-  __ASM("ldrex r0, [r0]");
-  __ASM("bx lr");
-}
-
-/**
- * @brief  STR Exclusive
- *
- * @param  uint8_t *address
- * @param  uint8_t value to store
- * @return uint32_t successful / failed
- *
- * Exclusive STR command
- */
-uint32_t __STREXB(uint8_t value, uint8_t *addr)
-{
-  __ASM("strexb r0, r0, [r1]");
-  __ASM("bx lr");
-}
-
-/**
- * @brief  STR Exclusive
- *
- * @param  uint16_t *address
- * @param  uint16_t value to store
- * @return uint32_t successful / failed
- *
- * Exclusive STR command
- */
-uint32_t __STREXH(uint16_t value, uint16_t *addr)
-{
-  __ASM("strexh r0, r0, [r1]");
-  __ASM("bx lr");
-}
-
-/**
- * @brief  STR Exclusive
- *
- * @param  uint32_t *address
- * @param  uint32_t value to store
- * @return uint32_t successful / failed
- *
- * Exclusive STR command
- */
-uint32_t __STREXW(uint32_t value, uint32_t *addr)
-{
-  __ASM("strex r0, r0, [r1]");
-  __ASM("bx lr");
-}
-
-#pragma diag_default=Pe940
-
-
-#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
-
-/**
- * @brief  Return the Process Stack Pointer
- *
- * @param  none
- * @return uint32_t ProcessStackPointer
- *
- * Return the actual process stack pointer
- */
-uint32_t __get_PSP(void) __attribute__( ( naked ) );
-uint32_t __get_PSP(void)
-{
-  uint32_t result=0;
-
-  __ASM volatile ("MRS %0, psp\n\t" 
-                  "MOV r0, %0 \n\t"
-                  "BX  lr     \n\t"  : "=r" (result) );
-  return(result);
-}
-
-
-/**
- * @brief  Set the Process Stack Pointer
- *
- * @param  uint32_t Process Stack Pointer
- * @return none
- *
- * Assign the value ProcessStackPointer to the MSP 
- * (process stack pointer) Cortex processor register
- */
-void __set_PSP(uint32_t topOfProcStack) __attribute__( ( naked ) );
-void __set_PSP(uint32_t topOfProcStack)
-{
-  __ASM volatile ("MSR psp, %0\n\t"
-                  "BX  lr     \n\t" : : "r" (topOfProcStack) );
-}
-
-/**
- * @brief  Return the Main Stack Pointer
- *
- * @param  none
- * @return uint32_t Main Stack Pointer
- *
- * Return the current value of the MSP (main stack pointer)
- * Cortex processor register
- */
-uint32_t __get_MSP(void) __attribute__( ( naked ) );
-uint32_t __get_MSP(void)
-{
-  uint32_t result=0;
-
-  __ASM volatile ("MRS %0, msp\n\t" 
-                  "MOV r0, %0 \n\t"
-                  "BX  lr     \n\t"  : "=r" (result) );
-  return(result);
-}
-
-/**
- * @brief  Set the Main Stack Pointer
- *
- * @param  uint32_t Main Stack Pointer
- * @return none
- *
- * Assign the value mainStackPointer to the MSP 
- * (main stack pointer) Cortex processor register
- */
-void __set_MSP(uint32_t topOfMainStack) __attribute__( ( naked ) );
-void __set_MSP(uint32_t topOfMainStack)
-{
-  __ASM volatile ("MSR msp, %0\n\t"
-                  "BX  lr     \n\t" : : "r" (topOfMainStack) );
-}
-
-/**
- * @brief  Return the Base Priority value
- *
- * @param  none
- * @return uint32_t BasePriority
- *
- * Return the content of the base priority register
- */
-uint32_t __get_BASEPRI(void)
-{
-  uint32_t result=0;
-  
-  __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
-  return(result);
-}
-
-/**
- * @brief  Set the Base Priority value
- *
- * @param  uint32_t BasePriority
- * @return none
- *
- * Set the base priority register
- */
-void __set_BASEPRI(uint32_t value)
-{
-  __ASM volatile ("MSR basepri, %0" : : "r" (value) );
-}
-
-/**
- * @brief  Return the Priority Mask value
- *
- * @param  none
- * @return uint32_t PriMask
- *
- * Return the state of the priority mask bit from the priority mask
- * register
- */
-uint32_t __get_PRIMASK(void)
-{
-  uint32_t result=0;
-
-  __ASM volatile ("MRS %0, primask" : "=r" (result) );
-  return(result);
-}
-
-/**
- * @brief  Set the Priority Mask value
- *
- * @param  uint32_t PriMask
- * @return none
- *
- * Set the priority mask bit in the priority mask register
- */
-void __set_PRIMASK(uint32_t priMask)
-{
-  __ASM volatile ("MSR primask, %0" : : "r" (priMask) );
-}
-
-/**
- * @brief  Return the Fault Mask value
- *
- * @param  none
- * @return uint32_t FaultMask
- *
- * Return the content of the fault mask register
- */
-uint32_t __get_FAULTMASK(void)
-{
-  uint32_t result=0;
-  
-  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
-  return(result);
-}
-
-/**
- * @brief  Set the Fault Mask value
- *
- * @param  uint32_t faultMask value
- * @return none
- *
- * Set the fault mask register
- */
-void __set_FAULTMASK(uint32_t faultMask)
-{
-  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
-}
-
-/**
- * @brief  Reverse byte order in integer value
- *
- * @param  uint32_t value to reverse
- * @return uint32_t reversed value
- *
- * Reverse byte order in integer value
- */
-uint32_t __REV(uint32_t value)
-{
-  uint32_t result=0;
-  
-  __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
-  return(result);
-}
-
-/**
- * @brief  Reverse byte order in unsigned short value
- *
- * @param  uint16_t value to reverse
- * @return uint32_t reversed value
- *
- * Reverse byte order in unsigned short value
- */
-uint32_t __REV16(uint16_t value)
-{
-  uint32_t result=0;
-  
-  __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
-  return(result);
-}
-
-/**
- * @brief  Reverse byte order in signed short value with sign extension to integer
- *
- * @param  int32_t value to reverse
- * @return int32_t reversed value
- *
- * Reverse byte order in signed short value with sign extension to integer
- */
-int32_t __REVSH(int16_t value)
-{
-  uint32_t result=0;
-  
-  __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
-  return(result);
-}
-
-/**
- * @brief  Reverse bit order of value
- *
- * @param  uint32_t value to reverse
- * @return uint32_t reversed value
- *
- * Reverse bit order of value
- */
-uint32_t __RBIT(uint32_t value)
-{
-  uint32_t result=0;
-  
-   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
-   return(result);
-}
-
-/**
- * @brief  LDR Exclusive
- *
- * @param  uint8_t* address
- * @return uint8_t value of (*address)
- *
- * Exclusive LDR command
- */
-uint8_t __LDREXB(uint8_t *addr)
-{
-    uint8_t result=0;
-  
-   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
-   return(result);
-}
-
-/**
- * @brief  LDR Exclusive
- *
- * @param  uint16_t* address
- * @return uint16_t value of (*address)
- *
- * Exclusive LDR command
- */
-uint16_t __LDREXH(uint16_t *addr)
-{
-    uint16_t result=0;
-  
-   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
-   return(result);
-}
-
-/**
- * @brief  LDR Exclusive
- *
- * @param  uint32_t* address
- * @return uint32_t value of (*address)
- *
- * Exclusive LDR command
- */
-uint32_t __LDREXW(uint32_t *addr)
-{
-    uint32_t result=0;
-  
-   __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
-   return(result);
-}
-
-/**
- * @brief  STR Exclusive
- *
- * @param  uint8_t *address
- * @param  uint8_t value to store
- * @return uint32_t successful / failed
- *
- * Exclusive STR command
- */
-uint32_t __STREXB(uint8_t value, uint8_t *addr)
-{
-   uint32_t result=0;
-  
-   __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
-   return(result);
-}
-
-/**
- * @brief  STR Exclusive
- *
- * @param  uint16_t *address
- * @param  uint16_t value to store
- * @return uint32_t successful / failed
- *
- * Exclusive STR command
- */
-uint32_t __STREXH(uint16_t value, uint16_t *addr)
-{
-   uint32_t result=0;
-  
-   __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
-   return(result);
-}
-
-/**
- * @brief  STR Exclusive
- *
- * @param  uint32_t *address
- * @param  uint32_t value to store
- * @return uint32_t successful / failed
- *
- * Exclusive STR command
- */
-uint32_t __STREXW(uint32_t value, uint32_t *addr)
-{
-   uint32_t result=0;
-  
-   __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
-   return(result);
-}
-
-/**
- * @brief  Return the Control Register value
- * 
- * @param  none
- * @return uint32_t Control value
- *
- * Return the content of the control register
- */
-uint32_t __get_CONTROL(void)
-{
-  uint32_t result=0;
-
-  __ASM volatile ("MRS %0, control" : "=r" (result) );
-  return(result);
-}
-
-/**
- * @brief  Set the Control Register value
- *
- * @param  uint32_t Control value
- * @return none
- *
- * Set the control register
- */
-void __set_CONTROL(uint32_t control)
-{
-  __ASM volatile ("MSR control, %0" : : "r" (control) );
-}
-
-#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/
-/* TASKING carm specific functions */
-
-/*
- * The CMSIS functions have been implemented as intrinsics in the compiler.
- * Please use "carm -?i" to get an up to date list of all instrinsics,
- * Including the CMSIS ones.
- */
-
-#endif
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
diff --git a/bsp/lpc176x/CMSIS/core_cm3.h b/bsp/lpc176x/CMSIS/core_cm3.h
deleted file mode 100644
index b6f9696bfca99f9bbb965b9efc3c707aade55345..0000000000000000000000000000000000000000
--- a/bsp/lpc176x/CMSIS/core_cm3.h
+++ /dev/null
@@ -1,1367 +0,0 @@
-/******************************************************************************
- * @file:    core_cm3.h
- * @purpose: CMSIS Cortex-M3 Core Peripheral Access Layer Header File
- * @version: V1.20
- * @date:    22. May 2009
- *----------------------------------------------------------------------------
- *
- * Copyright (C) 2009 ARM Limited. All rights reserved.
- *
- * ARM Limited (ARM) is supplying this software for use with Cortex-Mx 
- * processor based microcontrollers.  This file can be freely distributed 
- * within development tools that are supporting such ARM based processors. 
- *
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-
-#ifndef __CM3_CORE_H__
-#define __CM3_CORE_H__
-
-#ifdef __cplusplus
- extern "C" {
-#endif 
-
-#define __CM3_CMSIS_VERSION_MAIN  (0x01)                                                       /*!< [31:16] CMSIS HAL main version */
-#define __CM3_CMSIS_VERSION_SUB   (0x20)                                                       /*!< [15:0]  CMSIS HAL sub version  */
-#define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number       */
-
-#define __CORTEX_M                (0x03)                                                       /*!< Cortex core                    */
-
-/**
- *  Lint configuration \n
- *  ----------------------- \n
- *
- *  The following Lint messages will be suppressed and not shown: \n
- *  \n
- *    --- Error 10: --- \n
- *    register uint32_t __regBasePri         __asm("basepri"); \n
- *    Error 10: Expecting ';' \n
- *     \n
- *    --- Error 530: --- \n
- *    return(__regBasePri); \n
- *    Warning 530: Symbol '__regBasePri' (line 264) not initialized \n
- *     \n
- *    --- Error 550: --- \n
- *      __regBasePri = (basePri & 0x1ff); \n
- *    } \n
- *    Warning 550: Symbol '__regBasePri' (line 271) not accessed \n
- *     \n
- *    --- Error 754: --- \n
- *    uint32_t RESERVED0[24]; \n
- *    Info 754: local structure member '<some, not used in the HAL>' (line 109, file ./cm3_core.h) not referenced \n
- *     \n
- *    --- Error 750: --- \n
- *    #define __CM3_CORE_H__ \n
- *    Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced \n
- *     \n
- *    --- Error 528: --- \n
- *    static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n
- *    Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced \n
- *     \n
- *    --- Error 751: --- \n
- *    } InterruptType_Type; \n
- *    Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced \n
- * \n
- * \n
- *    Note:  To re-enable a Message, insert a space before 'lint' * \n
- *
- */
-
-/*lint -save */
-/*lint -e10  */
-/*lint -e530 */
-/*lint -e550 */
-/*lint -e754 */
-/*lint -e750 */
-/*lint -e528 */
-/*lint -e751 */
-
-
-#include <stdint.h>                           /* Include standard types */
-
-#if defined (__ICCARM__)
-  #include <intrinsics.h>                     /* IAR Intrinsics   */
-#endif
-
-
-#ifndef __NVIC_PRIO_BITS
-  #define __NVIC_PRIO_BITS    4               /*!< standard definition for NVIC Priority Bits */
-#endif
-
-
-
-
-/**
- * IO definitions
- *
- * define access restrictions to peripheral registers
- */
-
-#ifdef __cplusplus
-#define     __I     volatile                  /*!< defines 'read only' permissions      */
-#else
-#define     __I     volatile const            /*!< defines 'read only' permissions      */
-#endif
-#define     __O     volatile                  /*!< defines 'write only' permissions     */
-#define     __IO    volatile                  /*!< defines 'read / write' permissions   */
-
-
-
-/*******************************************************************************
- *                 Register Abstraction
- ******************************************************************************/
-
-
-/* System Reset */
-#define NVIC_VECTRESET              0         /*!< Vector Reset Bit             */
-#define NVIC_SYSRESETREQ            2         /*!< System Reset Request         */
-#define NVIC_AIRCR_VECTKEY    (0x5FA << 16)   /*!< AIRCR Key for write access   */
-#define NVIC_AIRCR_ENDIANESS        15        /*!< Endianess                    */
-
-/* Core Debug */
-#define CoreDebug_DEMCR_TRCENA (1 << 24)      /*!< DEMCR TRCENA enable          */
-#define ITM_TCR_ITMENA              1         /*!< ITM enable                   */
-
-
-
-
-/* memory mapping struct for Nested Vectored Interrupt Controller (NVIC) */
-typedef struct
-{
-  __IO uint32_t ISER[8];                      /*!< Interrupt Set Enable Register            */
-       uint32_t RESERVED0[24];
-  __IO uint32_t ICER[8];                      /*!< Interrupt Clear Enable Register          */
-       uint32_t RSERVED1[24];
-  __IO uint32_t ISPR[8];                      /*!< Interrupt Set Pending Register           */
-       uint32_t RESERVED2[24];
-  __IO uint32_t ICPR[8];                      /*!< Interrupt Clear Pending Register         */
-       uint32_t RESERVED3[24];
-  __IO uint32_t IABR[8];                      /*!< Interrupt Active bit Register            */
-       uint32_t RESERVED4[56];
-  __IO uint8_t  IP[240];                      /*!< Interrupt Priority Register, 8Bit wide   */
-       uint32_t RESERVED5[644];
-  __O  uint32_t STIR;                         /*!< Software Trigger Interrupt Register      */
-}  NVIC_Type;
-
-
-/* memory mapping struct for System Control Block */
-typedef struct
-{
-  __I  uint32_t CPUID;                        /*!< CPU ID Base Register                                     */
-  __IO uint32_t ICSR;                         /*!< Interrupt Control State Register                         */
-  __IO uint32_t VTOR;                         /*!< Vector Table Offset Register                             */
-  __IO uint32_t AIRCR;                        /*!< Application Interrupt / Reset Control Register           */
-  __IO uint32_t SCR;                          /*!< System Control Register                                  */
-  __IO uint32_t CCR;                          /*!< Configuration Control Register                           */
-  __IO uint8_t  SHP[12];                      /*!< System Handlers Priority Registers (4-7, 8-11, 12-15)    */
-  __IO uint32_t SHCSR;                        /*!< System Handler Control and State Register                */
-  __IO uint32_t CFSR;                         /*!< Configurable Fault Status Register                       */
-  __IO uint32_t HFSR;                         /*!< Hard Fault Status Register                               */
-  __IO uint32_t DFSR;                         /*!< Debug Fault Status Register                              */
-  __IO uint32_t MMFAR;                        /*!< Mem Manage Address Register                              */
-  __IO uint32_t BFAR;                         /*!< Bus Fault Address Register                               */
-  __IO uint32_t AFSR;                         /*!< Auxiliary Fault Status Register                          */
-  __I  uint32_t PFR[2];                       /*!< Processor Feature Register                               */
-  __I  uint32_t DFR;                          /*!< Debug Feature Register                                   */
-  __I  uint32_t ADR;                          /*!< Auxiliary Feature Register                               */
-  __I  uint32_t MMFR[4];                      /*!< Memory Model Feature Register                            */
-  __I  uint32_t ISAR[5];                      /*!< ISA Feature Register                                     */
-} SCB_Type;
-
-
-/* memory mapping struct for SysTick */
-typedef struct
-{
-  __IO uint32_t CTRL;                         /*!< SysTick Control and Status Register */
-  __IO uint32_t LOAD;                         /*!< SysTick Reload Value Register       */
-  __IO uint32_t VAL;                          /*!< SysTick Current Value Register      */
-  __I  uint32_t CALIB;                        /*!< SysTick Calibration Register        */
-} SysTick_Type;
-
-
-/* memory mapping structur for ITM */
-typedef struct
-{
-  __O  union  
-  {
-    __O  uint8_t    u8;                       /*!< ITM Stimulus Port 8-bit               */
-    __O  uint16_t   u16;                      /*!< ITM Stimulus Port 16-bit              */
-    __O  uint32_t   u32;                      /*!< ITM Stimulus Port 32-bit              */
-  }  PORT [32];                               /*!< ITM Stimulus Port Registers           */
-       uint32_t RESERVED0[864];
-  __IO uint32_t TER;                          /*!< ITM Trace Enable Register             */
-       uint32_t RESERVED1[15];
-  __IO uint32_t TPR;                          /*!< ITM Trace Privilege Register          */
-       uint32_t RESERVED2[15];
-  __IO uint32_t TCR;                          /*!< ITM Trace Control Register            */
-       uint32_t RESERVED3[29];
-  __IO uint32_t IWR;                          /*!< ITM Integration Write Register        */
-  __IO uint32_t IRR;                          /*!< ITM Integration Read Register         */
-  __IO uint32_t IMCR;                         /*!< ITM Integration Mode Control Register */
-       uint32_t RESERVED4[43];
-  __IO uint32_t LAR;                          /*!< ITM Lock Access Register              */
-  __IO uint32_t LSR;                          /*!< ITM Lock Status Register              */
-       uint32_t RESERVED5[6];
-  __I  uint32_t PID4;                         /*!< ITM Product ID Registers              */
-  __I  uint32_t PID5;
-  __I  uint32_t PID6;
-  __I  uint32_t PID7;
-  __I  uint32_t PID0;
-  __I  uint32_t PID1;
-  __I  uint32_t PID2;
-  __I  uint32_t PID3;
-  __I  uint32_t CID0;
-  __I  uint32_t CID1;
-  __I  uint32_t CID2;
-  __I  uint32_t CID3;
-} ITM_Type;
-
-
-/* memory mapped struct for Interrupt Type */
-typedef struct
-{
-       uint32_t RESERVED0;
-  __I  uint32_t ICTR;                         /*!< Interrupt Control Type Register  */
-#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
-  __IO uint32_t ACTLR;                        /*!< Auxiliary Control Register       */
-#else
-       uint32_t RESERVED1;
-#endif
-} InterruptType_Type;
-
-
-/* Memory Protection Unit */
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)
-typedef struct
-{
-  __I  uint32_t TYPE;                         /*!< MPU Type Register                               */
-  __IO uint32_t CTRL;                         /*!< MPU Control Register                            */
-  __IO uint32_t RNR;                          /*!< MPU Region RNRber Register                      */
-  __IO uint32_t RBAR;                         /*!< MPU Region Base Address Register                */
-  __IO uint32_t RASR;                         /*!< MPU Region Attribute and Size Register          */
-  __IO uint32_t RBAR_A1;                      /*!< MPU Alias 1 Region Base Address Register        */
-  __IO uint32_t RASR_A1;                      /*!< MPU Alias 1 Region Attribute and Size Register  */
-  __IO uint32_t RBAR_A2;                      /*!< MPU Alias 2 Region Base Address Register        */
-  __IO uint32_t RASR_A2;                      /*!< MPU Alias 2 Region Attribute and Size Register  */
-  __IO uint32_t RBAR_A3;                      /*!< MPU Alias 3 Region Base Address Register        */
-  __IO uint32_t RASR_A3;                      /*!< MPU Alias 3 Region Attribute and Size Register  */
-} MPU_Type;
-#endif
-
-
-/* Core Debug Register */
-typedef struct
-{
-  __IO uint32_t DHCSR;                        /*!< Debug Halting Control and Status Register       */
-  __O  uint32_t DCRSR;                        /*!< Debug Core Register Selector Register           */
-  __IO uint32_t DCRDR;                        /*!< Debug Core Register Data Register               */
-  __IO uint32_t DEMCR;                        /*!< Debug Exception and Monitor Control Register    */
-} CoreDebug_Type;
-
-
-/* Memory mapping of Cortex-M3 Hardware */
-#define SCS_BASE            (0xE000E000)                              /*!< System Control Space Base Address    */
-#define ITM_BASE            (0xE0000000)                              /*!< ITM Base Address                     */
-#define CoreDebug_BASE      (0xE000EDF0)                              /*!< Core Debug Base Address              */
-#define SysTick_BASE        (SCS_BASE +  0x0010)                      /*!< SysTick Base Address                 */
-#define NVIC_BASE           (SCS_BASE +  0x0100)                      /*!< NVIC Base Address                    */
-#define SCB_BASE            (SCS_BASE +  0x0D00)                      /*!< System Control Block Base Address    */
-
-#define InterruptType       ((InterruptType_Type *) SCS_BASE)         /*!< Interrupt Type Register              */
-#define SCB                 ((SCB_Type *)           SCB_BASE)         /*!< SCB configuration struct             */
-#define SysTick             ((SysTick_Type *)       SysTick_BASE)     /*!< SysTick configuration struct         */
-#define NVIC                ((NVIC_Type *)          NVIC_BASE)        /*!< NVIC configuration struct            */
-#define ITM                 ((ITM_Type *)           ITM_BASE)         /*!< ITM configuration struct             */
-#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct      */
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)
-  #define MPU_BASE          (SCS_BASE +  0x0D90)                      /*!< Memory Protection Unit               */
-  #define MPU               ((MPU_Type*)            MPU_BASE)         /*!< Memory Protection Unit               */
-#endif
-
-
-
-/*******************************************************************************
- *                Hardware Abstraction Layer
- ******************************************************************************/
-
-
-#if defined ( __CC_ARM   )
-  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
-  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
-
-#elif defined ( __ICCARM__ )
-  #define __ASM           __asm                                       /*!< asm keyword for IAR Compiler           */
-  #define __INLINE        inline                                      /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
-
-#elif defined   (  __GNUC__  )
-  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
-  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
-
-#elif defined   (  __TASKING__  )
-  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler          */
-  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler       */
-
-#endif
-
-
-/* ###################  Compiler specific Intrinsics  ########################### */
-
-#if defined ( __CC_ARM   ) /*------------------RealView Compiler -----------------*/
-/* ARM armcc specific functions */
-
-#define __enable_fault_irq                __enable_fiq
-#define __disable_fault_irq               __disable_fiq
-
-#define __NOP                             __nop
-#define __WFI                             __wfi
-#define __WFE                             __wfe
-#define __SEV                             __sev
-#define __ISB()                           __isb(0)
-#define __DSB()                           __dsb(0)
-#define __DMB()                           __dmb(0)
-#define __REV                             __rev
-#define __RBIT                            __rbit
-#define __LDREXB(ptr)                     ((unsigned char ) __ldrex(ptr))
-#define __LDREXH(ptr)                     ((unsigned short) __ldrex(ptr))
-#define __LDREXW(ptr)                     ((unsigned int  ) __ldrex(ptr))
-#define __STREXB(value, ptr)              __strex(value, ptr)
-#define __STREXH(value, ptr)              __strex(value, ptr)
-#define __STREXW(value, ptr)              __strex(value, ptr)
-
-
-/* intrinsic unsigned long long __ldrexd(volatile void *ptr) */
-/* intrinsic int __strexd(unsigned long long val, volatile void *ptr) */
-/* intrinsic void __enable_irq();     */
-/* intrinsic void __disable_irq();    */
-
-
-/**
- * @brief  Return the Process Stack Pointer
- *
- * @param  none
- * @return uint32_t ProcessStackPointer
- *
- * Return the actual process stack pointer
- */
-extern uint32_t __get_PSP(void);
-
-/**
- * @brief  Set the Process Stack Pointer
- *
- * @param  uint32_t Process Stack Pointer
- * @return none
- *
- * Assign the value ProcessStackPointer to the MSP 
- * (process stack pointer) Cortex processor register
- */
-extern void __set_PSP(uint32_t topOfProcStack);
-
-/**
- * @brief  Return the Main Stack Pointer
- *
- * @param  none
- * @return uint32_t Main Stack Pointer
- *
- * Return the current value of the MSP (main stack pointer)
- * Cortex processor register
- */
-extern uint32_t __get_MSP(void);
-
-/**
- * @brief  Set the Main Stack Pointer
- *
- * @param  uint32_t Main Stack Pointer
- * @return none
- *
- * Assign the value mainStackPointer to the MSP 
- * (main stack pointer) Cortex processor register
- */
-extern void __set_MSP(uint32_t topOfMainStack);
-
-/**
- * @brief  Reverse byte order in unsigned short value
- *
- * @param  uint16_t value to reverse
- * @return uint32_t reversed value
- *
- * Reverse byte order in unsigned short value
- */
-extern uint32_t __REV16(uint16_t value);
-
-/*
- * @brief  Reverse byte order in signed short value with sign extension to integer
- *
- * @param  int16_t value to reverse
- * @return int32_t reversed value
- *
- * Reverse byte order in signed short value with sign extension to integer
- */
-extern int32_t __REVSH(int16_t value);
-
-
-#if (__ARMCC_VERSION < 400000)
-
-/**
- * @brief  Remove the exclusive lock created by ldrex
- *
- * @param  none
- * @return none
- *
- * Removes the exclusive lock which is created by ldrex.
- */
-extern void __CLREX(void);
-
-/**
- * @brief  Return the Base Priority value
- *
- * @param  none
- * @return uint32_t BasePriority
- *
- * Return the content of the base priority register
- */
-extern uint32_t __get_BASEPRI(void);
-
-/**
- * @brief  Set the Base Priority value
- *
- * @param  uint32_t BasePriority
- * @return none
- *
- * Set the base priority register
- */
-extern void __set_BASEPRI(uint32_t basePri);
-
-/**
- * @brief  Return the Priority Mask value
- *
- * @param  none
- * @return uint32_t PriMask
- *
- * Return the state of the priority mask bit from the priority mask
- * register
- */
-extern uint32_t __get_PRIMASK(void);
-
-/**
- * @brief  Set the Priority Mask value
- *
- * @param  uint32_t PriMask
- * @return none
- *
- * Set the priority mask bit in the priority mask register
- */
-extern void __set_PRIMASK(uint32_t priMask);
-
-/**
- * @brief  Return the Fault Mask value
- *
- * @param  none
- * @return uint32_t FaultMask
- *
- * Return the content of the fault mask register
- */
-extern uint32_t __get_FAULTMASK(void);
-
-/**
- * @brief  Set the Fault Mask value
- *
- * @param  uint32_t faultMask value
- * @return none
- *
- * Set the fault mask register
- */
-extern void __set_FAULTMASK(uint32_t faultMask);
-
-/**
- * @brief  Return the Control Register value
- * 
- * @param  none
- * @return uint32_t Control value
- *
- * Return the content of the control register
- */
-extern uint32_t __get_CONTROL(void);
-
-/**
- * @brief  Set the Control Register value
- *
- * @param  uint32_t Control value
- * @return none
- *
- * Set the control register
- */
-extern void __set_CONTROL(uint32_t control);
-
-#else  /* (__ARMCC_VERSION >= 400000)  */
-
-
-/**
- * @brief  Remove the exclusive lock created by ldrex
- *
- * @param  none
- * @return none
- *
- * Removes the exclusive lock which is created by ldrex.
- */
-#define __CLREX                           __clrex
-
-/**
- * @brief  Return the Base Priority value
- *
- * @param  none
- * @return uint32_t BasePriority
- *
- * Return the content of the base priority register
- */
-static __INLINE uint32_t  __get_BASEPRI(void)
-{
-  register uint32_t __regBasePri         __ASM("basepri");
-  return(__regBasePri);
-}
-
-/**
- * @brief  Set the Base Priority value
- *
- * @param  uint32_t BasePriority
- * @return none
- *
- * Set the base priority register
- */
-static __INLINE void __set_BASEPRI(uint32_t basePri)
-{
-  register uint32_t __regBasePri         __ASM("basepri");
-  __regBasePri = (basePri & 0x1ff);
-}
-
-/**
- * @brief  Return the Priority Mask value
- *
- * @param  none
- * @return uint32_t PriMask
- *
- * Return the state of the priority mask bit from the priority mask
- * register
- */
-static __INLINE uint32_t __get_PRIMASK(void)
-{
-  register uint32_t __regPriMask         __ASM("primask");
-  return(__regPriMask);
-}
-
-/**
- * @brief  Set the Priority Mask value
- *
- * @param  uint32_t PriMask
- * @return none
- *
- * Set the priority mask bit in the priority mask register
- */
-static __INLINE void __set_PRIMASK(uint32_t priMask)
-{
-  register uint32_t __regPriMask         __ASM("primask");
-  __regPriMask = (priMask);
-}
-
-/**
- * @brief  Return the Fault Mask value
- *
- * @param  none
- * @return uint32_t FaultMask
- *
- * Return the content of the fault mask register
- */
-static __INLINE uint32_t __get_FAULTMASK(void)
-{
-  register uint32_t __regFaultMask       __ASM("faultmask");
-  return(__regFaultMask);
-}
-
-/**
- * @brief  Set the Fault Mask value
- *
- * @param  uint32_t faultMask value
- * @return none
- *
- * Set the fault mask register
- */
-static __INLINE void __set_FAULTMASK(uint32_t faultMask)
-{
-  register uint32_t __regFaultMask       __ASM("faultmask");
-  __regFaultMask = (faultMask & 1);
-}
-
-/**
- * @brief  Return the Control Register value
- * 
- * @param  none
- * @return uint32_t Control value
- *
- * Return the content of the control register
- */
-static __INLINE uint32_t __get_CONTROL(void)
-{
-  register uint32_t __regControl         __ASM("control");
-  return(__regControl);
-}
-
-/**
- * @brief  Set the Control Register value
- *
- * @param  uint32_t Control value
- * @return none
- *
- * Set the control register
- */
-static __INLINE void __set_CONTROL(uint32_t control)
-{
-  register uint32_t __regControl         __ASM("control");
-  __regControl = control;
-}
-
-#endif /* __ARMCC_VERSION  */ 
-
-
-
-#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
-/* IAR iccarm specific functions */
-
-#define __enable_irq                              __enable_interrupt        /*!< global Interrupt enable */
-#define __disable_irq                             __disable_interrupt       /*!< global Interrupt disable */
-
-static __INLINE void __enable_fault_irq()         { __ASM ("cpsie f"); }
-static __INLINE void __disable_fault_irq()        { __ASM ("cpsid f"); }
-
-#define __NOP                                     __no_operation()          /*!< no operation intrinsic in IAR Compiler */ 
-static __INLINE  void __WFI()                     { __ASM ("wfi"); }
-static __INLINE  void __WFE()                     { __ASM ("wfe"); }
-static __INLINE  void __SEV()                     { __ASM ("sev"); }
-static __INLINE  void __CLREX()                   { __ASM ("clrex"); }
-
-/* intrinsic void __ISB(void)                                     */
-/* intrinsic void __DSB(void)                                     */
-/* intrinsic void __DMB(void)                                     */
-/* intrinsic void __set_PRIMASK();                                */
-/* intrinsic void __get_PRIMASK();                                */
-/* intrinsic void __set_FAULTMASK();                              */
-/* intrinsic void __get_FAULTMASK();                              */
-/* intrinsic uint32_t __REV(uint32_t value);                      */
-/* intrinsic uint32_t __REVSH(uint32_t value);                    */
-/* intrinsic unsigned long __STREX(unsigned long, unsigned long); */
-/* intrinsic unsigned long __LDREX(unsigned long *);              */
-
-
-/**
- * @brief  Return the Process Stack Pointer
- *
- * @param  none
- * @return uint32_t ProcessStackPointer
- *
- * Return the actual process stack pointer
- */
-extern uint32_t __get_PSP(void);
-
-/**
- * @brief  Set the Process Stack Pointer
- *
- * @param  uint32_t Process Stack Pointer
- * @return none
- *
- * Assign the value ProcessStackPointer to the MSP 
- * (process stack pointer) Cortex processor register
- */
-extern void __set_PSP(uint32_t topOfProcStack);
-
-/**
- * @brief  Return the Main Stack Pointer
- *
- * @param  none
- * @return uint32_t Main Stack Pointer
- *
- * Return the current value of the MSP (main stack pointer)
- * Cortex processor register
- */
-extern uint32_t __get_MSP(void);
-
-/**
- * @brief  Set the Main Stack Pointer
- *
- * @param  uint32_t Main Stack Pointer
- * @return none
- *
- * Assign the value mainStackPointer to the MSP 
- * (main stack pointer) Cortex processor register
- */
-extern void __set_MSP(uint32_t topOfMainStack);
-
-/**
- * @brief  Reverse byte order in unsigned short value
- *
- * @param  uint16_t value to reverse
- * @return uint32_t reversed value
- *
- * Reverse byte order in unsigned short value
- */
-extern uint32_t __REV16(uint16_t value);
-
-/**
- * @brief  Reverse bit order of value
- *
- * @param  uint32_t value to reverse
- * @return uint32_t reversed value
- *
- * Reverse bit order of value
- */
-extern uint32_t __RBIT(uint32_t value);
-
-/**
- * @brief  LDR Exclusive
- *
- * @param  uint8_t* address
- * @return uint8_t value of (*address)
- *
- * Exclusive LDR command
- */
-extern uint8_t __LDREXB(uint8_t *addr);
-
-/**
- * @brief  LDR Exclusive
- *
- * @param  uint16_t* address
- * @return uint16_t value of (*address)
- *
- * Exclusive LDR command
- */
-extern uint16_t __LDREXH(uint16_t *addr);
-
-/**
- * @brief  LDR Exclusive
- *
- * @param  uint32_t* address
- * @return uint32_t value of (*address)
- *
- * Exclusive LDR command
- */
-extern uint32_t __LDREXW(uint32_t *addr);
-
-/**
- * @brief  STR Exclusive
- *
- * @param  uint8_t *address
- * @param  uint8_t value to store
- * @return uint32_t successful / failed
- *
- * Exclusive STR command
- */
-extern uint32_t __STREXB(uint8_t value, uint8_t *addr);
-
-/**
- * @brief  STR Exclusive
- *
- * @param  uint16_t *address
- * @param  uint16_t value to store
- * @return uint32_t successful / failed
- *
- * Exclusive STR command
- */
-extern uint32_t __STREXH(uint16_t value, uint16_t *addr);
-
-/**
- * @brief  STR Exclusive
- *
- * @param  uint32_t *address
- * @param  uint32_t value to store
- * @return uint32_t successful / failed
- *
- * Exclusive STR command
- */
-extern uint32_t __STREXW(uint32_t value, uint32_t *addr);
-
-
-
-#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
-/* GNU gcc specific functions */
-
-static __INLINE void __enable_irq()               { __ASM volatile ("cpsie i"); }
-static __INLINE void __disable_irq()              { __ASM volatile ("cpsid i"); }
-
-static __INLINE void __enable_fault_irq()         { __ASM volatile ("cpsie f"); }
-static __INLINE void __disable_fault_irq()        { __ASM volatile ("cpsid f"); }
-
-static __INLINE void __NOP()                      { __ASM volatile ("nop"); }
-static __INLINE void __WFI()                      { __ASM volatile ("wfi"); }
-static __INLINE void __WFE()                      { __ASM volatile ("wfe"); }
-static __INLINE void __SEV()                      { __ASM volatile ("sev"); }
-static __INLINE void __ISB()                      { __ASM volatile ("isb"); }
-static __INLINE void __DSB()                      { __ASM volatile ("dsb"); }
-static __INLINE void __DMB()                      { __ASM volatile ("dmb"); }
-static __INLINE void __CLREX()                    { __ASM volatile ("clrex"); }
-
-
-/**
- * @brief  Return the Process Stack Pointer
- *
- * @param  none
- * @return uint32_t ProcessStackPointer
- *
- * Return the actual process stack pointer
- */
-extern uint32_t __get_PSP(void);
-
-/**
- * @brief  Set the Process Stack Pointer
- *
- * @param  uint32_t Process Stack Pointer
- * @return none
- *
- * Assign the value ProcessStackPointer to the MSP 
- * (process stack pointer) Cortex processor register
- */
-extern void __set_PSP(uint32_t topOfProcStack);
-
-/**
- * @brief  Return the Main Stack Pointer
- *
- * @param  none
- * @return uint32_t Main Stack Pointer
- *
- * Return the current value of the MSP (main stack pointer)
- * Cortex processor register
- */
-extern uint32_t __get_MSP(void);
-
-/**
- * @brief  Set the Main Stack Pointer
- *
- * @param  uint32_t Main Stack Pointer
- * @return none
- *
- * Assign the value mainStackPointer to the MSP 
- * (main stack pointer) Cortex processor register
- */
-extern void __set_MSP(uint32_t topOfMainStack);
-
-/**
- * @brief  Return the Base Priority value
- *
- * @param  none
- * @return uint32_t BasePriority
- *
- * Return the content of the base priority register
- */
-extern uint32_t __get_BASEPRI(void);
-
-/**
- * @brief  Set the Base Priority value
- *
- * @param  uint32_t BasePriority
- * @return none
- *
- * Set the base priority register
- */
-extern void __set_BASEPRI(uint32_t basePri);
-
-/**
- * @brief  Return the Priority Mask value
- *
- * @param  none
- * @return uint32_t PriMask
- *
- * Return the state of the priority mask bit from the priority mask
- * register
- */
-extern uint32_t  __get_PRIMASK(void);
-
-/**
- * @brief  Set the Priority Mask value
- *
- * @param  uint32_t PriMask
- * @return none
- *
- * Set the priority mask bit in the priority mask register
- */
-extern void __set_PRIMASK(uint32_t priMask);
-
-/**
- * @brief  Return the Fault Mask value
- *
- * @param  none
- * @return uint32_t FaultMask
- *
- * Return the content of the fault mask register
- */
-extern uint32_t __get_FAULTMASK(void);
-
-/**
- * @brief  Set the Fault Mask value
- *
- * @param  uint32_t faultMask value
- * @return none
- *
- * Set the fault mask register
- */
-extern void __set_FAULTMASK(uint32_t faultMask);
-
-/**
- * @brief  Return the Control Register value
-* 
-*  @param  none
-*  @return uint32_t Control value
- *
- * Return the content of the control register
- */
-extern uint32_t __get_CONTROL(void);
-
-/**
- * @brief  Set the Control Register value
- *
- * @param  uint32_t Control value
- * @return none
- *
- * Set the control register
- */
-extern void __set_CONTROL(uint32_t control);
-
-/**
- * @brief  Reverse byte order in integer value
- *
- * @param  uint32_t value to reverse
- * @return uint32_t reversed value
- *
- * Reverse byte order in integer value
- */
-extern uint32_t __REV(uint32_t value);
-
-/**
- * @brief  Reverse byte order in unsigned short value
- *
- * @param  uint16_t value to reverse
- * @return uint32_t reversed value
- *
- * Reverse byte order in unsigned short value
- */
-extern uint32_t __REV16(uint16_t value);
-
-/*
- * Reverse byte order in signed short value with sign extension to integer
- *
- * @param  int16_t value to reverse
- * @return int32_t reversed value
- *
- * @brief  Reverse byte order in signed short value with sign extension to integer
- */
-extern int32_t __REVSH(int16_t value);
-
-/**
- * @brief  Reverse bit order of value
- *
- * @param  uint32_t value to reverse
- * @return uint32_t reversed value
- *
- * Reverse bit order of value
- */
-extern uint32_t __RBIT(uint32_t value);
-
-/**
- * @brief  LDR Exclusive
- *
- * @param  uint8_t* address
- * @return uint8_t value of (*address)
- *
- * Exclusive LDR command
- */
-extern uint8_t __LDREXB(uint8_t *addr);
-
-/**
- * @brief  LDR Exclusive
- *
- * @param  uint16_t* address
- * @return uint16_t value of (*address)
- *
- * Exclusive LDR command
- */
-extern uint16_t __LDREXH(uint16_t *addr);
-
-/**
- * @brief  LDR Exclusive
- *
- * @param  uint32_t* address
- * @return uint32_t value of (*address)
- *
- * Exclusive LDR command
- */
-extern uint32_t __LDREXW(uint32_t *addr);
-
-/**
- * @brief  STR Exclusive
- *
- * @param  uint8_t *address
- * @param  uint8_t value to store
- * @return uint32_t successful / failed
- *
- * Exclusive STR command
- */
-extern uint32_t __STREXB(uint8_t value, uint8_t *addr);
-
-/**
- * @brief  STR Exclusive
- *
- * @param  uint16_t *address
- * @param  uint16_t value to store
- * @return uint32_t successful / failed
- *
- * Exclusive STR command
- */
-extern uint32_t __STREXH(uint16_t value, uint16_t *addr);
-
-/**
- * @brief  STR Exclusive
- *
- * @param  uint32_t *address
- * @param  uint32_t value to store
- * @return uint32_t successful / failed
- *
- * Exclusive STR command
- */
-extern uint32_t __STREXW(uint32_t value, uint32_t *addr);
-
-
-#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/
-/* TASKING carm specific functions */
-
-/*
- * The CMSIS functions have been implemented as intrinsics in the compiler.
- * Please use "carm -?i" to get an up to date list of all instrinsics,
- * Including the CMSIS ones.
- */
-
-#endif
-
-
-
-/* ##########################   NVIC functions  #################################### */
-
-
-/**
- * @brief  Set the Priority Grouping in NVIC Interrupt Controller
- *
- * @param  uint32_t priority_grouping is priority grouping field
- * @return none 
- *
- * Set the priority grouping field using the required unlock sequence.
- * The parameter priority_grouping is assigned to the field 
- * SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used.
- * In case of a conflict between priority grouping and available
- * priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
- */
-static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-{
-  uint32_t reg_value;
-  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);                         /* only values 0..7 are used          */
-  
-  reg_value  = SCB->AIRCR;                                                    /* read old register configuration    */
-  reg_value &= ~((0xFFFFU << 16) | (0x0F << 8));                              /* clear bits to change               */
-  reg_value  = ((reg_value | NVIC_AIRCR_VECTKEY | (PriorityGroupTmp << 8)));  /* Insert write key and priorty group */
-  SCB->AIRCR = reg_value;
-}
-
-/**
- * @brief  Get the Priority Grouping from NVIC Interrupt Controller
- *
- * @param  none
- * @return uint32_t   priority grouping field 
- *
- * Get the priority grouping from NVIC Interrupt Controller.
- * priority grouping is SCB->AIRCR [10:8] PRIGROUP field.
- */
-static __INLINE uint32_t NVIC_GetPriorityGrouping(void)
-{
-  return ((SCB->AIRCR >> 8) & 0x07);                                          /* read priority grouping field */
-}
-
-/**
- * @brief  Enable Interrupt in NVIC Interrupt Controller
- *
- * @param  IRQn_Type IRQn specifies the interrupt number
- * @return none 
- *
- * Enable a device specific interupt in the NVIC interrupt controller.
- * The interrupt number cannot be a negative value.
- */
-static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
-}
-
-/**
- * @brief  Disable the interrupt line for external interrupt specified
- * 
- * @param  IRQn_Type IRQn is the positive number of the external interrupt
- * @return none
- * 
- * Disable a device specific interupt in the NVIC interrupt controller.
- * The interrupt number cannot be a negative value.
- */
-static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
-{
-  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
-}
-
-/**
- * @brief  Read the interrupt pending bit for a device specific interrupt source
- * 
- * @param  IRQn_Type IRQn is the number of the device specifc interrupt
- * @return uint32_t 1 if pending interrupt else 0
- *
- * Read the pending register in NVIC and return 1 if its status is pending, 
- * otherwise it returns 0
- */
-static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
-  return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
-}
-
-/**
- * @brief  Set the pending bit for an external interrupt
- * 
- * @param  IRQn_Type IRQn is the Number of the interrupt
- * @return none
- *
- * Set the pending bit for the specified interrupt.
- * The interrupt number cannot be a negative value.
- */
-static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
-  NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
-}
-
-/**
- * @brief  Clear the pending bit for an external interrupt
- *
- * @param  IRQn_Type IRQn is the Number of the interrupt
- * @return none
- *
- * Clear the pending bit for the specified interrupt. 
- * The interrupt number cannot be a negative value.
- */
-static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
-  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
-}
-
-/**
- * @brief  Read the active bit for an external interrupt
- *
- * @param  IRQn_Type  IRQn is the Number of the interrupt
- * @return uint32_t   1 if active else 0
- *
- * Read the active register in NVIC and returns 1 if its status is active, 
- * otherwise it returns 0.
- */
-static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
-{
-  return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
-}
-
-/**
- * @brief  Set the priority for an interrupt
- *
- * @param  IRQn_Type IRQn is the Number of the interrupt
- * @param  priority is the priority for the interrupt
- * @return none
- *
- * Set the priority for the specified interrupt. The interrupt 
- * number can be positive to specify an external (device specific) 
- * interrupt, or negative to specify an internal (core) interrupt. \n
- *
- * Note: The priority cannot be set for every core interrupt.
- */
-static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
-  if(IRQn < 0) {
-    SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */
-  else {
-    NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);    }        /* set Priority for device specific Interrupts      */
-}
-
-/**
- * @brief  Read the priority for an interrupt
- *
- * @param  IRQn_Type IRQn is the Number of the interrupt
- * @return uint32_t  priority is the priority for the interrupt
- *
- * Read the priority for the specified interrupt. The interrupt 
- * number can be positive to specify an external (device specific) 
- * interrupt, or negative to specify an internal (core) interrupt.
- *
- * The returned priority value is automatically aligned to the implemented
- * priority bits of the microcontroller.
- *
- * Note: The priority cannot be set for every core interrupt.
- */
-static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
-{
-
-  if(IRQn < 0) {
-    return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M3 system interrupts */
-  else {
-    return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)]           >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
-}
-
-
-/**
- * @brief  Encode the priority for an interrupt
- *
- * @param  uint32_t PriorityGroup   is the used priority group
- * @param  uint32_t PreemptPriority is the preemptive priority value (starting from 0)
- * @param  uint32_t SubPriority     is the sub priority value (starting from 0)
- * @return uint32_t                    the priority for the interrupt
- *
- * Encode the priority for an interrupt with the given priority group,
- * preemptive priority value and sub priority value.
- * In case of a conflict between priority grouping and available
- * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
- *
- * The returned priority value can be used for NVIC_SetPriority(...) function
- */
-static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
-{
-  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);                         /* only values 0..7 are used          */
-  uint32_t PreemptPriorityBits;
-  uint32_t SubPriorityBits;
-
-  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
-  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
- 
-  return (
-           ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
-           ((SubPriority     & ((1 << (SubPriorityBits    )) - 1)))
-         );
-}
-
-
-/**
- * @brief  Decode the priority of an interrupt
- *
- * @param  uint32_t   Priority       the priority for the interrupt
- * @param  uint32_t   PrioGroup   is the used priority group
- * @param  uint32_t* pPreemptPrio is the preemptive priority value (starting from 0)
- * @param  uint32_t* pSubPrio     is the sub priority value (starting from 0)
- * @return none
- *
- * Decode an interrupt priority value with the given priority group to 
- * preemptive priority value and sub priority value.
- * In case of a conflict between priority grouping and available
- * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
- *
- * The priority value can be retrieved with NVIC_GetPriority(...) function
- */
-static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
-{
-  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);                         /* only values 0..7 are used          */
-  uint32_t PreemptPriorityBits;
-  uint32_t SubPriorityBits;
-
-  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
-  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
-  
-  *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
-  *pSubPriority     = (Priority                   ) & ((1 << (SubPriorityBits    )) - 1);
-}
-
-
-
-/* ##################################    SysTick function  ############################################ */
-
-#if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0)
-
-/* SysTick constants */
-#define SYSTICK_ENABLE              0                                          /* Config-Bit to start or stop the SysTick Timer                         */
-#define SYSTICK_TICKINT             1                                          /* Config-Bit to enable or disable the SysTick interrupt                 */
-#define SYSTICK_CLKSOURCE           2                                          /* Clocksource has the offset 2 in SysTick Control and Status Register   */
-#define SYSTICK_MAXCOUNT       ((1<<24) -1)                                    /* SysTick MaxCount                                                      */
-
-/**
- * @brief  Initialize and start the SysTick counter and its interrupt.
- *
- * @param  uint32_t ticks is the number of ticks between two interrupts
- * @return  none
- *
- * Initialise the system tick timer and its interrupt and start the
- * system tick timer / counter in free running mode to generate 
- * periodical interrupts.
- */
-static __INLINE uint32_t SysTick_Config(uint32_t ticks)
-{ 
-  if (ticks > SYSTICK_MAXCOUNT)  return (1);                                             /* Reload value impossible */
-
-  SysTick->LOAD  =  (ticks & SYSTICK_MAXCOUNT) - 1;                                      /* set reload register */
-  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);                            /* set Priority for Cortex-M0 System Interrupts */
-  SysTick->VAL   =  (0x00);                                                              /* Load the SysTick Counter Value */
-  SysTick->CTRL = (1 << SYSTICK_CLKSOURCE) | (1<<SYSTICK_ENABLE) | (1<<SYSTICK_TICKINT); /* Enable SysTick IRQ and SysTick Timer */
-  return (0);                                                                            /* Function successful */
-}
-
-#endif
-
-
-
-
-
-/* ##################################    Reset function  ############################################ */
-
-/**
- * @brief  Initiate a system reset request.
- *
- * @param   none
- * @return  none
- *
- * Initialize a system reset request to reset the MCU
- */
-static __INLINE void NVIC_SystemReset(void)
-{
-  SCB->AIRCR  = (NVIC_AIRCR_VECTKEY | (SCB->AIRCR & (0x700)) | (1<<NVIC_SYSRESETREQ)); /* Keep priority group unchanged */
-  __DSB();                                                                             /* Ensure completion of memory access */              
-  while(1);                                                                            /* wait until reset */
-}
-
-
-/* ##################################    Debug Output  function  ############################################ */
-
-
-/**
- * @brief  Outputs a character via the ITM channel 0
- *
- * @param   uint32_t character to output
- * @return  uint32_t input character
- *
- * The function outputs a character via the ITM channel 0. 
- * The function returns when no debugger is connected that has booked the output.  
- * It is blocking when a debugger is connected, but the previous character send is not transmitted. 
- */
-static __INLINE uint32_t ITM_SendChar (uint32_t ch)
-{
-  if (ch == '\n') ITM_SendChar('\r');
-  
-  if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA)  &&
-      (ITM->TCR & ITM_TCR_ITMENA)                  &&
-      (ITM->TER & (1UL << 0))  ) 
-  {
-    while (ITM->PORT[0].u32 == 0);
-    ITM->PORT[0].u8 = (uint8_t) ch;
-  }  
-  return (ch);
-}
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CM3_CORE_H__ */
-
-/*lint -restore */
diff --git a/bsp/lpc176x/CMSIS/startup_LPC17xx.s b/bsp/lpc176x/CMSIS/startup_LPC17xx.s
deleted file mode 100644
index ec2aac3fc9e2a8c0aec12f4ee6bc36f91399e4ec..0000000000000000000000000000000000000000
--- a/bsp/lpc176x/CMSIS/startup_LPC17xx.s
+++ /dev/null
@@ -1,280 +0,0 @@
-;/*****************************************************************************
-; * @file:    startup_LPC17xx.s
-; * @purpose: CMSIS Cortex-M3 Core Device Startup File 
-; *           for the NXP LPC17xx Device Series 
-; * @version: V1.0
-; * @date:    25. Nov. 2008
-; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
-; *
-; * Copyright (C) 2008 ARM Limited. All rights reserved.
-; * ARM Limited (ARM) is supplying this software for use with Cortex-M3 
-; * processor based microcontrollers.  This file can be freely distributed 
-; * within development tools that are supporting such ARM based processors. 
-; *
-; * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-; *
-; *****************************************************************************/
-
-
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x00000200
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
-__initial_sp
-
-
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size       EQU     0x00000000
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-
-__Vectors       DCD     __initial_sp              ; Top of Stack
-                DCD     Reset_Handler             ; Reset Handler
-                DCD     NMI_Handler               ; NMI Handler
-                DCD     HardFault_Handler         ; Hard Fault Handler
-                DCD     MemManage_Handler         ; MPU Fault Handler
-                DCD     BusFault_Handler          ; Bus Fault Handler
-                DCD     UsageFault_Handler        ; Usage Fault Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     SVC_Handler               ; SVCall Handler
-                DCD     DebugMon_Handler          ; Debug Monitor Handler
-                DCD     0                         ; Reserved
-                DCD     PendSV_Handler            ; PendSV Handler
-                DCD     SysTick_Handler           ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WDT_IRQHandler            ; 16: Watchdog Timer
-                DCD     TIMER0_IRQHandler         ; 17: Timer0
-                DCD     TIMER1_IRQHandler         ; 18: Timer1
-                DCD     TIMER2_IRQHandler         ; 19: Timer2
-                DCD     TIMER3_IRQHandler         ; 20: Timer3
-                DCD     UART0_IRQHandler          ; 21: UART0
-                DCD     UART1_IRQHandler          ; 22: UART1
-                DCD     UART2_IRQHandler          ; 23: UART2
-                DCD     UART3_IRQHandler          ; 24: UART3
-                DCD     PWM1_IRQHandler           ; 25: PWM1
-                DCD     I2C0_IRQHandler           ; 26: I2C0
-                DCD     I2C1_IRQHandler           ; 27: I2C1
-                DCD     I2C2_IRQHandler           ; 28: I2C2
-                DCD     SPI_IRQHandler            ; 29: SPI
-                DCD     SSP0_IRQHandler           ; 30: SSP0
-                DCD     SSP1_IRQHandler           ; 31: SSP1
-                DCD     PLL0_IRQHandler           ; 32: PLL0 Lock (Main PLL)
-                DCD     RTC_IRQHandler            ; 33: Real Time Clock
-                DCD     EINT0_IRQHandler          ; 34: External Interrupt 0
-                DCD     EINT1_IRQHandler          ; 35: External Interrupt 1
-                DCD     EINT2_IRQHandler          ; 36: External Interrupt 2
-                DCD     EINT3_IRQHandler          ; 37: External Interrupt 3
-                DCD     ADC_IRQHandler            ; 38: A/D Converter
-                DCD     BOD_IRQHandler            ; 39: Brown-Out Detect
-                DCD     USB_IRQHandler            ; 40: USB
-                DCD     CAN_IRQHandler            ; 41: CAN
-                DCD     DMA_IRQHandler            ; 42: General Purpose DMA
-                DCD     I2S_IRQHandler            ; 43: I2S
-                DCD     ENET_IRQHandler           ; 44: Ethernet
-                DCD     RIT_IRQHandler            ; 45: Repetitive Interrupt Timer
-                DCD     MCPWM_IRQHandler          ; 46: Motor Control PWM
-                DCD     QEI_IRQHandler            ; 47: Quadrature Encoder Interface
-                DCD     PLL1_IRQHandler           ; 48: PLL1 Lock (USB PLL)
-				DCD		USBActivity_IRQHandler    ; USB Activity interrupt to wakeup
-				DCD		CANActivity_IRQHandler    ; CAN Activity interrupt to wakeup
-
-
-                IF      :LNOT::DEF:NO_CRP
-                AREA    |.ARM.__at_0x02FC|, CODE, READONLY
-CRP_Key         DCD     0xFFFFFFFF
-                ENDIF
-
-
-                AREA    |.text|, CODE, READONLY
-
-
-; Reset Handler
-
-Reset_Handler   PROC
-                EXPORT  Reset_Handler             [WEAK]
-                IMPORT  __main
-                LDR     R0, =__main
-                BX      R0
-                ENDP
-
-
-; Dummy Exception Handlers (infinite loops which can be modified)                
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler               [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler         [WEAK]
-                B       .
-                ENDP
-MemManage_Handler\
-                PROC
-                EXPORT  MemManage_Handler         [WEAK]
-                B       .
-                ENDP
-BusFault_Handler\
-                PROC
-                EXPORT  BusFault_Handler          [WEAK]
-                B       .
-                ENDP
-UsageFault_Handler\
-                PROC
-                EXPORT  UsageFault_Handler        [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler               [WEAK]
-                B       .
-                ENDP
-DebugMon_Handler\
-                PROC
-                EXPORT  DebugMon_Handler          [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler            [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler           [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WDT_IRQHandler            [WEAK]
-                EXPORT  TIMER0_IRQHandler         [WEAK]
-                EXPORT  TIMER1_IRQHandler         [WEAK]
-                EXPORT  TIMER2_IRQHandler         [WEAK]
-                EXPORT  TIMER3_IRQHandler         [WEAK]
-                EXPORT  UART0_IRQHandler          [WEAK]
-                EXPORT  UART1_IRQHandler          [WEAK]
-                EXPORT  UART2_IRQHandler          [WEAK]
-                EXPORT  UART3_IRQHandler          [WEAK]
-                EXPORT  PWM1_IRQHandler           [WEAK]
-                EXPORT  I2C0_IRQHandler           [WEAK]
-                EXPORT  I2C1_IRQHandler           [WEAK]
-                EXPORT  I2C2_IRQHandler           [WEAK]
-                EXPORT  SPI_IRQHandler            [WEAK]
-                EXPORT  SSP0_IRQHandler           [WEAK]
-                EXPORT  SSP1_IRQHandler           [WEAK]
-                EXPORT  PLL0_IRQHandler           [WEAK]
-                EXPORT  RTC_IRQHandler            [WEAK]
-                EXPORT  EINT0_IRQHandler          [WEAK]
-                EXPORT  EINT1_IRQHandler          [WEAK]
-                EXPORT  EINT2_IRQHandler          [WEAK]
-                EXPORT  EINT3_IRQHandler          [WEAK]
-                EXPORT  ADC_IRQHandler            [WEAK]
-                EXPORT  BOD_IRQHandler            [WEAK]
-                EXPORT  USB_IRQHandler            [WEAK]
-                EXPORT  CAN_IRQHandler            [WEAK]
-                EXPORT  DMA_IRQHandler            [WEAK]
-                EXPORT  I2S_IRQHandler            [WEAK]
-                EXPORT  ENET_IRQHandler           [WEAK]
-                EXPORT  RIT_IRQHandler            [WEAK]
-                EXPORT  MCPWM_IRQHandler          [WEAK]
-                EXPORT  QEI_IRQHandler            [WEAK]
-                EXPORT  PLL1_IRQHandler           [WEAK]
-				EXPORT  USBActivity_IRQHandler    [WEAK]
-				EXPORT  CANActivity_IRQHandler    [WEAK]
-
-WDT_IRQHandler           
-TIMER0_IRQHandler         
-TIMER1_IRQHandler         
-TIMER2_IRQHandler         
-TIMER3_IRQHandler         
-UART0_IRQHandler          
-UART1_IRQHandler          
-UART2_IRQHandler          
-UART3_IRQHandler          
-PWM1_IRQHandler           
-I2C0_IRQHandler           
-I2C1_IRQHandler           
-I2C2_IRQHandler           
-SPI_IRQHandler            
-SSP0_IRQHandler           
-SSP1_IRQHandler           
-PLL0_IRQHandler           
-RTC_IRQHandler            
-EINT0_IRQHandler          
-EINT1_IRQHandler          
-EINT2_IRQHandler          
-EINT3_IRQHandler          
-ADC_IRQHandler            
-BOD_IRQHandler            
-USB_IRQHandler            
-CAN_IRQHandler            
-DMA_IRQHandler          
-I2S_IRQHandler            
-ENET_IRQHandler       
-RIT_IRQHandler          
-MCPWM_IRQHandler             
-QEI_IRQHandler            
-PLL1_IRQHandler           
-USBActivity_IRQHandler
-CANActivity_IRQHandler
-
-                B       .
-
-                ENDP
-
-
-                ALIGN
-
-
-; User Initial Stack & Heap
-
-                IF      :DEF:__MICROLIB
-                
-                EXPORT  __initial_sp
-                EXPORT  __heap_base
-                EXPORT  __heap_limit
-                
-                ELSE
-                
-                IMPORT  __use_two_region_memory
-                EXPORT  __user_initial_stackheap
-__user_initial_stackheap
-
-                LDR     R0, =  Heap_Mem
-                LDR     R1, =(Stack_Mem + Stack_Size)
-                LDR     R2, = (Heap_Mem +  Heap_Size)
-                LDR     R3, = Stack_Mem
-                BX      LR
-
-                ALIGN
-
-                ENDIF
-
-
-                END
diff --git a/bsp/lpc176x/CMSIS/system_LPC17xx.c b/bsp/lpc176x/CMSIS/system_LPC17xx.c
deleted file mode 100644
index 8e5e883f9bc0f96f484337e593a227409b29b97c..0000000000000000000000000000000000000000
--- a/bsp/lpc176x/CMSIS/system_LPC17xx.c
+++ /dev/null
@@ -1,495 +0,0 @@
-/******************************************************************************
- * @file:    system_LPC17xx.c
- * @purpose: CMSIS Cortex-M3 Device Peripheral Access Layer Source File
- *           for the NXP LPC17xx Device Series 
- * @version: V1.1
- * @date:    18th May 2009
- *----------------------------------------------------------------------------
- *
- * Copyright (C) 2008 ARM Limited. All rights reserved.
- *
- * ARM Limited (ARM) is supplying this software for use with Cortex-M3 
- * processor based microcontrollers.  This file can be freely distributed 
- * within development tools that are supporting such ARM based processors. 
- *
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-
-
-#include <stdint.h>
-#include "LPC17xx.h"
-
-/*
-//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
-*/
-
-/*--------------------- Clock Configuration ----------------------------------
-//
-// <e> Clock Configuration
-//   <h> System Controls and Status Register (SCS)
-//     <o1.4>    OSCRANGE: Main Oscillator Range Select
-//                     <0=>  1 MHz to 20 MHz
-//                     <1=> 15 MHz to 24 MHz
-//     <e1.5>       OSCEN: Main Oscillator Enable
-//     </e>
-//   </h>
-//
-//   <h> Clock Source Select Register (CLKSRCSEL)
-//     <o2.0..1>   CLKSRC: PLL Clock Source Selection
-//                     <0=> Internal RC oscillator
-//                     <1=> Main oscillator
-//                     <2=> RTC oscillator
-//   </h>
-//
-//   <e3> PLL0 Configuration (Main PLL)
-//     <h> PLL0 Configuration Register (PLL0CFG)
-//                     <i> F_cco0 = (2 * M * F_in) / N
-//                     <i> F_in must be in the range of 32 kHz to 50 MHz
-//                     <i> F_cco0 must be in the range of 275 MHz to 550 MHz
-//       <o4.0..14>  MSEL: PLL Multiplier Selection
-//                     <6-32768><#-1>
-//                     <i> M Value
-//       <o4.16..23> NSEL: PLL Divider Selection
-//                     <1-256><#-1>
-//                     <i> N Value
-//     </h>
-//   </e>
-//
-//   <e5> PLL1 Configuration (USB PLL)
-//     <h> PLL1 Configuration Register (PLL1CFG)
-//                     <i> F_usb = M * F_osc or F_usb = F_cco1 / (2 * P)
-//                     <i> F_cco1 = F_osc * M * 2 * P
-//                     <i> F_cco1 must be in the range of 156 MHz to 320 MHz
-//       <o6.0..4>   MSEL: PLL Multiplier Selection
-//                     <1-32><#-1>
-//                     <i> M Value (for USB maximum value is 4)
-//       <o6.5..6>   PSEL: PLL Divider Selection
-//                     <0=> 1
-//                     <1=> 2
-//                     <2=> 4
-//                     <3=> 8
-//                     <i> P Value
-//     </h>
-//   </e>
-//
-//   <h> CPU Clock Configuration Register (CCLKCFG)
-//     <o7.0..7>  CCLKSEL: Divide Value for CPU Clock from PLL0
-//                     <3-256><#-1>
-//   </h>
-//
-//   <h> USB Clock Configuration Register (USBCLKCFG)
-//     <o8.0..3>   USBSEL: Divide Value for USB Clock from PLL1
-//                     <0-15>
-//                     <i> Divide is USBSEL + 1
-//   </h>
-//
-//   <h> Peripheral Clock Selection Register 0 (PCLKSEL0)
-//     <o9.0..1>    PCLK_WDT: Peripheral Clock Selection for WDT
-//                     <0=> Pclk = Cclk / 4
-//                     <1=> Pclk = Cclk
-//                     <2=> Pclk = Cclk / 2
-//                     <3=> Pclk = Hclk / 8
-//     <o9.2..3>    PCLK_TIMER0: Peripheral Clock Selection for TIMER0
-//                     <0=> Pclk = Cclk / 4
-//                     <1=> Pclk = Cclk
-//                     <2=> Pclk = Cclk / 2
-//                     <3=> Pclk = Hclk / 8
-//     <o9.4..5>    PCLK_TIMER1: Peripheral Clock Selection for TIMER1
-//                     <0=> Pclk = Cclk / 4
-//                     <1=> Pclk = Cclk
-//                     <2=> Pclk = Cclk / 2
-//                     <3=> Pclk = Hclk / 8
-//     <o9.6..7>    PCLK_UART0: Peripheral Clock Selection for UART0
-//                     <0=> Pclk = Cclk / 4
-//                     <1=> Pclk = Cclk
-//                     <2=> Pclk = Cclk / 2
-//                     <3=> Pclk = Hclk / 8
-//     <o9.8..9>    PCLK_UART1: Peripheral Clock Selection for UART1
-//                     <0=> Pclk = Cclk / 4
-//                     <1=> Pclk = Cclk
-//                     <2=> Pclk = Cclk / 2
-//                     <3=> Pclk = Hclk / 8
-//     <o9.12..13>  PCLK_PWM1: Peripheral Clock Selection for PWM1
-//                     <0=> Pclk = Cclk / 4
-//                     <1=> Pclk = Cclk
-//                     <2=> Pclk = Cclk / 2
-//                     <3=> Pclk = Hclk / 8
-//     <o9.14..15>  PCLK_I2C0: Peripheral Clock Selection for I2C0
-//                     <0=> Pclk = Cclk / 4
-//                     <1=> Pclk = Cclk
-//                     <2=> Pclk = Cclk / 2
-//                     <3=> Pclk = Hclk / 8
-//     <o9.16..17>  PCLK_SPI: Peripheral Clock Selection for SPI
-//                     <0=> Pclk = Cclk / 4
-//                     <1=> Pclk = Cclk
-//                     <2=> Pclk = Cclk / 2
-//                     <3=> Pclk = Hclk / 8
-//     <o9.20..21>  PCLK_SSP1: Peripheral Clock Selection for SSP1
-//                     <0=> Pclk = Cclk / 4
-//                     <1=> Pclk = Cclk
-//                     <2=> Pclk = Cclk / 2
-//                     <3=> Pclk = Hclk / 8
-//     <o9.22..23>  PCLK_DAC: Peripheral Clock Selection for DAC
-//                     <0=> Pclk = Cclk / 4
-//                     <1=> Pclk = Cclk
-//                     <2=> Pclk = Cclk / 2
-//                     <3=> Pclk = Hclk / 8
-//     <o9.24..25>  PCLK_ADC: Peripheral Clock Selection for ADC
-//                     <0=> Pclk = Cclk / 4
-//                     <1=> Pclk = Cclk
-//                     <2=> Pclk = Cclk / 2
-//                     <3=> Pclk = Hclk / 8
-//     <o9.26..27>  PCLK_CAN1: Peripheral Clock Selection for CAN1
-//                     <0=> Pclk = Cclk / 4
-//                     <1=> Pclk = Cclk
-//                     <2=> Pclk = Cclk / 2
-//                     <3=> Pclk = Hclk / 6
-//     <o9.28..29>  PCLK_CAN2: Peripheral Clock Selection for CAN2
-//                     <0=> Pclk = Cclk / 4
-//                     <1=> Pclk = Cclk
-//                     <2=> Pclk = Cclk / 2
-//                     <3=> Pclk = Hclk / 6
-//     <o9.30..31>  PCLK_ACF: Peripheral Clock Selection for ACF
-//                     <0=> Pclk = Cclk / 4
-//                     <1=> Pclk = Cclk
-//                     <2=> Pclk = Cclk / 2
-//                     <3=> Pclk = Hclk / 6
-//   </h>
-//
-//   <h> Peripheral Clock Selection Register 1 (PCLKSEL1)
-//     <o10.0..1>   PCLK_QEI: Peripheral Clock Selection for the Quadrature Encoder Interface
-//                     <0=> Pclk = Cclk / 4
-//                     <1=> Pclk = Cclk
-//                     <2=> Pclk = Cclk / 2
-//                     <3=> Pclk = Hclk / 8
-//     <o10.2..3>   PCLK_GPIO: Peripheral Clock Selection for GPIOs
-//                     <0=> Pclk = Cclk / 4
-//                     <1=> Pclk = Cclk
-//                     <2=> Pclk = Cclk / 2
-//                     <3=> Pclk = Hclk / 8
-//     <o10.4..5>   PCLK_PCB: Peripheral Clock Selection for the Pin Connect Block
-//                     <0=> Pclk = Cclk / 4
-//                     <1=> Pclk = Cclk
-//                     <2=> Pclk = Cclk / 2
-//                     <3=> Pclk = Hclk / 8
-//     <o10.6..7>   PCLK_I2C1: Peripheral Clock Selection for I2C1
-//                     <0=> Pclk = Cclk / 4
-//                     <1=> Pclk = Cclk
-//                     <2=> Pclk = Cclk / 2
-//                     <3=> Pclk = Hclk / 8
-//     <o10.10..11> PCLK_SSP0: Peripheral Clock Selection for SSP0
-//                     <0=> Pclk = Cclk / 4
-//                     <1=> Pclk = Cclk
-//                     <2=> Pclk = Cclk / 2
-//                     <3=> Pclk = Hclk / 8
-//     <o10.12..13> PCLK_TIMER2: Peripheral Clock Selection for TIMER2
-//                     <0=> Pclk = Cclk / 4
-//                     <1=> Pclk = Cclk
-//                     <2=> Pclk = Cclk / 2
-//                     <3=> Pclk = Hclk / 8
-//     <o10.14..15> PCLK_TIMER3: Peripheral Clock Selection for TIMER3
-//                     <0=> Pclk = Cclk / 4
-//                     <1=> Pclk = Cclk
-//                     <2=> Pclk = Cclk / 2
-//                     <3=> Pclk = Hclk / 8
-//     <o10.16..17> PCLK_UART2: Peripheral Clock Selection for UART2
-//                     <0=> Pclk = Cclk / 4
-//                     <1=> Pclk = Cclk
-//                     <2=> Pclk = Cclk / 2
-//                     <3=> Pclk = Hclk / 8
-//     <o10.18..19> PCLK_UART3: Peripheral Clock Selection for UART3
-//                     <0=> Pclk = Cclk / 4
-//                     <1=> Pclk = Cclk
-//                     <2=> Pclk = Cclk / 2
-//                     <3=> Pclk = Hclk / 8
-//     <o10.20..21> PCLK_I2C2: Peripheral Clock Selection for I2C2
-//                     <0=> Pclk = Cclk / 4
-//                     <1=> Pclk = Cclk
-//                     <2=> Pclk = Cclk / 2
-//                     <3=> Pclk = Hclk / 8
-//     <o10.22..23> PCLK_I2S: Peripheral Clock Selection for I2S
-//                     <0=> Pclk = Cclk / 4
-//                     <1=> Pclk = Cclk
-//                     <2=> Pclk = Cclk / 2
-//                     <3=> Pclk = Hclk / 8
-//     <o10.26..27> PCLK_RIT: Peripheral Clock Selection for the Repetitive Interrupt Timer
-//                     <0=> Pclk = Cclk / 4
-//                     <1=> Pclk = Cclk
-//                     <2=> Pclk = Cclk / 2
-//                     <3=> Pclk = Hclk / 8
-//     <o10.28..29> PCLK_SYSCON: Peripheral Clock Selection for the System Control Block
-//                     <0=> Pclk = Cclk / 4
-//                     <1=> Pclk = Cclk
-//                     <2=> Pclk = Cclk / 2
-//                     <3=> Pclk = Hclk / 8
-//     <o10.30..31> PCLK_MC: Peripheral Clock Selection for the Motor Control PWM
-//                     <0=> Pclk = Cclk / 4
-//                     <1=> Pclk = Cclk
-//                     <2=> Pclk = Cclk / 2
-//                     <3=> Pclk = Hclk / 8
-//   </h>
-//
-//   <h> Power Control for Peripherals Register (PCONP)
-//     <o11.1>      PCTIM0: Timer/Counter 0 power/clock enable
-//     <o11.2>      PCTIM1: Timer/Counter 1 power/clock enable
-//     <o11.3>      PCUART0: UART 0 power/clock enable
-//     <o11.4>      PCUART1: UART 1 power/clock enable
-//     <o11.6>      PCPWM1: PWM 1 power/clock enable
-//     <o11.7>      PCI2C0: I2C interface 0 power/clock enable
-//     <o11.8>      PCSPI: SPI interface power/clock enable
-//     <o11.9>      PCRTC: RTC power/clock enable
-//     <o11.10>     PCSSP1: SSP interface 1 power/clock enable
-//     <o11.12>     PCAD: A/D converter power/clock enable
-//     <o11.13>     PCCAN1: CAN controller 1 power/clock enable
-//     <o11.14>     PCCAN2: CAN controller 2 power/clock enable
-//     <o11.15>     PCGPIO: GPIOs power/clock enable
-//     <o11.16>     PCRIT: Repetitive interrupt timer power/clock enable
-//     <o11.17>     PCMC: Motor control PWM power/clock enable
-//     <o11.18>     PCQEI: Quadrature encoder interface power/clock enable
-//     <o11.19>     PCI2C1: I2C interface 1 power/clock enable
-//     <o11.21>     PCSSP0: SSP interface 0 power/clock enable
-//     <o11.22>     PCTIM2: Timer 2 power/clock enable
-//     <o11.23>     PCTIM3: Timer 3 power/clock enable
-//     <o11.24>     PCUART2: UART 2 power/clock enable
-//     <o11.25>     PCUART3: UART 3 power/clock enable
-//     <o11.26>     PCI2C2: I2C interface 2 power/clock enable
-//     <o11.27>     PCI2S: I2S interface power/clock enable
-//     <o11.29>     PCGPDMA: GP DMA function power/clock enable
-//     <o11.30>     PCENET: Ethernet block power/clock enable
-//     <o11.31>     PCUSB: USB interface power/clock enable
-//   </h>
-//
-//   <h> Clock Output Configuration Register (CLKOUTCFG)
-//     <o12.0..3>   CLKOUTSEL: Selects clock source for CLKOUT
-//                     <0=> CPU clock
-//                     <1=> Main oscillator
-//                     <2=> Internal RC oscillator
-//                     <3=> USB clock
-//                     <4=> RTC oscillator
-//     <o12.4..7>   CLKOUTDIV: Selects clock divider for CLKOUT
-//                     <1-16><#-1>
-//     <o12.8>      CLKOUT_EN: CLKOUT enable control
-//   </h>
-//
-// </e>
-*/
-#define CLOCK_SETUP           1
-#define SCS_Val               0x00000020
-#define CLKSRCSEL_Val         0x00000001
-#define PLL0_SETUP            1
-#define PLL0CFG_Val           0x0000000B
-#define PLL1_SETUP            1
-#define PLL1CFG_Val           0x00000023
-#define CCLKCFG_Val           0x00000003
-#define USBCLKCFG_Val         0x00000000
-#define PCLKSEL0_Val          0x00000000
-#define PCLKSEL1_Val          0x00000000
-#define PCONP_Val             0x042887DE
-#define CLKOUTCFG_Val         0x00000000
-
-
-/*--------------------- Flash Accelerator Configuration ----------------------
-//
-// <e> Flash Accelerator Configuration
-//   <o1.0..1>   FETCHCFG: Fetch Configuration
-//               <0=> Instruction fetches from flash are not buffered
-//               <1=> One buffer is used for all instruction fetch buffering
-//               <2=> All buffers may be used for instruction fetch buffering
-//               <3=> Reserved (do not use this setting)
-//   <o1.2..3>   DATACFG: Data Configuration
-//               <0=> Data accesses from flash are not buffered
-//               <1=> One buffer is used for all data access buffering
-//               <2=> All buffers may be used for data access buffering
-//               <3=> Reserved (do not use this setting)
-//   <o1.4>      ACCEL: Acceleration Enable
-//   <o1.5>      PREFEN: Prefetch Enable
-//   <o1.6>      PREFOVR: Prefetch Override
-//   <o1.12..15> FLASHTIM: Flash Access Time
-//               <0=> 1 CPU clock (for CPU clock up to 20 MHz)
-//               <1=> 2 CPU clocks (for CPU clock up to 40 MHz)
-//               <2=> 3 CPU clocks (for CPU clock up to 60 MHz)
-//               <3=> 4 CPU clocks (for CPU clock up to 80 MHz)
-//               <4=> 5 CPU clocks (for CPU clock up to 100 MHz)
-//               <5=> 6 CPU clocks (for any CPU clock)
-// </e>
-*/
-#define FLASH_SETUP           1
-#define FLASHCFG_Val          0x0000303A
-
-/*
-//-------- <<< end of configuration section >>> ------------------------------
-*/
-
-/*----------------------------------------------------------------------------
-  Check the register settings
- *----------------------------------------------------------------------------*/
-#define CHECK_RANGE(val, min, max)                ((val < min) || (val > max))
-#define CHECK_RSVD(val, mask)                     (val & mask)
-
-/* Clock Configuration -------------------------------------------------------*/
-#if (CHECK_RSVD((SCS_Val),       ~0x00000030))
-   #error "SCS: Invalid values of reserved bits!"
-#endif
-
-#if (CHECK_RANGE((CLKSRCSEL_Val), 0, 2))
-   #error "CLKSRCSEL: Value out of range!"
-#endif
-
-#if (CHECK_RSVD((PLL0CFG_Val),   ~0x00FF7FFF))
-   #error "PLL0CFG: Invalid values of reserved bits!"
-#endif
-
-#if (CHECK_RSVD((PLL1CFG_Val),   ~0x0000007F))
-   #error "PLL1CFG: Invalid values of reserved bits!"
-#endif
-
-#if ((CCLKCFG_Val != 0) && (((CCLKCFG_Val - 1) % 2)))
-   #error "CCLKCFG: CCLKSEL field does not contain only odd values or 0!"
-#endif
-
-#if (CHECK_RSVD((USBCLKCFG_Val), ~0x0000000F))
-   #error "USBCLKCFG: Invalid values of reserved bits!"
-#endif
-
-#if (CHECK_RSVD((PCLKSEL0_Val),   0x000C0C00))
-   #error "PCLKSEL0: Invalid values of reserved bits!"
-#endif
-
-#if (CHECK_RSVD((PCLKSEL1_Val),   0x03000300))
-   #error "PCLKSEL1: Invalid values of reserved bits!"
-#endif
-
-#if (CHECK_RSVD((PCONP_Val),      0x10100821))
-   #error "PCONP: Invalid values of reserved bits!"
-#endif
-
-#if (CHECK_RSVD((CLKOUTCFG_Val), ~0x000001FF))
-   #error "CLKOUTCFG: Invalid values of reserved bits!"
-#endif
-
-/* Flash Accelerator Configuration -------------------------------------------*/
-#if (CHECK_RSVD((FLASHCFG_Val), ~0x0000F07F))
-   #error "FLASHCFG: Invalid values of reserved bits!"
-#endif
-
-
-/*----------------------------------------------------------------------------
-  DEFINES
- *----------------------------------------------------------------------------*/
-    
-/*----------------------------------------------------------------------------
-  Define clocks
- *----------------------------------------------------------------------------*/
-#define XTAL        (12000000UL)        /* Oscillator frequency               */
-#define OSC_CLK     (      XTAL)        /* Main oscillator frequency          */
-#define RTC_CLK     (   32000UL)        /* RTC oscillator frequency           */
-#define IRC_OSC     ( 4000000UL)        /* Internal RC oscillator frequency   */
-
-
-/*----------------------------------------------------------------------------
-  Clock Variable definitions
- *----------------------------------------------------------------------------*/
-uint32_t SystemFrequency = IRC_OSC; /*!< System Clock Frequency (Core Clock)  */
-
-
-/**
- * Initialize the system
- *
- * @param  none
- * @return none
- *
- * @brief  Setup the microcontroller system.
- *         Initialize the System and update the SystemFrequency variable.
- */
-void SystemInit (void)
-{
-#if (CLOCK_SETUP)                       /* Clock Setup                        */
-  LPC_SC->SCS       = SCS_Val;
-  if (SCS_Val & (1 << 5)) {             /* If Main Oscillator is enabled      */
-    while ((LPC_SC->SCS & (1<<6)) == 0);/* Wait for Oscillator to be ready    */
-  }
-
-  LPC_SC->CCLKCFG   = CCLKCFG_Val;      /* Setup Clock Divider                */
-
-  LPC_SC->PCLKSEL0  = PCLKSEL0_Val;     /* Peripheral Clock Selection         */
-  LPC_SC->PCLKSEL1  = PCLKSEL1_Val;
-
-#if (PLL0_SETUP)
-  LPC_SC->CLKSRCSEL = CLKSRCSEL_Val;    /* Select Clock Source for PLL0       */
-  LPC_SC->PLL0CFG   = PLL0CFG_Val;
-  LPC_SC->PLL0CON   = 0x01;             /* PLL0 Enable                        */
-  LPC_SC->PLL0FEED  = 0xAA;
-  LPC_SC->PLL0FEED  = 0x55;
-  while (!(LPC_SC->PLL0STAT & (1<<26)));/* Wait for PLOCK0                    */
-
-  LPC_SC->PLL0CON   = 0x03;             /* PLL0 Enable & Connect              */
-  LPC_SC->PLL0FEED  = 0xAA;
-  LPC_SC->PLL0FEED  = 0x55;
-#endif
-
-#if (PLL1_SETUP)
-  LPC_SC->PLL1CFG   = PLL1CFG_Val;
-  LPC_SC->PLL1CON   = 0x01;             /* PLL1 Enable                        */
-  LPC_SC->PLL1FEED  = 0xAA;
-  LPC_SC->PLL1FEED  = 0x55;
-  while (!(LPC_SC->PLL1STAT & (1<<10)));/* Wait for PLOCK1                    */
-
-  LPC_SC->PLL1CON   = 0x03;             /* PLL1 Enable & Connect              */
-  LPC_SC->PLL1FEED  = 0xAA;
-  LPC_SC->PLL1FEED  = 0x55;
-#else
-  LPC_SC->USBCLKCFG = USBCLKCFG_Val;    /* Setup USB Clock Divider            */
-#endif
-
-  LPC_SC->PCONP     = PCONP_Val;        /* Power Control for Peripherals      */
-
-  LPC_SC->CLKOUTCFG = CLKOUTCFG_Val;    /* Clock Output Configuration         */
-#endif
-
-  /* Determine clock frequency according to clock register values             */
-  if (((LPC_SC->PLL0STAT >> 24)&3)==3) {/* If PLL0 enabled and connected      */
-    switch (LPC_SC->CLKSRCSEL & 0x03) {
-      case 0:                           /* Internal RC oscillator => PLL0     */
-      case 3:                           /* Reserved, default to Internal RC   */
-        SystemFrequency = (IRC_OSC * 
-                          (((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
-                          (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1))   /
-                          ((LPC_SC->CCLKCFG & 0xFF)+ 1));
-        break;
-      case 1:                           /* Main oscillator => PLL0            */
-        SystemFrequency = (OSC_CLK * 
-                          (((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
-                          (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1))   /
-                          ((LPC_SC->CCLKCFG & 0xFF)+ 1));
-        break;
-      case 2:                           /* RTC oscillator => PLL0             */
-        SystemFrequency = (RTC_CLK * 
-                          (((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
-                          (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1))   /
-                          ((LPC_SC->CCLKCFG & 0xFF)+ 1));
-        break;
-    }
-  } else {
-    switch (LPC_SC->CLKSRCSEL & 0x03) {
-      case 0:                           /* Internal RC oscillator => PLL0     */
-      case 3:                           /* Reserved, default to Internal RC   */
-        SystemFrequency = IRC_OSC / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
-        break;
-      case 1:                           /* Main oscillator => PLL0            */
-        SystemFrequency = OSC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
-        break;
-      case 2:                           /* RTC oscillator => PLL0             */
-        SystemFrequency = RTC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
-        break;
-    }
-  }
-
-#if (FLASH_SETUP == 1)                  /* Flash Accelerator Setup            */
-  LPC_SC->FLASHCFG  = FLASHCFG_Val;
-#endif
-}
diff --git a/bsp/lpc176x/CMSIS/system_LPC17xx.h b/bsp/lpc176x/CMSIS/system_LPC17xx.h
deleted file mode 100644
index e90b8e33ae50541fae0c0a4f867b76a637376a0d..0000000000000000000000000000000000000000
--- a/bsp/lpc176x/CMSIS/system_LPC17xx.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/******************************************************************************
- * @file:    system_LPC17xx.h
- * @purpose: CMSIS Cortex-M3 Device Peripheral Access Layer Header File
- *           for the NXP LPC17xx Device Series 
- * @version: V1.01
- * @date:    22. Jul. 2009
- *----------------------------------------------------------------------------
- *
- * Copyright (C) 2009 ARM Limited. All rights reserved.
- *
- * ARM Limited (ARM) is supplying this software for use with Cortex-M3 
- * processor based microcontrollers.  This file can be freely distributed 
- * within development tools that are supporting such ARM based processors. 
- *
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-
-
-#ifndef __SYSTEM_LPC17xx_H
-#define __SYSTEM_LPC17xx_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif 
-
-extern uint32_t SystemFrequency;    /*!< System Clock Frequency (Core Clock)  */
-
-
-/**
- * Initialize the system
- *
- * @param  none
- * @return none
- *
- * @brief  Setup the microcontroller system.
- *         Initialize the System and update the SystemFrequency variable.
- */
-extern void SystemInit (void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __SYSTEM_LPC17xx_H */
diff --git a/bsp/lpc176x/CMSIS/type.h b/bsp/lpc176x/CMSIS/type.h
deleted file mode 100644
index b9a7c518a1d846974a54d8bb10b70fc3b9ab3b2b..0000000000000000000000000000000000000000
--- a/bsp/lpc176x/CMSIS/type.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*****************************************************************************
- *   type.h:  Type definition Header file for NXP LPC17xx Family 
- *   Microprocessors
- *
- *   Copyright(C) 2009, NXP Semiconductor
- *   All rights reserved.
- *
- *   History
- *   2009.05.25  ver 1.00    Prelimnary version, first Release
- *
-******************************************************************************/
-#include <stdint.h>
-
-#ifndef __TYPE_H__
-#define __TYPE_H__
-
-#ifndef NULL
-#define NULL    ((void *)0)
-#endif
-
-#ifndef FALSE
-#define FALSE   (0)
-#endif
-
-#ifndef TRUE
-#define TRUE    (1)
-#endif
-
-
-typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
-typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
-
-#endif  /* __TYPE_H__ */