From 93122aaa195ff64d426b5c3d3112eb1743828c37 Mon Sep 17 00:00:00 2001 From: Bright Pan Date: Wed, 25 Mar 2015 10:44:02 +0800 Subject: [PATCH] [BSP]stm32f10x: Fix gpio driver for 144pins and 64pins --- bsp/stm32f10x/drivers/gpio.c | 216 ++++++++++++++++++++++++++++++++++- 1 file changed, 215 insertions(+), 1 deletion(-) diff --git a/bsp/stm32f10x/drivers/gpio.c b/bsp/stm32f10x/drivers/gpio.c index e7a2f7c3c..747b55b4d 100644 --- a/bsp/stm32f10x/drivers/gpio.c +++ b/bsp/stm32f10x/drivers/gpio.c @@ -18,7 +18,7 @@ #ifdef RT_USING_PIN -#define STM32F10X_PIN_NUMBERS 100 +#define STM32F10X_PIN_NUMBERS 100 //[ 64, 100, 144 ] #define __STM32_PIN(index, rcc, gpio, gpio_index) { 0, RCC_##rcc##Periph_GPIO##gpio, GPIO##gpio, GPIO_Pin_##gpio_index} #define __STM32_PIN_DEFAULT {-1, 0, 0, 0} @@ -34,6 +34,72 @@ struct pin_index static const struct pin_index pins[] = { +#if (STM32F10X_PIN_NUMBERS == 64) + __STM32_PIN_DEFAULT, + __STM32_PIN(2, APB2, C, 13), + __STM32_PIN(3, APB2, C, 14), + __STM32_PIN(4, APB2, C, 15), + __STM32_PIN(5, APB2, D, 0), + __STM32_PIN(6, APB2, D, 1), + __STM32_PIN_DEFAULT, + __STM32_PIN(8, APB2, C, 0), + __STM32_PIN(9, APB2, C, 1), + __STM32_PIN(10, APB2, C, 2), + __STM32_PIN(11, APB2, C, 3), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(14, APB2, A, 0), + __STM32_PIN(15, APB2, A, 1), + __STM32_PIN(16, APB2, A, 2), + __STM32_PIN(17, APB2, A, 3), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(20, APB2, A, 4), + __STM32_PIN(21, APB2, A, 5), + __STM32_PIN(22, APB2, A, 6), + __STM32_PIN(23, APB2, A, 7), + __STM32_PIN(24, APB2, C, 4), + __STM32_PIN(25, APB2, C, 5), + __STM32_PIN(26, APB2, B, 0), + __STM32_PIN(27, APB2, B, 1), + __STM32_PIN(28, APB2, B, 2), + __STM32_PIN(29, APB2, B, 10), + __STM32_PIN(30, APB2, B, 11), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(33, APB2, B, 12), + __STM32_PIN(34, APB2, B, 13), + __STM32_PIN(35, APB2, B, 14), + __STM32_PIN(36, APB2, B, 15), + __STM32_PIN(37, APB2, C, 6), + __STM32_PIN(38, APB2, C, 7), + __STM32_PIN(39, APB2, C, 8), + __STM32_PIN(40, APB2, C, 9), + __STM32_PIN(41, APB2, A, 8), + __STM32_PIN(42, APB2, A, 9), + __STM32_PIN(43, APB2, A, 10), + __STM32_PIN(44, APB2, A, 11), + __STM32_PIN(45, APB2, A, 12), + __STM32_PIN(46, APB2, A, 13), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(49, APB2, A, 14), + __STM32_PIN(50, APB2, A, 15), + __STM32_PIN(51, APB2, C, 10), + __STM32_PIN(52, APB2, C, 11), + __STM32_PIN(53, APB2, C, 12), + __STM32_PIN(54, APB2, D, 2), + __STM32_PIN(55, APB2, B, 3), + __STM32_PIN(56, APB2, B, 4), + __STM32_PIN(57, APB2, B, 5), + __STM32_PIN(58, APB2, B, 6), + __STM32_PIN(59, APB2, B, 7), + __STM32_PIN_DEFAULT, + __STM32_PIN(61, APB2, B, 8), + __STM32_PIN(62, APB2, B, 9), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, +#endif #if (STM32F10X_PIN_NUMBERS == 100) __STM32_PIN_DEFAULT, __STM32_PIN(1, APB2, E, 2), @@ -137,6 +203,154 @@ static const struct pin_index pins[] = __STM32_PIN_DEFAULT, __STM32_PIN_DEFAULT, #endif +#if (STM32F10X_PIN_NUMBERS == 144) + __STM32_PIN_DEFAULT, + __STM32_PIN(1, APB2, E, 2), + __STM32_PIN(2, APB2, E, 3), + __STM32_PIN(3, APB2, E, 4), + __STM32_PIN(4, APB2, E, 5), + __STM32_PIN(5, APB2, E, 6), + __STM32_PIN_DEFAULT, + __STM32_PIN(7, APB2, C, 13), + __STM32_PIN(8, APB2, C, 14), + __STM32_PIN(9, APB2, C, 15), + + __STM32_PIN(10, APB2, F, 0), + __STM32_PIN(11, APB2, F, 1), + __STM32_PIN(12, APB2, F, 2), + __STM32_PIN(13, APB2, F, 3), + __STM32_PIN(14, APB2, F, 4), + __STM32_PIN(15, APB2, F, 5), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(18, APB2, F, 6), + __STM32_PIN(19, APB2, F, 7), + __STM32_PIN(20, APB2, F, 8), + __STM32_PIN(21, APB2, F, 9), + __STM32_PIN(22, APB2, F, 10), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(26, APB2, C, 0), + __STM32_PIN(27, APB2, C, 1), + __STM32_PIN(28, APB2, C, 2), + __STM32_PIN(29, APB2, C, 3), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(34, APB2, A, 0), + __STM32_PIN(35, APB2, A, 1), + __STM32_PIN(36, APB2, A, 2), + __STM32_PIN(37, APB2, A, 3), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(40, APB2, A, 4), + __STM32_PIN(41, APB2, A, 5), + __STM32_PIN(42, APB2, A, 6), + __STM32_PIN(43, APB2, A, 7), + __STM32_PIN(44, APB2, C, 4), + __STM32_PIN(45, APB2, C, 5), + __STM32_PIN(46, APB2, B, 0), + __STM32_PIN(47, APB2, B, 1), + __STM32_PIN(48, APB2, B, 2), + __STM32_PIN(49, APB2, F, 11), + __STM32_PIN(50, APB2, F, 12), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(53, APB2, F, 13), + __STM32_PIN(54, APB2, F, 14), + __STM32_PIN(55, APB2, F, 15), + __STM32_PIN(56, APB2, G, 0), + __STM32_PIN(57, APB2, G, 1), + __STM32_PIN(58, APB2, E, 7), + __STM32_PIN(59, APB2, E, 8), + __STM32_PIN(60, APB2, E, 9), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(63, APB2, E, 10), + __STM32_PIN(64, APB2, E, 11), + __STM32_PIN(65, APB2, E, 12), + __STM32_PIN(66, APB2, E, 13), + __STM32_PIN(67, APB2, E, 14), + __STM32_PIN(68, APB2, E, 15), + __STM32_PIN(69, APB2, B, 10), + __STM32_PIN(70, APB2, B, 11), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(73, APB2, B, 12), + __STM32_PIN(74, APB2, B, 13), + __STM32_PIN(75, APB2, B, 14), + __STM32_PIN(76, APB2, B, 15), + __STM32_PIN(77, APB2, D, 8), + __STM32_PIN(78, APB2, D, 9), + __STM32_PIN(79, APB2, D, 10), + __STM32_PIN(80, APB2, D, 11), + __STM32_PIN(81, APB2, D, 12), + __STM32_PIN(82, APB2, D, 13), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(85, APB2, D, 14), + __STM32_PIN(86, APB2, D, 15), + __STM32_PIN(87, APB2, G, 2), + __STM32_PIN(88, APB2, G, 3), + __STM32_PIN(89, APB2, G, 4), + __STM32_PIN(90, APB2, G, 5), + __STM32_PIN(91, APB2, G, 6), + __STM32_PIN(92, APB2, G, 7), + __STM32_PIN(93, APB2, G, 8), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(96, APB2, C, 6), + __STM32_PIN(97, APB2, C, 7), + __STM32_PIN(98, APB2, C, 8), + __STM32_PIN(99, APB2, C, 9), + __STM32_PIN(100, APB2, A, 8), + __STM32_PIN(101, APB2, A, 9), + __STM32_PIN(102, APB2, A, 10), + __STM32_PIN(103, APB2, A, 11), + __STM32_PIN(104, APB2, A, 12), + __STM32_PIN(105, APB2, A, 13), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(109, APB2, A, 14), + __STM32_PIN(110, APB2, A, 15), + __STM32_PIN(111, APB2, C, 10), + __STM32_PIN(112, APB2, C, 11), + __STM32_PIN(113, APB2, C, 12), + __STM32_PIN(114, APB2, D, 0), + __STM32_PIN(115, APB2, D, 1), + __STM32_PIN(116, APB2, D, 2), + __STM32_PIN(117, APB2, D, 3), + __STM32_PIN(118, APB2, D, 4), + __STM32_PIN(119, APB2, D, 5), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(122, APB2, D, 6), + __STM32_PIN(123, APB2, D, 7), + __STM32_PIN(124, APB2, G, 9), + __STM32_PIN(125, APB2, G, 10), + __STM32_PIN(126, APB2, G, 11), + __STM32_PIN(127, APB2, G, 12), + __STM32_PIN(128, APB2, G, 13), + __STM32_PIN(129, APB2, G, 14), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(132, APB2, G, 15), + __STM32_PIN(133, APB2, B, 3), + __STM32_PIN(134, APB2, B, 4), + __STM32_PIN(135, APB2, B, 5), + __STM32_PIN(136, APB2, B, 6), + __STM32_PIN(137, APB2, B, 7), + __STM32_PIN_DEFAULT, + __STM32_PIN(139, APB2, B, 8), + __STM32_PIN(140, APB2, B, 9), + __STM32_PIN(141, APB2, E, 0), + __STM32_PIN(142, APB2, E, 1), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, +#endif }; -- GitLab