diff --git a/bsp/imx6ull-100ask-smart/applications/lcd_init.c b/bsp/imx6ull-100ask-smart/applications/lcd_init.c deleted file mode 100644 index 75fcfe9f19964fd62041b0961196dfb09057f9d3..0000000000000000000000000000000000000000 --- a/bsp/imx6ull-100ask-smart/applications/lcd_init.c +++ /dev/null @@ -1,27 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - */ -#include - -#if defined(RT_USING_RTGUI) || defined(PKG_USING_GUIENGINE) - -#include -int lcd_init(void) -{ - struct rt_device *device; - device = rt_device_find("lcd"); - if (device) - { - rtgui_graphic_set_device(device); - } - - return 0; -} -INIT_APP_EXPORT(lcd_init); - -#endif diff --git a/bsp/imx6ull-100ask-smart/drivers/board.c b/bsp/imx6ull-100ask-smart/drivers/board.c index 7087ad893af8a0b5297abc3d95a0cc59a730d990..bdb41b7a958a540998c81a4f581bf9ec3145e742 100644 --- a/bsp/imx6ull-100ask-smart/drivers/board.c +++ b/bsp/imx6ull-100ask-smart/drivers/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/imx6ull-100ask-smart/drivers/drv_timer.c b/bsp/imx6ull-100ask-smart/drivers/drv_timer.c index 03f497315eaf146c1c60a2f7dc2489718a1925e4..1b3eaeb05a711de8cf7fe37de9b8a3719d8a17cd 100644 --- a/bsp/imx6ull-100ask-smart/drivers/drv_timer.c +++ b/bsp/imx6ull-100ask-smart/drivers/drv_timer.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -25,22 +25,22 @@ static int g_sys_freq; /* System Counter */ struct sctr_regs { - rt_uint32_t cntcr; - rt_uint32_t cntsr; - rt_uint32_t cntcv1; - rt_uint32_t cntcv2; - rt_uint32_t resv1[4]; - rt_uint32_t cntfid0; - rt_uint32_t cntfid1; - rt_uint32_t cntfid2; - rt_uint32_t resv2[1001]; - rt_uint32_t counterid[1]; + rt_uint32_t cntcr; + rt_uint32_t cntsr; + rt_uint32_t cntcv1; + rt_uint32_t cntcv2; + rt_uint32_t resv1[4]; + rt_uint32_t cntfid0; + rt_uint32_t cntfid1; + rt_uint32_t cntfid2; + rt_uint32_t resv2[1001]; + rt_uint32_t counterid[1]; }; -#define SC_CNTCR_ENABLE (1 << 0) -#define SC_CNTCR_HDBG (1 << 1) -#define SC_CNTCR_FREQ0 (1 << 8) -#define SC_CNTCR_FREQ1 (1 << 9) +#define SC_CNTCR_ENABLE (1 << 0) +#define SC_CNTCR_HDBG (1 << 1) +#define SC_CNTCR_FREQ0 (1 << 8) +#define SC_CNTCR_FREQ1 (1 << 9) #define isb() __asm__ __volatile__ ("" : : : "memory") @@ -96,79 +96,76 @@ volatile unsigned int *CCM_CLPCR; static void imx6ull_enable_clk_in_waitmode(void) { - CCM_CLPCR = rt_hw_kernel_phys_to_virt((void*)0x20C4054, 4); - *CCM_CLPCR &= ~(1<<5 | 0x3); + CCM_CLPCR = rt_hw_kernel_phys_to_virt((void*)0x20C4054, 4); + *CCM_CLPCR &= ~(1<<5 | 0x3); } static void system_counter_clk_source_init(void) { - /* to do */ + /* to do */ } static void system_counter_init(void) { - /* enable system_counter */ -#define SCTR_BASE_ADDR 0x021DC000 + /* enable system_counter */ +#define SCTR_BASE_ADDR 0x021DC000 #define CONFIG_SC_TIMER_CLK 8000000 - /* imx6ull, enable system counter */ - struct sctr_regs *sctr = (struct sctr_regs *)rt_hw_kernel_phys_to_virt((void*)SCTR_BASE_ADDR, sizeof(struct sctr_regs)); - unsigned long val, freq; + /* imx6ull, enable system counter */ + struct sctr_regs *sctr = (struct sctr_regs *)rt_hw_kernel_phys_to_virt((void*)SCTR_BASE_ADDR, sizeof(struct sctr_regs)); + unsigned long val, freq; - freq = CONFIG_SC_TIMER_CLK; - asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq)); + freq = CONFIG_SC_TIMER_CLK; + asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq)); - sctr->cntfid0 = freq; + sctr->cntfid0 = freq; - /* Enable system counter */ - val = sctr->cntcr; - val &= ~(SC_CNTCR_FREQ0 | SC_CNTCR_FREQ1); - val |= SC_CNTCR_FREQ0 | SC_CNTCR_ENABLE | SC_CNTCR_HDBG; - sctr->cntcr = val; - - imx6ull_enable_clk_in_waitmode(); + /* Enable system counter */ + val = sctr->cntcr; + val &= ~(SC_CNTCR_FREQ0 | SC_CNTCR_FREQ1); + val |= SC_CNTCR_FREQ0 | SC_CNTCR_ENABLE | SC_CNTCR_HDBG; + sctr->cntcr = val; + + imx6ull_enable_clk_in_waitmode(); } static void arch_timer_init(void) { - g_sys_freq = read_cntfrq(); - - /* set timeout val */ - disable_cntp(); - write_cntp_tval(TICK_PERIOD); - - /* start timer */ - enable_cntp(); - - /* enable irq */ - -} + g_sys_freq = read_cntfrq(); + + /* set timeout val */ + disable_cntp(); + write_cntp_tval(TICK_PERIOD); + /* start timer */ + enable_cntp(); + + /* enable irq */ +} static void rt_hw_timer_isr(int vector, void *param) { rt_tick_increase(); - /* setup for next irq */ + /* setup for next irq */ /* clear interrupt */ - disable_cntp(); + disable_cntp(); write_cntp_cval(read_cntp_cval() + TICK_PERIOD); - enable_cntp(); + enable_cntp(); } int rt_hw_timer_init(void) { /* Setup Timer for generating irq */ /* enable timer */ - system_counter_clk_source_init(); - system_counter_init(); - arch_timer_init(); + system_counter_clk_source_init(); + system_counter_init(); + arch_timer_init(); - /* insall irq, enable irq */ + /* insall irq, enable irq */ rt_hw_interrupt_install(IRQ_SYS_TICK, rt_hw_timer_isr, RT_NULL, "tick"); rt_hw_interrupt_umask(IRQ_SYS_TICK); return 0; } INIT_BOARD_EXPORT(rt_hw_timer_init); - diff --git a/bsp/imx6ull-100ask-smart/drivers/drv_timer.h b/bsp/imx6ull-100ask-smart/drivers/drv_timer.h index 718f5d43cf230b973f376b8d646267eed9ac9bcf..c50b073d36c9a0ed9ca72e164b459a5841d1b4b9 100644 --- a/bsp/imx6ull-100ask-smart/drivers/drv_timer.h +++ b/bsp/imx6ull-100ask-smart/drivers/drv_timer.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/imx6ull-100ask-smart/drivers/imx6ul.h b/bsp/imx6ull-100ask-smart/drivers/imx6ul.h index e08da5b224b9596753c15b98a6292562b12b8c9d..799298f56545be6304600f6c4922155a176dd08c 100644 --- a/bsp/imx6ull-100ask-smart/drivers/imx6ul.h +++ b/bsp/imx6ull-100ask-smart/drivers/imx6ul.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/imx6ull-100ask-smart/drivers/rt_lcd.h b/bsp/imx6ull-100ask-smart/drivers/rt_lcd.h index e496a871da38693db597dcc45ac9a181c8d0c55a..c79400888410a2901c45f01d0cd5fd39de3ba408 100644 --- a/bsp/imx6ull-100ask-smart/drivers/rt_lcd.h +++ b/bsp/imx6ull-100ask-smart/drivers/rt_lcd.h @@ -30,7 +30,7 @@ struct fb_bitfield { uint32_t offset; /* beginning of bitfield */ uint32_t length; /* length of bitfield */ - uint32_t msb_right; /* != 0 : Most significant bit is */ + uint32_t msb_right; /* != 0 : Most significant bit is */ /* right */ }; diff --git a/bsp/imx6ull-100ask-smart/drivers/rv.h b/bsp/imx6ull-100ask-smart/drivers/rv.h deleted file mode 100644 index 13e5b6c520003f2e2ae33d05fb0005584cc85c2a..0000000000000000000000000000000000000000 --- a/bsp/imx6ull-100ask-smart/drivers/rv.h +++ /dev/null @@ -1,331 +0,0 @@ -#ifndef __AM33XX_H__ -#define __AM33XX_H__ - -#define __REG32(x) (*((volatile unsigned int *)(x))) -#define __REG16(x) (*((volatile unsigned short *)(x))) - -/* - * Peripheral addresses - */ -#define REALVIEW_UART0_BASE 0x10009000 /* UART 0 */ -#define REALVIEW_UART1_BASE 0x1000A000 /* UART 1 */ -#define REALVIEW_UART2_BASE 0x1000B000 /* UART 2 */ -#define REALVIEW_UART3_BASE 0x1000C000 /* UART 3 */ -#define REALVIEW_SSP_BASE 0x1000D000 /* Synchronous Serial Port */ -#define REALVIEW_WATCHDOG0_BASE 0x1000F000 /* Watchdog 0 */ -#define REALVIEW_WATCHDOG_BASE 0x10010000 /* watchdog interface */ -#define REALVIEW_TIMER0_1_BASE 0x10011000 /* Timer 0 and 1 */ -#define REALVIEW_TIMER2_3_BASE 0x10012000 /* Timer 2 and 3 */ -#define REALVIEW_GPIO0_BASE 0x10013000 /* GPIO port 0 */ -#define REALVIEW_RTC_BASE 0x10017000 /* Real Time Clock */ -#define REALVIEW_TIMER4_5_BASE 0x10018000 /* Timer 4/5 */ -#define REALVIEW_TIMER6_7_BASE 0x10019000 /* Timer 6/7 */ -#define REALVIEW_SCTL_BASE 0x10001000 /* System Controller */ -#define REALVIEW_CLCD_BASE 0x10020000 /* CLCD */ -#define REALVIEW_ONB_SRAM_BASE 0x10060000 /* On-board SRAM */ -#define REALVIEW_DMC_BASE 0x100E0000 /* DMC configuration */ -#define REALVIEW_SMC_BASE 0x100E1000 /* SMC configuration */ -#define REALVIEW_CAN_BASE 0x100E2000 /* CAN bus */ -#define REALVIEW_GIC_CPU_BASE (0x00A00000+0x2000) /* Generic interrupt controller CPU interface */ -#define REALVIEW_FLASH0_BASE 0x40000000 -#define REALVIEW_FLASH0_SIZE SZ_64M -#define REALVIEW_FLASH1_BASE 0x44000000 -#define REALVIEW_FLASH1_SIZE SZ_64M - -#define VEXPRESS_SRAM_BASE 0x48000000 - -#define REALVIEW_ETH_BASE 0x4E000000 /* Ethernet */ -#define VEXPRESS_ETH_BASE 0x4E000000 /* Ethernet */ - -#define REALVIEW_USB_BASE 0x4F000000 /* USB */ -#define REALVIEW_GIC_DIST_BASE (0x00A00000+0x1000) /* Generic interrupt controller distributor */ -#define REALVIEW_LT_BASE 0xC0000000 /* Logic Tile expansion */ -#define REALVIEW_SDRAM6_BASE 0x70000000 /* SDRAM bank 6 256MB */ -#define REALVIEW_SDRAM7_BASE 0x80000000 /* SDRAM bank 7 256MB */ - -#define REALVIEW_SYS_PLD_CTRL1 0x74 - -/* - * PCI regions - */ -#define REALVIEW_PCI_BASE 0x90040000 /* PCI-X Unit base */ -#define REALVIEW_PCI_IO_BASE 0x90050000 /* IO Region on AHB */ -#define REALVIEW_PCI_MEM_BASE 0xA0000000 /* MEM Region on AHB */ - -#define REALVIEW_PCI_BASE_SIZE 0x10000 /* 16 Kb */ -#define REALVIEW_PCI_IO_SIZE 0x1000 /* 4 Kb */ -#define REALVIEW_PCI_MEM_SIZE 0x20000000 /* 512 MB */ - -/* - * Memory definitions - */ -#define REALVIEW_BOOT_ROM_LO 0x30000000 /* DoC Base (64Mb)... */ -#define REALVIEW_BOOT_ROM_HI 0x30000000 -#define REALVIEW_BOOT_ROM_BASE REALVIEW_BOOT_ROM_HI /* Normal position */ -#define REALVIEW_BOOT_ROM_SIZE SZ_64M - -#define REALVIEW_SSRAM_BASE /* REALVIEW_SSMC_BASE ? */ -#define REALVIEW_SSRAM_SIZE SZ_2M - -/* - * SDRAM - */ -#define REALVIEW_SDRAM_BASE 0x00000000 - -/* - * Logic expansion modules - * - */ -#define IRQ_PBA8_GIC_START 32 - -/* - * PB-A8 on-board gic irq sources - */ -#define IRQ_PBA8_WATCHDOG (IRQ_PBA8_GIC_START + 0) /* Watchdog timer */ -#define IRQ_PBA8_SOFT (IRQ_PBA8_GIC_START + 1) /* Software interrupt */ -#define IRQ_PBA8_TIMER0_1 (IRQ_PBA8_GIC_START + 2) /* Timer 0/1 (default timer) */ -#define IRQ_PBA8_TIMER2_3 (IRQ_PBA8_GIC_START + 3) /* Timer 2/3 */ -#define IRQ_PBA8_RTC (IRQ_PBA8_GIC_START + 4) /* Timer 2/3 */ -#define IRQ_VEXPRESS_A9_RTC (IRQ_PBA8_GIC_START + 4) - -#define IRQ_PBA8_UART0 (IRQ_PBA8_GIC_START + 5) /* UART 0 on development chip */ -#define IRQ_PBA8_UART1 (IRQ_PBA8_GIC_START + 6) /* UART 1 on development chip */ -#define IRQ_PBA8_UART2 (IRQ_PBA8_GIC_START + 7) /* UART 2 on development chip */ -#define IRQ_PBA8_UART3 (IRQ_PBA8_GIC_START + 8) /* UART 3 on development chip */ - -#define IRQ_VEXPRESS_A9_KBD (IRQ_PBA8_GIC_START + 12) -#define IRQ_VEXPRESS_A9_MOUSE (IRQ_PBA8_GIC_START + 13) -#define IRQ_VEXPRESS_A9_CLCD (IRQ_PBA8_GIC_START + 14) -#define IRQ_VEXPRESS_A9_ETH (IRQ_PBA8_GIC_START + 15) - -/* 9 reserved */ -#define IRQ_PBA8_SSP (IRQ_PBA8_GIC_START + 11) /* Synchronous Serial Port */ -#define IRQ_PBA8_SCI (IRQ_PBA8_GIC_START + 16) /* Smart Card Interface */ -#define IRQ_PBA8_MMCI0A (IRQ_PBA8_GIC_START + 17) /* Multimedia Card 0A */ -#define IRQ_PBA8_MMCI0B (IRQ_PBA8_GIC_START + 18) /* Multimedia Card 0B */ -#define IRQ_PBA8_AACI (IRQ_PBA8_GIC_START + 19) /* Audio Codec */ -#define IRQ_PBA8_KMI0 (IRQ_PBA8_GIC_START + 20) /* Keyboard/Mouse port 0 */ -#define IRQ_PBA8_KMI1 (IRQ_PBA8_GIC_START + 21) /* Keyboard/Mouse port 1 */ -#define IRQ_PBA8_CHARLCD (IRQ_PBA8_GIC_START + 22) /* Character LCD */ -#define IRQ_PBA8_CLCD (IRQ_PBA8_GIC_START + 23) /* CLCD controller */ -#define IRQ_PBA8_DMAC (IRQ_PBA8_GIC_START + 24) /* DMA controller */ -#define IRQ_PBA8_PWRFAIL (IRQ_PBA8_GIC_START + 25) /* Power failure */ -#define IRQ_PBA8_PISMO (IRQ_PBA8_GIC_START + 26) /* PISMO interface */ -#define IRQ_PBA8_DoC (IRQ_PBA8_GIC_START + 27) /* Disk on Chip memory controller */ -#define IRQ_PBA8_ETH (IRQ_PBA8_GIC_START + 28) /* Ethernet controller */ -#define IRQ_PBA8_USB (IRQ_PBA8_GIC_START + 29) /* USB controller */ -#define IRQ_PBA8_TSPEN (IRQ_PBA8_GIC_START + 30) /* Touchscreen pen */ -#define IRQ_PBA8_TSKPAD (IRQ_PBA8_GIC_START + 31) /* Touchscreen keypad */ - -#define IRQ_PBA8_PMU (IRQ_PBA8_GIC_START + 47) /* Cortex-A8 PMU */ - -/* ... */ -#define IRQ_PBA8_PCI0 (IRQ_PBA8_GIC_START + 50) -#define IRQ_PBA8_PCI1 (IRQ_PBA8_GIC_START + 51) -#define IRQ_PBA8_PCI2 (IRQ_PBA8_GIC_START + 52) -#define IRQ_PBA8_PCI3 (IRQ_PBA8_GIC_START + 53) - -#define IRQ_PBA8_SMC -1 -#define IRQ_PBA8_SCTL -1 - -#define NR_GIC_PBA8 1 - -/* - * Only define NR_IRQS if less than NR_IRQS_PBA8 - */ -#define NR_IRQS_PBA8 (IRQ_PBA8_GIC_START + 64) - -/* ------------------------------------------------------------------------ - * RealView Registers - * ------------------------------------------------------------------------ - * - */ -#define REALVIEW_SYS_ID_OFFSET 0x00 -#define REALVIEW_SYS_SW_OFFSET 0x04 -#define REALVIEW_SYS_LED_OFFSET 0x08 -#define REALVIEW_SYS_OSC0_OFFSET 0x0C - -#define REALVIEW_SYS_OSC1_OFFSET 0x10 -#define REALVIEW_SYS_OSC2_OFFSET 0x14 -#define REALVIEW_SYS_OSC3_OFFSET 0x18 -#define REALVIEW_SYS_OSC4_OFFSET 0x1C /* OSC1 for RealView/AB */ - -#define REALVIEW_SYS_LOCK_OFFSET 0x20 -#define REALVIEW_SYS_100HZ_OFFSET 0x24 -#define REALVIEW_SYS_CFGDATA1_OFFSET 0x28 -#define REALVIEW_SYS_CFGDATA2_OFFSET 0x2C -#define REALVIEW_SYS_FLAGS_OFFSET 0x30 -#define REALVIEW_SYS_FLAGSSET_OFFSET 0x30 -#define REALVIEW_SYS_FLAGSCLR_OFFSET 0x34 -#define REALVIEW_SYS_NVFLAGS_OFFSET 0x38 -#define REALVIEW_SYS_NVFLAGSSET_OFFSET 0x38 -#define REALVIEW_SYS_NVFLAGSCLR_OFFSET 0x3C -#define REALVIEW_SYS_RESETCTL_OFFSET 0x40 -#define REALVIEW_SYS_PCICTL_OFFSET 0x44 -#define REALVIEW_SYS_MCI_OFFSET 0x48 -#define REALVIEW_SYS_FLASH_OFFSET 0x4C -#define REALVIEW_SYS_CLCD_OFFSET 0x50 -#define REALVIEW_SYS_CLCDSER_OFFSET 0x54 -#define REALVIEW_SYS_BOOTCS_OFFSET 0x58 -#define REALVIEW_SYS_24MHz_OFFSET 0x5C -#define REALVIEW_SYS_MISC_OFFSET 0x60 -#define REALVIEW_SYS_IOSEL_OFFSET 0x70 -#define REALVIEW_SYS_PROCID_OFFSET 0x84 -#define REALVIEW_SYS_TEST_OSC0_OFFSET 0xC0 -#define REALVIEW_SYS_TEST_OSC1_OFFSET 0xC4 -#define REALVIEW_SYS_TEST_OSC2_OFFSET 0xC8 -#define REALVIEW_SYS_TEST_OSC3_OFFSET 0xCC -#define REALVIEW_SYS_TEST_OSC4_OFFSET 0xD0 - -#define REALVIEW_SYS_BASE 0x10000000 -#define REALVIEW_SYS_ID (REALVIEW_SYS_BASE + REALVIEW_SYS_ID_OFFSET) -#define REALVIEW_SYS_SW (REALVIEW_SYS_BASE + REALVIEW_SYS_SW_OFFSET) -#define REALVIEW_SYS_LED (REALVIEW_SYS_BASE + REALVIEW_SYS_LED_OFFSET) -#define REALVIEW_SYS_OSC0 (REALVIEW_SYS_BASE + REALVIEW_SYS_OSC0_OFFSET) -#define REALVIEW_SYS_OSC1 (REALVIEW_SYS_BASE + REALVIEW_SYS_OSC1_OFFSET) - -#define REALVIEW_SYS_LOCK (REALVIEW_SYS_BASE + REALVIEW_SYS_LOCK_OFFSET) -#define REALVIEW_SYS_100HZ (REALVIEW_SYS_BASE + REALVIEW_SYS_100HZ_OFFSET) -#define REALVIEW_SYS_CFGDATA1 (REALVIEW_SYS_BASE + REALVIEW_SYS_CFGDATA1_OFFSET) -#define REALVIEW_SYS_CFGDATA2 (REALVIEW_SYS_BASE + REALVIEW_SYS_CFGDATA2_OFFSET) -#define REALVIEW_SYS_FLAGS (REALVIEW_SYS_BASE + REALVIEW_SYS_FLAGS_OFFSET) -#define REALVIEW_SYS_FLAGSSET (REALVIEW_SYS_BASE + REALVIEW_SYS_FLAGSSET_OFFSET) -#define REALVIEW_SYS_FLAGSCLR (REALVIEW_SYS_BASE + REALVIEW_SYS_FLAGSCLR_OFFSET) -#define REALVIEW_SYS_NVFLAGS (REALVIEW_SYS_BASE + REALVIEW_SYS_NVFLAGS_OFFSET) -#define REALVIEW_SYS_NVFLAGSSET (REALVIEW_SYS_BASE + REALVIEW_SYS_NVFLAGSSET_OFFSET) -#define REALVIEW_SYS_NVFLAGSCLR (REALVIEW_SYS_BASE + REALVIEW_SYS_NVFLAGSCLR_OFFSET) -#define REALVIEW_SYS_RESETCTL (REALVIEW_SYS_BASE + REALVIEW_SYS_RESETCTL_OFFSET) -#define REALVIEW_SYS_PCICTL (REALVIEW_SYS_BASE + REALVIEW_SYS_PCICTL_OFFSET) -#define REALVIEW_SYS_MCI (REALVIEW_SYS_BASE + REALVIEW_SYS_MCI_OFFSET) -#define REALVIEW_SYS_FLASH (REALVIEW_SYS_BASE + REALVIEW_SYS_FLASH_OFFSET) -#define REALVIEW_SYS_CLCD (REALVIEW_SYS_BASE + REALVIEW_SYS_CLCD_OFFSET) -#define REALVIEW_SYS_CLCDSER (REALVIEW_SYS_BASE + REALVIEW_SYS_CLCDSER_OFFSET) -#define REALVIEW_SYS_BOOTCS (REALVIEW_SYS_BASE + REALVIEW_SYS_BOOTCS_OFFSET) -#define REALVIEW_SYS_24MHz (REALVIEW_SYS_BASE + REALVIEW_SYS_24MHz_OFFSET) -#define REALVIEW_SYS_MISC (REALVIEW_SYS_BASE + REALVIEW_SYS_MISC_OFFSET) -#define REALVIEW_SYS_IOSEL (REALVIEW_SYS_BASE + REALVIEW_SYS_IOSEL_OFFSET) -#define REALVIEW_SYS_PROCID (REALVIEW_SYS_BASE + REALVIEW_SYS_PROCID_OFFSET) -#define REALVIEW_SYS_TEST_OSC0 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC0_OFFSET) -#define REALVIEW_SYS_TEST_OSC1 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC1_OFFSET) -#define REALVIEW_SYS_TEST_OSC2 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC2_OFFSET) -#define REALVIEW_SYS_TEST_OSC3 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC3_OFFSET) -#define REALVIEW_SYS_TEST_OSC4 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC4_OFFSET) - -#define REALVIEW_SYS_CTRL_LED (1 << 0) - -/* ------------------------------------------------------------------------ - * RealView control registers - * ------------------------------------------------------------------------ - */ - -/* - * REALVIEW_IDFIELD - * - * 31:24 = manufacturer (0x41 = ARM) - * 23:16 = architecture (0x08 = AHB system bus, ASB processor bus) - * 15:12 = FPGA (0x3 = XVC600 or XVC600E) - * 11:4 = build value - * 3:0 = revision number (0x1 = rev B (AHB)) - */ - -/* - * REALVIEW_SYS_LOCK - * control access to SYS_OSCx, SYS_CFGDATAx, SYS_RESETCTL, - * SYS_CLD, SYS_BOOTCS - */ -#define REALVIEW_SYS_LOCK_LOCKED (1 << 16) -#define REALVIEW_SYS_LOCKVAL 0xA05F -#define REALVIEW_SYS_LOCKVAL_MASK 0xFFFF /* write 0xA05F to enable write access */ - -/* - * REALVIEW_SYS_FLASH - */ -#define REALVIEW_FLASHPROG_FLVPPEN (1 << 0) /* Enable writing to flash */ - -/* - * REALVIEW_INTREG - * - used to acknowledge and control MMCI and UART interrupts - */ -#define REALVIEW_INTREG_WPROT 0x00 /* MMC protection status (no interrupt generated) */ -#define REALVIEW_INTREG_RI0 0x01 /* Ring indicator UART0 is asserted, */ -#define REALVIEW_INTREG_CARDIN 0x08 /* MMCI card in detect */ -/* write 1 to acknowledge and clear */ -#define REALVIEW_INTREG_RI1 0x02 /* Ring indicator UART1 is asserted, */ -#define REALVIEW_INTREG_CARDINSERT 0x03 /* Signal insertion of MMC card */ - -/* - * LED settings, bits [7:0] - */ -#define REALVIEW_SYS_LED0 (1 << 0) -#define REALVIEW_SYS_LED1 (1 << 1) -#define REALVIEW_SYS_LED2 (1 << 2) -#define REALVIEW_SYS_LED3 (1 << 3) -#define REALVIEW_SYS_LED4 (1 << 4) -#define REALVIEW_SYS_LED5 (1 << 5) -#define REALVIEW_SYS_LED6 (1 << 6) -#define REALVIEW_SYS_LED7 (1 << 7) - -#define ALL_LEDS 0xFF - -#define LED_BANK REALVIEW_SYS_LED - -/* - * Control registers - */ -#define REALVIEW_IDFIELD_OFFSET 0x0 /* RealView build information */ -#define REALVIEW_FLASHPROG_OFFSET 0x4 /* Flash devices */ -#define REALVIEW_INTREG_OFFSET 0x8 /* Interrupt control */ -#define REALVIEW_DECODE_OFFSET 0xC /* Fitted logic modules */ - -/* - * Clean base - dummy - * - */ -#define CLEAN_BASE REALVIEW_BOOT_ROM_HI - -/* - * System controller bit assignment - */ -#define REALVIEW_REFCLK 0 -#define REALVIEW_TIMCLK 1 - -#define REALVIEW_TIMER1_EnSel 15 -#define REALVIEW_TIMER2_EnSel 17 -#define REALVIEW_TIMER3_EnSel 19 -#define REALVIEW_TIMER4_EnSel 21 - -struct rt_hw_register -{ - unsigned long r0; - unsigned long r1; - unsigned long r2; - unsigned long r3; - unsigned long r4; - unsigned long r5; - unsigned long r6; - unsigned long r7; - unsigned long r8; - unsigned long r9; - unsigned long r10; - unsigned long fp; - unsigned long ip; - unsigned long sp; - unsigned long lr; - unsigned long pc; - unsigned long cpsr; - unsigned long ORIG_r0; -}; - -#include -#include - -/* Interrupt Control Interface */ -#define ARM_GIC_CPU_BASE 0x1E000000 - -/* number of interrupts on board */ -#define ARM_GIC_NR_IRQS 96 -/* only one GIC available */ -#define ARM_GIC_MAX_NR 1 - -#endif - diff --git a/bsp/imx6ull-100ask-smart/drivers/serial.c b/bsp/imx6ull-100ask-smart/drivers/serial.c index 38be488c770cdd6ea6341e0702bf5287e4f89e47..77e626067bae6035c5a4eae89b0eb7f265ec4565 100644 --- a/bsp/imx6ull-100ask-smart/drivers/serial.c +++ b/bsp/imx6ull-100ask-smart/drivers/serial.c @@ -1,26 +1,7 @@ /* - * serial.c UART driver + * Copyright (c) 2006-2021, RT-Thread Development Team * - * COPYRIGHT (C) 2013, Shanghai Real-Thread Technology Co., Ltd - * - * This file is part of RT-Thread (http://www.rt-thread.org) - * Maintainer: bernard.xiong - * - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -36,12 +17,12 @@ /*根据IMX6ULL芯片手册<<55.15 UART Memory Map/Register Definition>>的3608页，定义UART的结构体,*/ typedef struct { - volatile unsigned int URXD; /**< UART Receiver Register, offset: 0x0 串口接收寄存器，偏移地址0x0 */ - unsigned char RESERVED_0[60]; + volatile unsigned int URXD; /**< UART Receiver Register, offset: 0x0 串口接收寄存器，偏移地址0x0 */ + unsigned char RESERVED_0[60]; volatile unsigned int UTXD; /**< UART Transmitter Register, offset: 0x40 串口发送寄存器，偏移地址0x40*/ - unsigned char RESERVED_1[60]; - volatile unsigned int UCR1; /**< UART Control Register 1, offset: 0x80 串口控制寄存器1，偏移地址0x80*/ - volatile unsigned int UCR2; /**< UART Control Register 2, offset: 0x84 串口控制寄存器2，偏移地址0x84*/ + unsigned char RESERVED_1[60]; + volatile unsigned int UCR1; /**< UART Control Register 1, offset: 0x80 串口控制寄存器1，偏移地址0x80*/ + volatile unsigned int UCR2; /**< UART Control Register 2, offset: 0x84 串口控制寄存器2，偏移地址0x84*/ volatile unsigned int UCR3; /**< UART Control Register 3, offset: 0x88 串口控制寄存器3，偏移地址0x88*/ volatile unsigned int UCR4; /**< UART Control Register 4, offset: 0x8C 串口控制寄存器4，偏移地址0x8C*/ volatile unsigned int UFCR; /**< UART FIFO Control Register, offset: 0x90 串口FIFO控制寄存器，偏移地址0x90*/ @@ -50,10 +31,10 @@ volatile unsigned int USR2; /**< UART Status Register 2, offset: volatile unsigned int UESC; /**< UART Escape Character Register, offset: 0x9C 串口转义字符寄存器，偏移地址0x9C*/ volatile unsigned int UTIM; /**< UART Escape Timer Register, offset: 0xA0 串口转义定时器寄存器 偏移地址0xA0*/ volatile unsigned int UBIR; /**< UART BRM Incremental Register, offset: 0xA4 串口二进制倍率增加寄存器 偏移地址0xA4*/ - volatile unsigned int UBMR; /**< UART BRM Modulator Register, offset: 0xA8 串口二进制倍率调节寄存器 偏移地址0xA8*/ + volatile unsigned int UBMR; /**< UART BRM Modulator Register, offset: 0xA8 串口二进制倍率调节寄存器 偏移地址0xA8*/ volatile unsigned int UBRC; /**< UART Baud Rate Count Register, offset: 0xAC 串口波特率计数寄存器 偏移地址0xAC*/ volatile unsigned int ONEMS; /**< UART One Millisecond Register, offset: 0xB0 串口一毫秒寄存器 偏移地址0xB0*/ - volatile unsigned int UTS; /**< UART Test Register, offset: 0xB4 串口测试寄存器 偏移地址0xB4*/ + volatile unsigned int UTS; /**< UART Test Register, offset: 0xB4 串口测试寄存器 偏移地址0xB4*/ volatile unsigned int UMCR; /**< UART RS-485 Mode Control Register, offset: 0xB8 串口485模式控制寄存器 偏移地址0xB8*/ } UART_Type; @@ -87,61 +68,61 @@ static void rt_hw_uart_isr(int irqno, void *param) static rt_err_t uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg) { - /* 115200,8n1 */ - volatile unsigned int *IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA ; - volatile unsigned int *IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA ; - volatile unsigned int *IOMUXC_UART1_RX_DATA_SELECT_INPUT ; - volatile unsigned int *CCM_CSCDR1; - volatile unsigned int *CCM_CCGR5; - - IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA = (volatile unsigned int *)rt_hw_kernel_phys_to_virt((void *)0x20E0084, 4); - IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA = (volatile unsigned int *)rt_hw_kernel_phys_to_virt((void *)0x20E0088, 4); - IOMUXC_UART1_RX_DATA_SELECT_INPUT = (volatile unsigned int *)rt_hw_kernel_phys_to_virt((void *)0x20E0624, 4); - CCM_CSCDR1 = (volatile unsigned int *)rt_hw_kernel_phys_to_virt((void *)0x020C4024, 4); - CCM_CCGR5 = (volatile unsigned int *)rt_hw_kernel_phys_to_virt((void *)0x020C407C, 4); + /* 115200,8n1 */ + volatile unsigned int *IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA ; + volatile unsigned int *IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA ; + volatile unsigned int *IOMUXC_UART1_RX_DATA_SELECT_INPUT ; + volatile unsigned int *CCM_CSCDR1; + volatile unsigned int *CCM_CCGR5; + + IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA = (volatile unsigned int *)rt_hw_kernel_phys_to_virt((void *)0x20E0084, 4); + IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA = (volatile unsigned int *)rt_hw_kernel_phys_to_virt((void *)0x20E0088, 4); + IOMUXC_UART1_RX_DATA_SELECT_INPUT = (volatile unsigned int *)rt_hw_kernel_phys_to_virt((void *)0x20E0624, 4); + CCM_CSCDR1 = (volatile unsigned int *)rt_hw_kernel_phys_to_virt((void *)0x020C4024, 4); + CCM_CCGR5 = (volatile unsigned int *)rt_hw_kernel_phys_to_virt((void *)0x020C407C, 4); struct hw_uart_device * uart = (struct hw_uart_device *)serial->parent.user_data; - UART_Type *uart_reg = (UART_Type *)uart->hw_base; + UART_Type *uart_reg = (UART_Type *)uart->hw_base; - /* 设置UART的总时钟 - * UART_CLK_ROOT = 80Mhz - */ - *CCM_CSCDR1 &= ~((1<<6) | (0x3f)); + /* 设置UART的总时钟 + * UART_CLK_ROOT = 80Mhz + */ + *CCM_CSCDR1 &= ~((1<<6) | (0x3f)); - /* 给UART1模块提供时钟 - * uart1_clk_enable - */ - *CCM_CCGR5 |= (3<<24); + /* 给UART1模块提供时钟 + * uart1_clk_enable + */ + *CCM_CCGR5 |= (3<<24); - /* 配置引脚功能 */ - *IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA &= ~0xf; - *IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA &= ~0xf; + /* 配置引脚功能 */ + *IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA &= ~0xf; + *IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA &= ~0xf; - /* IMX6ULL特殊的地方 */ - *IOMUXC_UART1_RX_DATA_SELECT_INPUT |= 3; + /* IMX6ULL特殊的地方 */ + *IOMUXC_UART1_RX_DATA_SELECT_INPUT |= 3; - /* 设置波特率 - * 115200 = 80M/(16*(UBMR+1)/(UBIR+1)) - * UBIR = 15 - * 115200 = 80M/(UBMR+1) - * UBMR = 80,000,000/115200 = 694 - 1 = 693 - * 真正的baudrate = 80,000,000/694 = 115274 - * 先设置UBIR, 后设置UBMR - */ - uart_reg->UFCR |= (5<<7); - uart_reg->UBIR = 15; - uart_reg->UBMR = 693; + /* 设置波特率 + * 115200 = 80M/(16*(UBMR+1)/(UBIR+1)) + * UBIR = 15 + * 115200 = 80M/(UBMR+1) + * UBMR = 80,000,000/115200 = 694 - 1 = 693 + * 真正的baudrate = 80,000,000/694 = 115274 + * 先设置UBIR, 后设置UBMR + */ + uart_reg->UFCR |= (5<<7); + uart_reg->UBIR = 15; + uart_reg->UBMR = 693; - /* 设置数据格式 */ - uart_reg->UCR2 |= (1<<14) | (0<<8) | (0<<6) | (1<<5) | (1<<2) | (1<<1); + /* 设置数据格式 */ + uart_reg->UCR2 |= (1<<14) | (0<<8) | (0<<6) | (1<<5) | (1<<2) | (1<<1); - /* IMX6ULL芯片要求必须设置 */ - uart_reg->UCR3 |= (1<<2); + /* IMX6ULL芯片要求必须设置 */ + uart_reg->UCR3 |= (1<<2); - /* 使能UART */ - uart_reg->UCR1 |= (1<<0); + /* 使能UART */ + uart_reg->UCR1 |= (1<<0); return RT_EOK; } @@ -149,11 +130,11 @@ static rt_err_t uart_configure(struct rt_serial_device *serial, struct serial_co static rt_err_t uart_control(struct rt_serial_device *serial, int cmd, void *arg) { struct hw_uart_device *uart; - UART_Type *uart_reg; + UART_Type *uart_reg; RT_ASSERT(serial != RT_NULL); uart = (struct hw_uart_device *)serial->parent.user_data; - uart_reg = (UART_Type *)uart->hw_base; + uart_reg = (UART_Type *)uart->hw_base; switch (cmd) { @@ -164,7 +145,7 @@ static rt_err_t uart_control(struct rt_serial_device *serial, int cmd, void *arg case RT_DEVICE_CTRL_SET_INT: /* enable rx irq */ - uart_reg->UCR4 |= (1<<0); + uart_reg->UCR4 |= (1<<0); rt_hw_interrupt_umask(uart->irqno); break; } @@ -175,14 +156,14 @@ static rt_err_t uart_control(struct rt_serial_device *serial, int cmd, void *arg static int uart_putc(struct rt_serial_device *serial, char c) { struct hw_uart_device *uart; - UART_Type *uart_reg; + UART_Type *uart_reg; RT_ASSERT(serial != RT_NULL); uart = (struct hw_uart_device *)serial->parent.user_data; - uart_reg = (UART_Type *)uart->hw_base; + uart_reg = (UART_Type *)uart->hw_base; - while ((uart_reg->USR2 & (1<<3)) == 0); - uart_reg->UTXD = c; + while ((uart_reg->USR2 & (1<<3)) == 0); + uart_reg->UTXD = c; return 1; } @@ -191,16 +172,16 @@ static int uart_getc(struct rt_serial_device *serial) { int ch; struct hw_uart_device *uart; - UART_Type *uart_reg; + UART_Type *uart_reg; RT_ASSERT(serial != RT_NULL); uart = (struct hw_uart_device *)serial->parent.user_data; - uart_reg = (UART_Type *)uart->hw_base; + uart_reg = (UART_Type *)uart->hw_base; - if ((uart_reg->USR2 & (1<<0)) == 0) - ch = -1; - else - ch = uart_reg->URXD; + if ((uart_reg->USR2 & (1<<0)) == 0) + ch = -1; + else + ch = uart_reg->URXD; return ch; } diff --git a/bsp/imx6ull-100ask-smart/drivers/serial.h b/bsp/imx6ull-100ask-smart/drivers/serial.h index 52e6f07ea399abdcc21a3d21b334db69fe77dddc..3d870466c19eb95a4990aff7e9aef8e6a0e3f730 100644 --- a/bsp/imx6ull-100ask-smart/drivers/serial.h +++ b/bsp/imx6ull-100ask-smart/drivers/serial.h @@ -1,26 +1,7 @@ /* - * UART driver + * Copyright (c) 2006-2021, RT-Thread Development Team * - * COPYRIGHT (C) 2013, Shanghai Real-Thread Technology Co., Ltd - * - * This file is part of RT-Thread (http://www.rt-thread.org) - * Maintainer: bernard.xiong - * - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -35,5 +16,3 @@ int rt_hw_uart_init(void); #endif - - diff --git a/bsp/imx6ull-100ask-smart/drivers/vexpress_a9.h b/bsp/imx6ull-100ask-smart/drivers/vexpress_a9.h deleted file mode 100644 index a6467973c5a13c248a088cbb0fad72e640a2b48e..0000000000000000000000000000000000000000 --- a/bsp/imx6ull-100ask-smart/drivers/vexpress_a9.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * Copyright (c) 2006-2018, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2018-03-22 quanzhao first version - */ - -#ifndef __VEXPRESS_A9_H__ -#define __VEXPRESS_A9_H__ - -/* for 'rt_inline' */ -#include -/* SOC-relative definitions */ -#include "realview.h" - -/* the maximum entries of the exception table */ -#define MAX_HANDLERS NR_IRQS_PBA8 - -/* the basic constants and interfaces needed by gic */ -rt_inline rt_uint32_t platform_get_gic_dist_base(void) -{ - return REALVIEW_GIC_DIST_BASE; -} - -rt_inline rt_uint32_t platform_get_gic_cpu_base(void) -{ - return REALVIEW_GIC_CPU_BASE; -} - -#define GIC_IRQ_START 0 - -#define GIC_ACK_INTID_MASK 0x000003ff - -#endif /* __VEXPRESS_A9_H__ */ diff --git a/libcpu/arm/common/backtrace.c b/libcpu/arm/common/backtrace.c deleted file mode 100644 index 4fc87b20d14642c3c64ff6c74f8b381cf6eaa310..0000000000000000000000000000000000000000 --- a/libcpu/arm/common/backtrace.c +++ /dev/null @@ -1,63 +0,0 @@ -/* - * Copyright (c) 2006-2018, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2008-07-29 Bernard first version from QiuYi implementation - */ - -#include - -#ifdef __GNUC__ -/* --->High Address,Stack Top -PC<------| -LR | -IP | -FP | -...... | -PC <-| | -LR | | -IP | | -FP---|-- | -...... | -PC | -LR | -IP | -FP--- --->Low Address,Stack Bottom -*/ -void rt_hw_backtrace(rt_uint32_t *fp, rt_uint32_t thread_entry) -{ - rt_uint32_t i, pc, func_entry; - - pc = *fp; - rt_kprintf("[0x%x]\n", pc-0xC); - - for(i=0; i<10; i++) - { - fp = (rt_uint32_t *)*(fp - 3); - pc = *fp ; - - func_entry = pc - 0xC; - - if(func_entry <= 0x30000000) break; - - if(func_entry == thread_entry) - { - rt_kprintf("EntryPoint:0x%x\n", func_entry); - - break; - } - - rt_kprintf("[0x%x]\n", func_entry); - } -} -#else -void rt_hw_backtrace(rt_uint32_t *fp, rt_uint32_t thread_entry) -{ - /* old compiler implementation */ -} -#endif diff --git a/libcpu/arm/common/showmem.c b/libcpu/arm/common/showmem.c deleted file mode 100644 index b770e4ce173172419e2cf7b24e73953d647cbdf0..0000000000000000000000000000000000000000 --- a/libcpu/arm/common/showmem.c +++ /dev/null @@ -1,38 +0,0 @@ -/* - * Copyright (c) 2006-2018, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2008-07-29 Bernard first version from QiuYi implementation - */ - -#include - -void rt_hw_show_memory(rt_uint32_t addr, rt_uint32_t size) -{ - int i = 0, j =0; - - RT_ASSERT(addr); - - addr = addr & ~0xF; - size = 4*((size + 3)/4); - - while(i < size) - { - rt_kprintf("0x%08x: ", addr ); - - for(j=0; j<4; j++) - { - rt_kprintf("0x%08x ", *(rt_uint32_t *)addr); - - addr += 4; - i++; - } - - rt_kprintf("\n"); - } - - return; -}