diff --git a/bsp/stm32f10x/drivers/bxcan.c b/bsp/stm32f10x/drivers/bxcan.c
index a21f9f1c4d0d643ca67dff40a72ebd665806e819..8c9b39ecf09a94d93fe253e2ec8dc2f10c11b2e5 100644
--- a/bsp/stm32f10x/drivers/bxcan.c
+++ b/bsp/stm32f10x/drivers/bxcan.c
@@ -262,8 +262,6 @@ static void bxcan1_hw_init(void)
       GPIO_InitTypeDef  GPIO_InitStructure;
       NVIC_InitTypeDef  NVIC_InitStructure;    
 
-      RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO | RCC_APB2Periph_GPIOA, ENABLE);
-         
       GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11;
       GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
       GPIO_Init(GPIOA, &GPIO_InitStructure);
@@ -273,9 +271,6 @@ static void bxcan1_hw_init(void)
       GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
       GPIO_Init(GPIOA, &GPIO_InitStructure);
     
-      RCC_APB1PeriphClockCmd(RCC_APB1Periph_CAN1 , ENABLE);  
-      
-      CAN_DeInit(CAN1);
       NVIC_PriorityGroupConfig(NVIC_PriorityGroup_1);
       NVIC_InitStructure.NVIC_IRQChannel = CAN1_RX0_IRQn;
       NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x1;
@@ -292,8 +287,6 @@ static void bxcan2_hw_init(void)
       GPIO_InitTypeDef  GPIO_InitStructure;
       NVIC_InitTypeDef  NVIC_InitStructure;    
 
-      RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO | RCC_APB2Periph_GPIOB, ENABLE);
-
       GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;      
       GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12;
       GPIO_Init(GPIOB, &GPIO_InitStructure);
@@ -302,10 +295,6 @@ static void bxcan2_hw_init(void)
       GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
       GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
       GPIO_Init(GPIOB, &GPIO_InitStructure);
-    
-      RCC_APB1PeriphClockCmd(RCC_APB1Periph_CAN2, ENABLE);  
-      
-      CAN_DeInit(CAN2);
 
       NVIC_PriorityGroupConfig(NVIC_PriorityGroup_1);
       NVIC_InitStructure.NVIC_IRQChannel = CAN2_RX0_IRQn;
@@ -1371,6 +1360,9 @@ int stm32_bxcan_init(void)
 {
 
 #ifdef USING_BXCAN1
+      RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO | RCC_APB2Periph_GPIOA, ENABLE);
+      RCC_APB1PeriphClockCmd(RCC_APB1Periph_CAN1 , ENABLE);  
+      CAN_DeInit(CAN1);
       bxcan1.config.baud_rate=CAN1MBaud;
       bxcan1.config.msgboxsz=16;
       bxcan1.config.sndboxnumber=3;
@@ -1389,6 +1381,12 @@ int stm32_bxcan_init(void)
 #endif
 
 #ifdef USING_BXCAN2
+      RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO | RCC_APB2Periph_GPIOB, ENABLE);
+#ifndef USING_BXCAN1
+      RCC_APB1PeriphClockCmd(RCC_APB1Periph_CAN1 , ENABLE); 
+#endif
+      RCC_APB1PeriphClockCmd(RCC_APB1Periph_CAN2, ENABLE);  
+      CAN_DeInit(CAN2);
       bxcan2.config.baud_rate=CAN1MBaud;
       bxcan2.config.msgboxsz=16;
       bxcan2.config.sndboxnumber=3;
diff --git a/libcpu/arm/arm926/start_gcc.S b/libcpu/arm/arm926/start_gcc.S
index aeeb37616b434439c837e96588c21c866ed2378b..4924583cb88535d7f7a09a6fc031c1e17a0c94f1 100644
--- a/libcpu/arm/arm926/start_gcc.S
+++ b/libcpu/arm/arm926/start_gcc.S
@@ -22,6 +22,7 @@
  * 2011-01-13     weety      first version
  * 2015-04-15     ArdaFu     Split from AT91SAM9260 BSP
  * 2015-04-21     ArdaFu     Remove remap code. Using mmu to map vector table
+ * 2015-06-04     aozima     Align stack address to 8 byte.
  */
  
 #define S_FRAME_SIZE    (18*4)   //72
@@ -61,31 +62,32 @@
     .section .nobss, "w"
 
     .space UND_STK_SIZE
+    .align 3
     .global UND_STACK_START
 UND_STACK_START:
 
     .space ABT_STK_SIZE
-    .align 2
+    .align 3
     .global ABT_STACK_START
 ABT_STACK_START:
 
     .space FIQ_STK_SIZE
-    .align 2
+    .align 3
     .global FIQ_STACK_START
 FIQ_STACK_START:
 
     .space IRQ_STK_SIZE
-    .align 2
+    .align 3
     .global IRQ_STACK_START
 IRQ_STACK_START:
 
     .skip SYS_STK_SIZE
-    .align 2
+    .align 3
     .global SYS_STACK_START
 SYS_STACK_START:
 
     .space SVC_STK_SIZE
-    .align 2
+    .align 3
     .global SVC_STACK_START
 SVC_STACK_START:
 
diff --git a/libcpu/arm/arm926/start_iar.S b/libcpu/arm/arm926/start_iar.S
index 4e689236a5b43b0c3a26c0594be323d0add11acf..3494b108d7b98654600ab88032b129778e356057 100644
--- a/libcpu/arm/arm926/start_iar.S
+++ b/libcpu/arm/arm926/start_iar.S
@@ -22,6 +22,7 @@
 ; * 2011-01-13     weety      first version
 ; * 2015-04-15     ArdaFu     Split from AT91SAM9260 BSP
 ; * 2015-04-21     ArdaFu     Remove remap code. Using mmu to map vector table
+; * 2015-06-04     aozima     Align stack address to 8 byte.
 ; */
  
 #define S_FRAME_SIZE    (18*4)   ;72
@@ -62,31 +63,32 @@
     SECTION .noinit:DATA:NOROOT(3)
     DATA
 
+    ALIGNRAM 3
     DS8 UND_STK_SIZE
     PUBLIC UND_STACK_START
 UND_STACK_START:
 
-    ALIGNRAM 2
+    ALIGNRAM 3
     DS8 ABT_STK_SIZE
     PUBLIC ABT_STACK_START
 ABT_STACK_START:
 
-    ALIGNRAM 2
+    ALIGNRAM 3
     DS8 FIQ_STK_SIZE
     PUBLIC FIQ_STACK_START
 FIQ_STACK_START:
 
-    ALIGNRAM 2
+    ALIGNRAM 3
     DS8 IRQ_STK_SIZE
     PUBLIC IRQ_STACK_START
 IRQ_STACK_START:
 
-    ALIGNRAM 2
+    ALIGNRAM 3
     DS8 SYS_STK_SIZE
     PUBLIC SYS_STACK_START
 SYS_STACK_START:
 
-    ALIGNRAM 2
+    ALIGNRAM 3
     DS8 SVC_STK_SIZE
     PUBLIC SVC_STACK_START
 SVC_STACK_START:
diff --git a/libcpu/arm/arm926/start_rvds.S b/libcpu/arm/arm926/start_rvds.S
index e086e394f1134a8bccf8260f606396a06dfbfc82..1c1e48c07ed7c8c392932c687b8be70cc241c244 100644
--- a/libcpu/arm/arm926/start_rvds.S
+++ b/libcpu/arm/arm926/start_rvds.S
@@ -22,6 +22,7 @@
 ; * 2011-08-14     weety      first version
 ; * 2015-04-15     ArdaFu     Split from AT91SAM9260 BSP
 ; * 2015-04-21     ArdaFu     Remove remap code. Using mmu to map vector table
+; * 2015-06-04     aozima     Align stack address to 8 byte.
 ; */
 
 S_FRAME_SIZE    EQU     (18*4)   ;72
@@ -60,38 +61,44 @@ NOINT           EQU     0xC0
     GET rt_low_level_keil.inc
     
 ;----------------------- Stack and Heap Definitions ----------------------------
-    AREA    STACK, NOINIT, READWRITE, ALIGN=2
+    AREA    STACK, NOINIT, READWRITE, ALIGN=3
 Stack_Mem
 
     SPACE   UND_STK_SIZE
     EXPORT UND_STACK_START
 UND_STACK_START
 
-    ALIGN 4
+    ALIGN 8
     SPACE   ABT_STK_SIZE
     EXPORT ABT_STACK_START
 ABT_STACK_START
 
-    ALIGN 4
+    ALIGN 8
     SPACE   FIQ_STK_SIZE
     EXPORT FIQ_STACK_START
 FIQ_STACK_START
 
-    ALIGN 4
+    ALIGN 8
     SPACE   IRQ_STK_SIZE
     EXPORT IRQ_STACK_START
 IRQ_STACK_START
 
-    ALIGN 4
+    ALIGN 8
     SPACE   SYS_STK_SIZE
     EXPORT SYS_STACK_START
 SYS_STACK_START
 
-    ALIGN 4
+    ALIGN 8
     SPACE   SVC_STK_SIZE
     EXPORT SVC_STACK_START
 SVC_STACK_START
 Stack_Top
+__initial_sp
+
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
     PRESERVE8
 ;--------------Jump vector table------------------------------------------------
     EXPORT Entry_Point
@@ -291,4 +298,31 @@ rt_hw_context_switch_interrupt_do PROC
 
     LDMFD   SP!, {R0-R12,LR,PC}^    ; pop new task's R0-R12,LR & PC SPSR to CPSR
     ENDP
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+                
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+                
+                 ELSE
+                
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+                 
+__user_initial_stackheap
+
+                 LDR     R0, = Heap_Mem                         ; heap base
+                 LDR     R1, = SVC_STACK_START                  ; stack base (top-address)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)          ; heap limit
+                 LDR     R3, = (SVC_STACK_START - SVC_STK_SIZE) ; stack limit (low-address)
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
     END