diff --git a/libcpu/arm/s3c24x0/mmu.c b/libcpu/arm/s3c24x0/mmu.c
index 9ef6bd5075ea22f0629871c9e3c08b37d9986d35..dfe3328b60aafd1062862b3a5ad9f6672cdf29a4 100644
--- a/libcpu/arm/s3c24x0/mmu.c
+++ b/libcpu/arm/s3c24x0/mmu.c
@@ -173,87 +173,147 @@ void mmu_invalidate_icache()
 #endif
 
 #ifdef __CC_ARM
-__asm void mmu_setttbase(rt_uint32_t i)
+void mmu_setttbase(rt_uint32_t i)
 {
-	mcr p15, 0, r0, c2, c2, 0
+    __asm
+    {
+        mcr p15, 0, i, c2, c2, 0
+    }
 }
 
-__asm void mmu_set_domain(rt_uint32_t i)
+void mmu_set_domain(rt_uint32_t i)
 {
-	mcr p15,0, r0, c3, c0,  0
+    __asm
+    {
+        mcr p15,0, i, c3, c0,  0
+    }
 }
 
-__asm void mmu_enable()
+void mmu_enable()
 {
-	mrc p15, 0, r0, c1, c0, 0
-	orr r0, r0, #0x01
-	mcr p15, 0, r0, c1, c0, 0
+    register rt_uint32_t value;
+
+    __asm
+    {
+        mrc p15, 0, value, c1, c0, 0
+        orr value, value, #0x01
+        mcr p15, 0, value, c1, c0, 0
+    }
 }
 
-__asm void mmu_disable()
+void mmu_disable()
 {
-	mrc p15, 0, r0, c1, c0, 0
-	bic r0, r0, #0x01
-	mcr p15, 0, r0, c1, c0, 0
+    register rt_uint32_t value;
+
+    __asm
+    {
+        mrc p15, 0, value, c1, c0, 0
+        bic value, value, #0x01
+        mcr p15, 0, value, c1, c0, 0
+    }
 }
 
-__asm void mmu_enable_icache()
+void mmu_enable_icache()
 {
-	mrc p15, 0, r0, c1, c0, 0
-	orr r0, r0, #0x1000
-	mcr p15, 0, r0, c1, c0, 0
+    register rt_uint32_t value;
+
+    __asm
+    {
+        mrc p15, 0, value, c1, c0, 0
+        orr value, value, #0x1000
+        mcr p15, 0, value, c1, c0, 0
+    }
 }
 
-__asm void mmu_enable_dcache()
+void mmu_enable_dcache()
 {
-	mrc p15, 0, r0, c1, c0, 0
-	orr r0, r0, #0x04
-	mcr p15, 0, r0, c1, c0, 0
+    register rt_uint32_t value;
+
+    __asm
+    {
+        mrc p15, 0, value, c1, c0, 0
+        orr value, value, #0x04
+        mcr p15, 0, value, c1, c0, 0
+    }
 }
 
-__asm void mmu_disable_icache()
+void mmu_disable_icache()
 {
-	mrc p15, 0, r0, c1, c0, 0
-	bic r0, r0, #0x1000
-	mcr p15, 0, r0, c1, c0, 0
+    register rt_uint32_t value;
+
+    __asm
+    {
+        mrc p15, 0, value, c1, c0, 0
+        bic value, value, #0x1000
+        mcr p15, 0, value, c1, c0, 0
+    }
 }
 
-__asm void mmu_disable_dcache()
+void mmu_disable_dcache()
 {
-	mrc p15, 0, r0, c1, c0, 0
-	bic r0, r0, #0x04
-	mcr p15, 0, r0, c1, c0, 0
+    register rt_uint32_t value;
+
+    __asm
+    {
+        mrc p15, 0, value, c1, c0, 0
+        bic value, value, #0x04
+        mcr p15, 0, value, c1, c0, 0
+    }
 }
 
-__asm void mmu_enable_alignfault()
+void mmu_enable_alignfault()
 {
-	mrc p15, 0, r0, c1, c0, 0
-	orr r0, r0, #0x02
-	mcr p15, 0, r0, c1, c0, 0
+    register rt_uint32_t value;
+
+    __asm
+    {
+        mrc p15, 0, value, c1, c0, 0
+        orr value, value, #0x02
+        mcr p15, 0, value, c1, c0, 0
+    }
 }
 
-__asm void mmu_disable_alignfault()
+void mmu_disable_alignfault()
 {
-	mrc p15, 0, r0, c1, c0, 0
-	bic r0, r0, #0x02
-	mcr p15, 0, r0, c1, c0, 0
+    register rt_uint32_t value;
+
+    __asm
+    {
+        mrc p15, 0, value, c1, c0, 0
+        bic value, value, #0x02
+        mcr p15, 0, value, c1, c0, 0
+    }
 }
 
-__asm void mmu_clean_invalidated_cache_index(int index)
+void mmu_clean_invalidated_cache_index(int index)
 {
-	mcr p15, 0, r0, c7, c14, 2
+    __asm
+    {
+        mcr p15, 0, index, c7, c14, 2
+    }
 }
 
-__asm void mmu_invalidate_tlb()
+void mmu_invalidate_tlb()
 {
-	mov r0, #0x0
-	mcr p15, 0, r0, c8, c7, 0
+    register rt_uint32_t value;
+
+    value = 0;
+    __asm
+    {
+        mcr p15, 0, value, c8, c7, 0
+    }
 }
 
-__asm void mmu_invalidate_icache()
+void mmu_invalidate_icache()
 {
-	mov r0, #0
-	mcr p15, 0, r0, c7, c5, 0
+    register rt_uint32_t value;
+
+    value = 0;
+
+    __asm
+    {
+        mcr p15, 0, value, c7, c5, 0
+    }
 }
 #endif
 
@@ -323,12 +383,12 @@ void rt_hw_mmu_init(void)
 	/* DOMAIN1: no_access, DOMAIN0,2~15=client(AP is checked) */
 	mmu_set_domain(0x55555550|DOMAIN1_ATTR|DOMAIN0_ATTR);
 
-	//mmu_SetProcessId(0x0);
 	mmu_enable_alignfault();
 
 	mmu_enable();
-	mmu_enable_icache();
 
+	/* ICache enable */
+	mmu_enable_icache();
 	/* DCache should be turned on after mmu is turned on. */
 	mmu_enable_dcache();
 }
diff --git a/libcpu/arm/s3c24x0/start_rvds.s b/libcpu/arm/s3c24x0/start_rvds.s
index 5dc5d8aefef2cc1ef1b6b033f3e780cf79d1757b..8cb7eea31575efbd857e5e29dd8ecfa4cd3dcb8a 100644
--- a/libcpu/arm/s3c24x0/start_rvds.s
+++ b/libcpu/arm/s3c24x0/start_rvds.s
@@ -1061,7 +1061,7 @@ Reset_Handler
                 SUB     R0, R0, #SVC_Stack_Size
 
 ;  Enter User Mode and set its Stack Pointer
-                MSR     CPSR_c, #Mode_USR
+                ; MSR     CPSR_c, #Mode_USR
                 MOV     SP, R0
                 SUB     SL, SP, #USR_Stack_Size