diff --git a/bsp/imx6ull-100ask-smart/.config b/bsp/imx6ull-100ask-smart/.config new file mode 100644 index 0000000000000000000000000000000000000000..b2eea34b15f1d1748183415b4255674e10670d6f --- /dev/null +++ b/bsp/imx6ull-100ask-smart/.config @@ -0,0 +1,640 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Project Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +CONFIG_RT_USING_SMART=y +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_ALIGN_SIZE=4 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=100 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=1024 +CONFIG_RT_USING_TIMER_SOFT=y +CONFIG_RT_TIMER_THREAD_PRIO=4 +CONFIG_RT_TIMER_THREAD_STACK_SIZE=1024 +CONFIG_RT_DEBUG=y +CONFIG_RT_DEBUG_COLOR=y +# CONFIG_RT_DEBUG_INIT_CONFIG is not set +# CONFIG_RT_DEBUG_THREAD_CONFIG is not set +# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set +# CONFIG_RT_DEBUG_IPC_CONFIG is not set +# CONFIG_RT_DEBUG_TIMER_CONFIG is not set +# CONFIG_RT_DEBUG_IRQ_CONFIG is not set +# CONFIG_RT_DEBUG_MEM_CONFIG is not set +# CONFIG_RT_DEBUG_SLAB_CONFIG is not set +# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set +# CONFIG_RT_DEBUG_MODULE_CONFIG is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +CONFIG_RT_USING_SIGNALS=y + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +CONFIG_RT_USING_MEMHEAP=y +# CONFIG_RT_USING_NOHEAP is not set +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set +CONFIG_RT_USING_MEMTRACE=y +CONFIG_RT_USING_HEAP=y + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +CONFIG_RT_USING_DEVICE_OPS=y +CONFIG_RT_USING_INTERRUPT_INFO=y +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=256 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" +CONFIG_RT_VER_NUM=0x40003 +CONFIG_RT_USING_CACHE=y +# CONFIG_RT_USING_CPU_FFS is not set +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set +CONFIG_ARCH_ARM=y +CONFIG_ARCH_ARM_MMU=y +CONFIG_RT_USING_USERSPACE=y +CONFIG_KERNEL_VADDR_START=0xc0000000 +CONFIG_PV_OFFSET=0xc0000000 +# CONFIG_RT_IOREMAP_LATE is not set +CONFIG_ARCH_ARM_CORTEX_A=y +CONFIG_ARCH_ARM_CORTEX_A7=y +CONFIG_RT_BACKTRACE_FUNCTION_NAME=y + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 + +# +# C++ features +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Command shell +# +CONFIG_RT_USING_FINSH=y +CONFIG_RT_USING_MSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_CMD_SIZE=80 +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_ARG_MAX=10 + +# +# Device virtual file system +# +CONFIG_RT_USING_DFS=y +CONFIG_DFS_USING_WORKDIR=y +CONFIG_DFS_FILESYSTEMS_MAX=4 +CONFIG_DFS_FILESYSTEM_TYPES_MAX=8 +CONFIG_DFS_FD_MAX=16 +# CONFIG_RT_USING_DFS_MNTTABLE is not set +# CONFIG_RT_USING_DFS_ELMFAT is not set +CONFIG_RT_USING_DFS_DEVFS=y +CONFIG_RT_USING_DFS_ROMFS=y +# CONFIG_RT_USING_DFS_CROMFS is not set +# CONFIG_RT_USING_DFS_RAMFS is not set +# CONFIG_RT_USING_DFS_UFFS is not set +# CONFIG_RT_USING_DFS_JFFS2 is not set +# CONFIG_RT_USING_DFS_NFS is not set + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_PIPE_BUFSZ=512 +CONFIG_RT_USING_SYSTEM_WORKQUEUE=y +CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=2048 +CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23 +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_SERIAL_USING_DMA=y +CONFIG_RT_SERIAL_RB_BUFSZ=64 +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CPUTIME is not set +CONFIG_RT_USING_I2C=y +# CONFIG_RT_I2C_DEBUG is not set +CONFIG_RT_USING_I2C_BITOPS=y +# CONFIG_RT_I2C_BITOPS_DEBUG is not set +# CONFIG_RT_USING_PHY is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_NULL is not set +# CONFIG_RT_USING_ZERO is not set +# CONFIG_RT_USING_RANDOM is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +CONFIG_RT_USING_RTC=y +# CONFIG_RT_USING_ALARM is not set +CONFIG_RT_USING_SOFT_RTC=y +CONFIG_RT_USING_SDIO=y +CONFIG_RT_SDIO_STACK_SIZE=512 +CONFIG_RT_SDIO_THREAD_PRIORITY=15 +CONFIG_RT_MMCSD_STACK_SIZE=1024 +CONFIG_RT_MMCSD_THREAD_PREORITY=22 +CONFIG_RT_MMCSD_MAX_PARTITION=16 +# CONFIG_RT_SDIO_DEBUG is not set +CONFIG_RT_USING_SPI=y +# CONFIG_RT_USING_QSPI is not set +CONFIG_RT_USING_SPI_MSD=y +CONFIG_RT_USING_SFUD=y +CONFIG_RT_SFUD_USING_SFDP=y +CONFIG_RT_SFUD_USING_FLASH_INFO_TABLE=y +# CONFIG_RT_SFUD_USING_QSPI is not set +CONFIG_RT_SFUD_SPI_MAX_HZ=50000000 +# CONFIG_RT_DEBUG_SFUD is not set +# CONFIG_RT_USING_ENC28J60 is not set +# CONFIG_RT_USING_SPI_WIFI is not set +CONFIG_RT_USING_WDT=y +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_WIFI is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# POSIX layer and C standard library +# +CONFIG_RT_USING_LIBC=y +# CONFIG_RT_USING_NEWLIB is not set +CONFIG_RT_USING_MUSL=y +# CONFIG_RT_USING_PTHREADS is not set +CONFIG_RT_USING_POSIX=y +CONFIG_RT_USING_POSIX_MMAP=y +CONFIG_RT_USING_POSIX_TERMIOS=y +# CONFIG_RT_USING_POSIX_GETLINE is not set +CONFIG_RT_USING_POSIX_AIO=y +CONFIG_RT_USING_POSIX_CLOCKTIME=y +# CONFIG_RT_USING_MODULE is not set + +# +# Network +# + +# +# Socket abstraction layer +# +CONFIG_RT_USING_SAL=y + +# +# protocol stack implement +# +CONFIG_SAL_USING_LWIP=y +CONFIG_SAL_USING_POSIX=y + +# +# Network interface device +# +CONFIG_RT_USING_NETDEV=y +CONFIG_NETDEV_USING_IFCONFIG=y +CONFIG_NETDEV_USING_PING=y +CONFIG_NETDEV_USING_NETSTAT=y +CONFIG_NETDEV_USING_AUTO_DEFAULT=y +CONFIG_NETDEV_USING_IPV6=y +CONFIG_NETDEV_IPV4=1 +CONFIG_NETDEV_IPV6=1 +# CONFIG_NETDEV_IPV6_SCOPES is not set + +# +# light weight TCP/IP stack +# +CONFIG_RT_USING_LWIP=y +# CONFIG_RT_USING_LWIP141 is not set +CONFIG_RT_USING_LWIP202=y +# CONFIG_RT_USING_LWIP212 is not set +CONFIG_RT_USING_LWIP_IPV6=y +CONFIG_RT_LWIP_MEM_ALIGNMENT=4 +CONFIG_RT_LWIP_IGMP=y +CONFIG_RT_LWIP_ICMP=y +# CONFIG_RT_LWIP_SNMP is not set +CONFIG_RT_LWIP_DNS=y +CONFIG_RT_LWIP_DHCP=y +CONFIG_IP_SOF_BROADCAST=1 +CONFIG_IP_SOF_BROADCAST_RECV=1 + +# +# Static IPv4 Address +# +CONFIG_RT_LWIP_IPADDR="192.168.1.30" +CONFIG_RT_LWIP_GWADDR="192.168.1.1" +CONFIG_RT_LWIP_MSKADDR="255.255.255.0" +CONFIG_RT_LWIP_UDP=y +CONFIG_RT_LWIP_TCP=y +CONFIG_RT_LWIP_RAW=y +# CONFIG_RT_LWIP_PPP is not set +CONFIG_RT_MEMP_NUM_NETCONN=8 +CONFIG_RT_LWIP_PBUF_NUM=16 +CONFIG_RT_LWIP_RAW_PCB_NUM=4 +CONFIG_RT_LWIP_UDP_PCB_NUM=4 +CONFIG_RT_LWIP_TCP_PCB_NUM=4 +CONFIG_RT_LWIP_TCP_SEG_NUM=40 +CONFIG_RT_LWIP_TCP_SND_BUF=8196 +CONFIG_RT_LWIP_TCP_WND=8196 +CONFIG_RT_LWIP_TCPTHREAD_PRIORITY=10 +CONFIG_RT_LWIP_TCPTHREAD_MBOX_SIZE=8 +CONFIG_RT_LWIP_TCPTHREAD_STACKSIZE=1024 +# CONFIG_LWIP_NO_RX_THREAD is not set +# CONFIG_LWIP_NO_TX_THREAD is not set +CONFIG_RT_LWIP_ETHTHREAD_PRIORITY=12 +CONFIG_RT_LWIP_ETHTHREAD_STACKSIZE=1024 +CONFIG_RT_LWIP_ETHTHREAD_MBOX_SIZE=8 +# CONFIG_RT_LWIP_REASSEMBLY_FRAG is not set +CONFIG_LWIP_NETIF_STATUS_CALLBACK=1 +CONFIG_LWIP_NETIF_LINK_CALLBACK=1 +CONFIG_SO_REUSE=1 +CONFIG_LWIP_SO_RCVTIMEO=1 +CONFIG_LWIP_SO_SNDTIMEO=1 +CONFIG_LWIP_SO_RCVBUF=1 +CONFIG_LWIP_SO_LINGER=0 +# CONFIG_RT_LWIP_NETIF_LOOPBACK is not set +CONFIG_LWIP_NETIF_LOOPBACK=0 +# CONFIG_RT_LWIP_STATS is not set +# CONFIG_RT_LWIP_USING_HW_CHECKSUM is not set +CONFIG_RT_LWIP_USING_PING=y +# CONFIG_RT_LWIP_DEBUG is not set + +# +# AT commands +# +# CONFIG_RT_USING_AT is not set +# CONFIG_LWIP_USING_DHCPD is not set + +# +# VBUS(Virtual Software BUS) +# +# CONFIG_RT_USING_VBUS is not set + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +CONFIG_RT_USING_LWP=y +CONFIG_RT_LWP_MAX_NR=30 +CONFIG_LWP_TASK_STACK_SIZE=16384 +# CONFIG_RT_USING_GDBSERVER is not set +CONFIG_RT_CH_MSG_MAX_NR=1024 +CONFIG_RT_LWP_SHM_MAX_NR=64 +CONFIG_LWP_CONSOLE_INPUT_BUFFER_SIZE=1024 +CONFIG_LWP_TID_MAX_NR=64 + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_LIBMODBUS is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_RW007 is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_libsodium is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set + +# +# language packages +# +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set + +# +# multimedia packages +# +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_ULOG_FILE is not set +# CONFIG_PKG_USING_LOGMGR is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set + +# +# system packages +# +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_PERSIMMON is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_LITTLEVGL2RTT is not set +# CONFIG_PKG_USING_CMSIS is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set +# CONFIG_PKG_USING_LPM is not set + +# +# peripheral libraries and drivers +# +# CONFIG_PKG_USING_SENSORS_DRIVERS is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_AS7341 is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_WM_LIBRARIES is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_TOUCH_DRIVERS is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_RDA58XX is not set + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set + +# +# miscellaneous packages +# +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_CRCLIB is not set + +# +# games: games run on RT-Thread console +# +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_COWSAY is not set +CONFIG_SOC_IMX6ULL=y +CONFIG_RT_USING_UART0=y +# CONFIG_RT_USING_UART1 is not set +CONFIG_BSP_DRV_EMAC=y diff --git a/bsp/imx6ull-100ask-smart/.cproject b/bsp/imx6ull-100ask-smart/.cproject new file mode 100644 index 0000000000000000000000000000000000000000..31c328ad90463d22ec9e1812ebf1f0cf7d6eac34 --- /dev/null +++ b/bsp/imx6ull-100ask-smart/.cproject @@ -0,0 +1,175 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/imx6ull-100ask-smart/.gitignore b/bsp/imx6ull-100ask-smart/.gitignore new file mode 100644 index 0000000000000000000000000000000000000000..0ce2d51447d4e9a98b2429f171655766260f06be --- /dev/null +++ b/bsp/imx6ull-100ask-smart/.gitignore @@ -0,0 +1,45 @@ +*.pyc +*.map +*.dblite +*.elf +*.bin +*.hex +*.axf +*.exe +*.pdb +*.idb +*.ilk +*.old +build +Debug +documentation/html +packages/ +*~ +*.o +*.obj +*.out +*.bak +*.dep +*.lib +*.i +*.d +.DS_Stor* +.config 3 +.config 4 +.config 5 +Midea-X1 +*.uimg +GPATH +GRTAGS +GTAGS +.vscode +JLinkLog.txt +JLinkSettings.ini +DebugConfig/ +RTE/ +settings/ +*.uvguix* +cconfig.h +.settings +drivers/automac.h +romfs.c diff --git a/bsp/imx6ull-100ask-smart/.project b/bsp/imx6ull-100ask-smart/.project new file mode 100644 index 0000000000000000000000000000000000000000..e5f00228c02c65463748aa48f618aea3e02462a9 --- /dev/null +++ b/bsp/imx6ull-100ask-smart/.project @@ -0,0 +1,54 @@ + + + qemu-vexpress-a9 + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.core.rttnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + rt-thread + 2 + virtual:/virtual + + + rt-thread/components + 2 + $%7BPARENT-2-PROJECT_LOC%7D/components + + + rt-thread/include + 2 + $%7BPARENT-2-PROJECT_LOC%7D/include + + + rt-thread/libcpu + 2 + $%7BPARENT-2-PROJECT_LOC%7D/libcpu + + + rt-thread/src + 2 + $%7BPARENT-2-PROJECT_LOC%7D/src + + + diff --git a/bsp/imx6ull-100ask-smart/Kconfig b/bsp/imx6ull-100ask-smart/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..10c1d6bcabc95234b93048c7691d06fafd962fdf --- /dev/null +++ b/bsp/imx6ull-100ask-smart/Kconfig @@ -0,0 +1,30 @@ +mainmenu "RT-Thread Project Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config RTT_DIR + string + option env="RTT_ROOT" + default "../.." + +config PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" + +config SOC_IMX6ULL + bool + select ARCH_ARM_CORTEX_A7 + select RT_USING_CACHE + select ARCH_ARM_MMU + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y + +source "$BSP_DIR/drivers/Kconfig" diff --git a/bsp/imx6ull-100ask-smart/README.md b/bsp/imx6ull-100ask-smart/README.md new file mode 100644 index 0000000000000000000000000000000000000000..9c025ec44368ef714914a12b423c120a64cc98a1 --- /dev/null +++ b/bsp/imx6ull-100ask-smart/README.md @@ -0,0 +1,111 @@ +# IMX6ULL板级支持包说明 + +## 1. 简介 + +​ IMX6ULL rt-smart 系统由百问网韦东山老师移植提供，作为CortexA7单核800M主频处理器的开发环境，开发板由myir公司提供核心板，百问网公司设计底板外设等资源 是一套专门用于学习的开发板套件，其中开发板介绍可以参考页面 http://download.100ask.org/boards/Nxp/100ask_imx6ull_pro 。 + +* 当前IMX6ULL开发板对应的硬件特性： + +| 硬件 | 描述 | +| -- | -- | +| CPU主频 | CortexA7 800Mhz x1 | +| DDR | 512MB | +| Flash| 4GB Emmc| +| Ethernet | lan8720a，10M/100M | +| Usb | UsbHost x2 UsbOtg x1 | +| wifi&bluetooth | rtl8723bu | +| Audio | wm8960 | +| Display | RGB888 LCD x1 HDMI x1 | +| Can | x1 | +| RS485 | x1 | +| AP6216 module | x1 | +| ICM8235 module | x1 | +|GPIO prot | Several | + + +* 同时开发板有配套的编译移植教程，可以使用浏览器访问此连接进行观看学习 https://www.bilibili.com/video/BV1ti4y1w7VQ + + + +## 2. 编译说明 + +​ 使用浏览器参考此页面 https://www.rt-thread.org/document/site/rt-smart/rt-smart-quickstart/rt-smart-quickstart/ 参考官方编译说明文档下载并配置相应的环境。 + +### 2.1 下载ENV工具 + +​ 在Windows下请下载[env工具](https://www.rt-thread.org/page/download.html)。 + +### 2.2 下载工具链 + +请先下载对应的工具链并展开到`rtthread-smart/tools/gnu_gcc`目录： + +* [Windows环境](http://117.143.63.254:9012/www/rt-smart/install_arm-linux-musleabi_for_i686-w64-mingw32.zip) +* [Linux环境](http://117.143.63.254:9012/www/rt-smart/install_arm-linux-musleabi_for_x86_64-pc-linux-gnu.tar.bz2) + +目录参考如下： + +``` bash +rtthread-smart\tools\gnu_gcc\install_arm-linux-musleabi_for_i686-w64-mingw32 +``` + +下载env工具，运行`env.bat`进入命令行。 +然后切换到这个代码包根目录rtthread-smart，**运行smart-env.bat**，它会设置一定的环境变量，然后整体的smart开发环境就可以使用了。 + +```bash +> cd \workspace\rt-smart +> smart-env.bat +``` + +**注** + +此处运行smart-env.bat以设置环境，这步非常重要，它包括编译器设置。同时它也会设置工具链的前缀，可以在env终端下输入`set RTT_CC_PREFIX`命令看看返回结果是否生效： + +```bash +> set RTT_CC_PREFIX +RTT_CC_PREFIX=arm-linux-musleabi- +``` + + + +## 2.3 获取最新kernel源码并编译 + +​ 参考上述说明配置好编译环境后，我们需要获取最新支持 imx6ull开发板的kernel源码，进入rt-smart目录下,首先移除掉默认的kernel 再使用git命令获取最新的rt-smart kernel源码. + +``` +> mv kerenl kernel_bak +> git clone https://gitee.com/rtthread/rt-thread.git -b rt-smart kernel +``` + +​ 使用[env工具][2]，可以在console下进入到rt-smart源码 kernel/bsp/imx6ull目录中，运行以下编译命令： + + scons + +​ 来编译这个板级支持包。如果编译正确无误，会产生rtthread.elf、rtthread.bin rtthread.imx文件。需要使用 百问网imx6ull烧写工具 http://wiki.100ask.org/100ask_imx6ull_tool 烧写更新 rtthread.imx 至imx6ull开发板。 + + + +## 3. 执行 + +​ 烧写方式请参考 https://www.bilibili.com/video/BV19A411s7f9?p=2 视频进行操作， + +​ 烧写成功后打开串口输出就可以看到如下启动打印信息了。 + +```text + \ | / +- RT - Thread Smart Operating System + / | \ 5.0.0 build Dec 22 2020 + 2006 - 2020 Copyright by rt-thread team +lwIP-2.0.2 initialized! +[I/sal.skt] Socket Abstraction Layer initialize success. +Dir /mnt mount failed! +hello rt-thread +msh /> + +``` + +## 4. 联系人信息 + +维护人：[weidongshan][2] + +[1]: http://infocenter.arm.com/help/index.jsp? +[2]: https://gitee.com/weidongshan diff --git a/bsp/imx6ull-100ask-smart/SConscript b/bsp/imx6ull-100ask-smart/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..c7ef7659ecea92b1dd9b71a97736a8552ee02551 --- /dev/null +++ b/bsp/imx6ull-100ask-smart/SConscript @@ -0,0 +1,14 @@ +# for module compiling +import os +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/imx6ull-100ask-smart/SConstruct b/bsp/imx6ull-100ask-smart/SConstruct new file mode 100644 index 0000000000000000000000000000000000000000..e1bc58f2c0b68d97bda381cde3e5456dcddcc7aa --- /dev/null +++ b/bsp/imx6ull-100ask-smart/SConstruct @@ -0,0 +1,33 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.join(os.getcwd(), '..', '..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +from building import * + +TARGET = 'rtthread.' + rtconfig.TARGET_EXT + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS, + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) +env['ASCOM'] = env['ASPPCOM'] +env['LINKCOM'] = '$LINK -o $TARGET $LINKFLAGS $__RPATH $SOURCES $_LIBDIRFLAGS -Wl,--start-group $_LIBFLAGS -Wl,--end-group' + +Export('RTT_ROOT') +Export('rtconfig') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/imx6ull-100ask-smart/applications/SConscript b/bsp/imx6ull-100ask-smart/applications/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..89083a964a159e254033baaa552061b3f03addb0 --- /dev/null +++ b/bsp/imx6ull-100ask-smart/applications/SConscript @@ -0,0 +1,11 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('*.cpp') +CPPPATH = [cwd] + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/imx6ull-100ask-smart/applications/lcd_init.c b/bsp/imx6ull-100ask-smart/applications/lcd_init.c new file mode 100644 index 0000000000000000000000000000000000000000..75fcfe9f19964fd62041b0961196dfb09057f9d3 --- /dev/null +++ b/bsp/imx6ull-100ask-smart/applications/lcd_init.c @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ +#include + +#if defined(RT_USING_RTGUI) || defined(PKG_USING_GUIENGINE) + +#include +int lcd_init(void) +{ + struct rt_device *device; + device = rt_device_find("lcd"); + if (device) + { + rtgui_graphic_set_device(device); + } + + return 0; +} +INIT_APP_EXPORT(lcd_init); + +#endif diff --git a/bsp/imx6ull-100ask-smart/applications/main.c b/bsp/imx6ull-100ask-smart/applications/main.c new file mode 100644 index 0000000000000000000000000000000000000000..d939e28fef5bc12768f66ad59f2910429dfe96dc --- /dev/null +++ b/bsp/imx6ull-100ask-smart/applications/main.c @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020/10/7 bernard the first version + */ +#include +#include +#include + +int main(void) +{ + printf("hello rt-smart\n"); + return 0; +} + diff --git a/bsp/imx6ull-100ask-smart/applications/mnt.c b/bsp/imx6ull-100ask-smart/applications/mnt.c new file mode 100644 index 0000000000000000000000000000000000000000..88107618916d17aad6d80b6c9bad9329c7d92c36 --- /dev/null +++ b/bsp/imx6ull-100ask-smart/applications/mnt.c @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ + #include + +#ifdef RT_USING_DFS +#include +#include + +int mnt_init(void) +{ + if (dfs_mount(RT_NULL, "/", "rom", 0, &romfs_root) != 0) + { + rt_kprintf("Dir / mount failed!\n"); + return -1; + } + + rt_thread_mdelay(200); + if (dfs_mount("sd0", "/mnt", "elm", 0, NULL) != 0) + { + rt_kprintf("Dir /mnt mount failed!\n"); + return -1; + } + + rt_kprintf("file system initialization done!\n"); + return 0; +} +INIT_ENV_EXPORT(mnt_init); +#endif + diff --git a/bsp/imx6ull-100ask-smart/drivers/Kconfig b/bsp/imx6ull-100ask-smart/drivers/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..0eea26be5875e940d61186a0f699c4fede5255ab --- /dev/null +++ b/bsp/imx6ull-100ask-smart/drivers/Kconfig @@ -0,0 +1,11 @@ +config RT_USING_UART0 + bool "Enable UART0" + default n + +config RT_USING_UART1 + bool "Enable UART1" + default y + +config BSP_DRV_EMAC + bool "EMAC driver" + default y diff --git a/bsp/imx6ull-100ask-smart/drivers/SConscript b/bsp/imx6ull-100ask-smart/drivers/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..4f10c262171804689c151339a081c037df768460 --- /dev/null +++ b/bsp/imx6ull-100ask-smart/drivers/SConscript @@ -0,0 +1,23 @@ +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') +list = os.listdir(cwd) +CPPPATH = [cwd] +objs = [] + +if not GetDepend('BSP_DRV_EMAC'): + SrcRemove(src, ['drv_smc911x.c']) + +if not GetDepend('BSP_DRV_CLCD'): + SrcRemove(src, ['drv_clcd.c']) + +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) +objs = objs + group + +Return('objs') diff --git a/bsp/imx6ull-100ask-smart/drivers/board.c b/bsp/imx6ull-100ask-smart/drivers/board.c new file mode 100644 index 0000000000000000000000000000000000000000..7087ad893af8a0b5297abc3d95a0cc59a730d990 --- /dev/null +++ b/bsp/imx6ull-100ask-smart/drivers/board.c @@ -0,0 +1,92 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2012-11-20 Bernard the first version + * 2018-11-22 Jesven add rt_hw_spin_lock + * add rt_hw_spin_unlock + * add smp ipi init + */ + +#include +#include + +#include "board.h" +#include "drv_timer.h" + +#include +#ifdef RT_USING_USERSPACE +#include +#include +#endif + +#ifdef RT_USING_USERSPACE +struct mem_desc platform_mem_desc[] = { /* 100ask_imx6ull ddr 512M */ + {KERNEL_VADDR_START, KERNEL_VADDR_START + 0x1FFFFFFF, KERNEL_VADDR_START + PV_OFFSET, NORMAL_MEM} +}; +#else +struct mem_desc platform_mem_desc[] = { + {0x10000000, 0x50000000, 0x10000000, DEVICE_MEM}, + {0x60000000, 0x70000000, 0x60000000, NORMAL_MEM} +}; +#endif + +const rt_uint32_t platform_mem_desc_size = sizeof(platform_mem_desc)/sizeof(platform_mem_desc[0]); + +#define SYS_CTRL __REG32(REALVIEW_SCTL_BASE) + +extern void rt_hw_ipi_handler_install(int ipi_vector, rt_isr_handler_t ipi_isr_handler); + +void idle_wfi(void) +{ + asm volatile ("wfi"); +} + +/** + * This function will initialize board + */ + +rt_mmu_info mmu_info; + +extern size_t MMUTable[]; + +#ifdef RT_USING_USERSPACE +rt_region_t init_page_region = { + (uint32_t)PAGE_START, + (uint32_t)PAGE_END, +}; +#endif + +void rt_hw_board_init(void) +{ +#ifdef RT_USING_USERSPACE + rt_hw_mmu_map_init(&mmu_info, (void*)0xf0000000, 0x10000000, MMUTable, PV_OFFSET); + + rt_page_init(init_page_region); + rt_hw_mmu_ioremap_init(&mmu_info, (void*)0xf0000000, 0x10000000); + + arch_kuser_init(&mmu_info, (void*)0xffff0000); +#else + rt_hw_mmu_map_init(&mmu_info, (void*)0x80000000, 0x10000000, MMUTable, 0); + rt_hw_mmu_ioremap_init(&mmu_info, (void*)0x80000000, 0x10000000); +#endif + + /* initialize hardware interrupt */ + rt_hw_interrupt_init(); + + /* initialize system heap */ + rt_system_heap_init(HEAP_BEGIN, HEAP_END); + + rt_components_board_init(); + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); + + rt_thread_idle_sethook(idle_wfi); + +#ifdef RT_USING_SMP + /* install IPI handle */ + rt_hw_ipi_handler_install(RT_SCHEDULE_IPI, rt_scheduler_ipi_handler); +#endif +} diff --git a/bsp/imx6ull-100ask-smart/drivers/board.h b/bsp/imx6ull-100ask-smart/drivers/board.h new file mode 100644 index 0000000000000000000000000000000000000000..80636e41efe317c7303a3463aa4da957c0402655 --- /dev/null +++ b/bsp/imx6ull-100ask-smart/drivers/board.h @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include + +#include "imx6ul.h" +#include "mmu.h" + +#if defined(__CC_ARM) +extern int Image$$RW_IRAM1$$ZI$$Limit; +#define HEAP_BEGIN ((void*)&Image$$RW_IRAM1$$ZI$$Limit) +#elif defined(__GNUC__) +extern int __bss_end; +#define HEAP_BEGIN ((void*)&__bss_end) +#endif + +#ifdef RT_USING_USERSPACE +#define HEAP_END (void*)(KERNEL_VADDR_START + 16 * 1024 * 1024) +#define PAGE_START HEAP_END +#define PAGE_END (void*)(KERNEL_VADDR_START + 128 * 1024 * 1024) +#else +#define HEAP_END (void*)(0x60000000 + 64 * 1024 * 1024) +#endif + +void rt_hw_board_init(void); + +extern rt_mmu_info mmu_info; + +#endif diff --git a/bsp/imx6ull-100ask-smart/drivers/drv_timer.c b/bsp/imx6ull-100ask-smart/drivers/drv_timer.c new file mode 100644 index 0000000000000000000000000000000000000000..03f497315eaf146c1c60a2f7dc2489718a1925e4 --- /dev/null +++ b/bsp/imx6ull-100ask-smart/drivers/drv_timer.c @@ -0,0 +1,174 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-11-22 Jesven first version + */ + +#include +#include +#include + +#include "mmu.h" + +#define TICK_PERIOD (g_sys_freq / RT_TICK_PER_SECOND) +static int g_sys_freq; + +#define IRQ_SECURE_PHY_TIMER 29 /* Secure physical timer event */ +#define IRQ_NOSECURE_PHY_TIMER 30 /* No-Secure physical timer event */ + +#define IRQ_SYS_TICK IRQ_SECURE_PHY_TIMER + + +/* System Counter */ +struct sctr_regs { + rt_uint32_t cntcr; + rt_uint32_t cntsr; + rt_uint32_t cntcv1; + rt_uint32_t cntcv2; + rt_uint32_t resv1[4]; + rt_uint32_t cntfid0; + rt_uint32_t cntfid1; + rt_uint32_t cntfid2; + rt_uint32_t resv2[1001]; + rt_uint32_t counterid[1]; +}; + +#define SC_CNTCR_ENABLE (1 << 0) +#define SC_CNTCR_HDBG (1 << 1) +#define SC_CNTCR_FREQ0 (1 << 8) +#define SC_CNTCR_FREQ1 (1 << 9) + + +#define isb() __asm__ __volatile__ ("" : : : "memory") +#define dsb() __asm__ __volatile__ ("" : : : "memory") +#define dmb() __asm__ __volatile__ ("" : : : "memory") + + +static inline void enable_cntp(void) +{ + rt_uint32_t cntv_ctl; + cntv_ctl = 1; + asm volatile ("mcr p15, 0, %0, c14, c2, 1" :: "r"(cntv_ctl)); // write CNTP_CTL + isb(); +} + +static inline void disable_cntp(void) +{ + rt_uint32_t cntv_ctl; + cntv_ctl = 0; + asm volatile ("mcr p15, 0, %0, c14, c2, 1" :: "r"(cntv_ctl)); // write CNTP_CTL + isb(); +} + +static inline rt_uint32_t read_cntfrq(void) +{ + rt_uint32_t val; + asm volatile ("mrc p15, 0, %0, c14, c0, 0" : "=r"(val)); + return val; +} + +static inline void write_cntp_tval(rt_uint32_t val) +{ + asm volatile ("mcr p15, 0, %0, c14, c2, 0" :: "r"(val)); + isb(); + return; +} + +static inline void write_cntp_cval(rt_uint64_t val) +{ + asm volatile ("mcrr p15, 2, %Q0, %R0, c14" :: "r" (val)); + isb(); + return; +} + +static inline rt_uint64_t read_cntp_cval(void) +{ + rt_uint64_t val; + asm volatile ("mrrc p15, 2, %Q0, %R0, c14" : "=r" (val)); + return (val); +} + +volatile unsigned int *CCM_CLPCR; + +static void imx6ull_enable_clk_in_waitmode(void) +{ + CCM_CLPCR = rt_hw_kernel_phys_to_virt((void*)0x20C4054, 4); + *CCM_CLPCR &= ~(1<<5 | 0x3); +} + +static void system_counter_clk_source_init(void) +{ + /* to do */ +} + +static void system_counter_init(void) +{ + /* enable system_counter */ +#define SCTR_BASE_ADDR 0x021DC000 +#define CONFIG_SC_TIMER_CLK 8000000 + + /* imx6ull, enable system counter */ + struct sctr_regs *sctr = (struct sctr_regs *)rt_hw_kernel_phys_to_virt((void*)SCTR_BASE_ADDR, sizeof(struct sctr_regs)); + unsigned long val, freq; + + freq = CONFIG_SC_TIMER_CLK; + asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq)); + + sctr->cntfid0 = freq; + + /* Enable system counter */ + val = sctr->cntcr; + val &= ~(SC_CNTCR_FREQ0 | SC_CNTCR_FREQ1); + val |= SC_CNTCR_FREQ0 | SC_CNTCR_ENABLE | SC_CNTCR_HDBG; + sctr->cntcr = val; + + imx6ull_enable_clk_in_waitmode(); +} + +static void arch_timer_init(void) +{ + g_sys_freq = read_cntfrq(); + + /* set timeout val */ + disable_cntp(); + write_cntp_tval(TICK_PERIOD); + + /* start timer */ + enable_cntp(); + + /* enable irq */ + +} + + +static void rt_hw_timer_isr(int vector, void *param) +{ + rt_tick_increase(); + + /* setup for next irq */ + /* clear interrupt */ + disable_cntp(); + write_cntp_cval(read_cntp_cval() + TICK_PERIOD); + enable_cntp(); +} + +int rt_hw_timer_init(void) +{ + /* Setup Timer for generating irq */ + /* enable timer */ + system_counter_clk_source_init(); + system_counter_init(); + arch_timer_init(); + + /* insall irq, enable irq */ + rt_hw_interrupt_install(IRQ_SYS_TICK, rt_hw_timer_isr, RT_NULL, "tick"); + rt_hw_interrupt_umask(IRQ_SYS_TICK); + + return 0; +} +INIT_BOARD_EXPORT(rt_hw_timer_init); + diff --git a/bsp/imx6ull-100ask-smart/drivers/drv_timer.h b/bsp/imx6ull-100ask-smart/drivers/drv_timer.h new file mode 100644 index 0000000000000000000000000000000000000000..718f5d43cf230b973f376b8d646267eed9ac9bcf --- /dev/null +++ b/bsp/imx6ull-100ask-smart/drivers/drv_timer.h @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-11-22 Jesven first version + */ + +#ifndef DRV_TIMER_H__ +#define DRV_TIMER_H__ + +void timer_init(int timer, unsigned int preload); +void timer_clear_pending(int timer); + +#endif diff --git a/bsp/imx6ull-100ask-smart/drivers/imx6ul.h b/bsp/imx6ull-100ask-smart/drivers/imx6ul.h new file mode 100644 index 0000000000000000000000000000000000000000..e08da5b224b9596753c15b98a6292562b12b8c9d --- /dev/null +++ b/bsp/imx6ull-100ask-smart/drivers/imx6ul.h @@ -0,0 +1,263 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-03-22 quanzhao first version + */ +#ifndef __IMX6UL_H__ +#define __IMX6UL_H__ + +#include +#include + +enum _gic_base_offsets +{ + kGICDBaseOffset = 0x1000, //!< GIC distributor offset. + kGICCBaseOffset = 0x2000 //!< GIC CPU interface offset. +}; + +/* SOC-relative definitions */ +enum _imx_interrupts +{ + SW_INTERRUPT_0 = 0, //!< Software interrupt 0. + SW_INTERRUPT_1 = 1, //!< Software interrupt 1. + SW_INTERRUPT_2 = 2, //!< Software interrupt 2. + SW_INTERRUPT_3 = 3, //!< Software interrupt 3. + SW_INTERRUPT_4 = 4, //!< Software interrupt 4. + SW_INTERRUPT_5 = 5, //!< Software interrupt 5. + SW_INTERRUPT_6 = 6, //!< Software interrupt 6. + SW_INTERRUPT_7 = 7, //!< Software interrupt 7. + SW_INTERRUPT_8 = 8, //!< Software interrupt 8. + SW_INTERRUPT_9 = 9, //!< Software interrupt 9. + SW_INTERRUPT_10 = 10, //!< Software interrupt 10. + SW_INTERRUPT_11 = 11, //!< Software interrupt 11. + SW_INTERRUPT_12 = 12, //!< Software interrupt 12. + SW_INTERRUPT_13 = 13, //!< Software interrupt 13. + SW_INTERRUPT_14 = 14, //!< Software interrupt 14. + SW_INTERRUPT_15 = 15, //!< Software interrupt 15. + RSVD_INTERRUPT_16 = 16, //!< Reserved. + RSVD_INTERRUPT_17 = 17, //!< Reserved. + RSVD_INTERRUPT_18 = 18, //!< Reserved. + RSVD_INTERRUPT_19 = 19, //!< Reserved. + RSVD_INTERRUPT_20 = 20, //!< Reserved. + RSVD_INTERRUPT_21 = 21, //!< Reserved. + RSVD_INTERRUPT_22 = 22, //!< Reserved. + RSVD_INTERRUPT_23 = 23, //!< Reserved. + RSVD_INTERRUPT_24 = 24, //!< Reserved. + RSVD_INTERRUPT_25 = 25, //!< Reserved. + RSVD_INTERRUPT_26 = 26, //!< Reserved. + RSVD_INTERRUPT_27 = 27, //!< Reserved. + RSVD_INTERRUPT_28 = 28, //!< Reserved. + RSVD_INTERRUPT_29 = 29, //!< Reserved. + RSVD_INTERRUPT_30 = 30, //!< Reserved. + RSVD_INTERRUPT_31 = 31, //!< Reserved. + IMX_INT_IOMUXC_GPR = 32, //!< General Purpose Register 1 from IOMUXC. Used to notify cores on exception condition while boot. + IMX_INT_CHEETAH_CSYSPWRUPREQ = 33, //!< @todo Listed as DAP in RM + IMX_INT_SDMA = 34, //!< Logical OR of all 48 SDMA interrupt requests/events from all channels. + IMX_INT_TSC = 35, //!< TSC + IMX_INT_SNVS_LP_SET_PWR_OFF = 36, //!< PMIC power off request. + IMX_INT_LCDIF = 37, //!< LCDIF interrupt request. + IMX_INT_BEE = 38, //!< BEE interrupt request. + IMX_INT_CSI = 39, //!< CMOS Sensor Interface interrupt request. + IMX_INT_PXP = 40, //!< PXP interrupt request. + IMX_INT_SCTR1 = 41, //!< SCTR1 + IMX_INT_SCTR2 = 42, //!< SCTR2 + IMX_INT_WDOG3 = 43, //!< WDOG3 timer reset interrupt request. + IMX_INT_INTERRUPT_44 = 44, //!< Reserved. + IMX_INT_APBH_DMA = 45, //!< APBH DMA + IMX_INT_EIM = 46, //!< EIM interrupt request. + IMX_INT_NAND_BCH = 47, //!< Reserved. + IMX_INT_NAND_GPMI = 48, //!< Reserved. + IMX_INT_UART6 = 49, //!< Logical OR of UART5 interrupt requests. + IMX_INT_INTERRUPT_50 = 50, //!< Reserved. + IMX_INT_SNVS = 51, //!< SNVS consolidated interrupt. + IMX_INT_SNVS_SEC = 52, //!< SNVS security interrupt. + IMX_INT_CSU = 53, //!< CSU interrupt request 1. Indicates to the processor that one or more alarm inputs were asserted. + IMX_INT_USDHC1 = 54, //!< uSDHC1 (Enhanced SDHC) interrupt request. + IMX_INT_USDHC2 = 55, //!< uSDHC2 (Enhanced SDHC) interrupt request. + IMX_INT_SAI3 = 56, //!< uSDHC3 (Enhanced SDHC) interrupt request. + IMX_INT_SAI4 = 57, //!< uSDHC4 (Enhanced SDHC) interrupt request. + IMX_INT_UART1 = 58, //!< Logical OR of UART1 interrupt requests. + IMX_INT_UART2 = 59, //!< Logical OR of UART2 interrupt requests. + IMX_INT_UART3 = 60, //!< Logical OR of UART3 interrupt requests. + IMX_INT_UART4 = 61, //!< Logical OR of UART4 interrupt requests. + IMX_INT_UART5 = 62, //!< Logical OR of UART5 interrupt requests. + IMX_INT_ECSPI1 = 63, //!< eCSPI1 interrupt request. + IMX_INT_ECSPI2 = 64, //!< eCSPI2 interrupt request. + IMX_INT_ECSPI3 = 65, //!< eCSPI3 interrupt request. + IMX_INT_ECSPI4 = 66, //!< eCSPI4 interrupt request. + IMX_INT_I2C4 = 67, //!< Reserved. + IMX_INT_I2C1 = 68, //!< I2C1 interrupt request. + IMX_INT_I2C2 = 69, //!< I2C2 interrupt request. + IMX_INT_I2C3 = 70, //!< I2C3 interrupt request. + IMX_INT_UART7 = 71, //!< Logical OR of UART5 interrupt requests. + IMX_INT_UART8 = 72, //!< Logical OR of UART5 interrupt requests. + IMX_INT_INTERRUPT_73 = 73, //!< Reserved. + IMX_INT_USB_OTG2 = 74, //!< USB Host 1 interrupt request. + IMX_INT_USB_OTG1 = 75, //!< USB OTG1 interrupt request. + IMX_INT_USB_UTMI0 = 76, //!< UTMI0 interrupt request. + IMX_INT_USB_UTMI1 = 77, //!< UTMI1 interrupt request. + IMX_INT_CAAM_JQ2 = 78, //!< SSI1 interrupt request. + IMX_INT_CAAM_ERR = 79, //!< SSI2 interrupt request. + IMX_INT_CAAM_RTIC = 80, //!< SSI3 interrupt request. + IMX_INT_TEMPERATURE = 81, //!< Temperature Sensor (temp. greater than threshold) interrupt request. + IMX_INT_ASRC = 82, //!< Reserved. + IMX_INT_INTERRUPT_83 = 83, //!< Reserved. + IMX_INT_SPDIF = 84, //!< Logical OR of SPDIF TX and SPDIF RX interrupts. + IMX_INT_INTERRUPT_85 = 85, //!< Reserved. + IMX_INT_PMU_ANA_BO = 86, //!< PMU analog regulator brown-out interrupt request. + IMX_INT_GPT1 = 87, // + IMX_INT_EPIT1 = 88, //!< EPIT1 output compare interrupt. + IMX_INT_EPIT2 = 89, //!< EPIT2 output compare interrupt. + IMX_INT_GPIO1_INT7 = 90, //!< INT7 interrupt request. + IMX_INT_GPIO1_INT6 = 91, //!< INT6 interrupt request. + IMX_INT_GPIO1_INT5 = 92, //!< INT5 interrupt request. + IMX_INT_GPIO1_INT4 = 93, //!< INT4 interrupt request. + IMX_INT_GPIO1_INT3 = 94, //!< INT3 interrupt request. + IMX_INT_GPIO1_INT2 = 95, //!< INT2 interrupt request. + IMX_INT_GPIO1_INT1 = 96, //!< INT1 interrupt request. + IMX_INT_GPIO1_INT0 = 97, //!< INT0 interrupt request. + IMX_INT_GPIO1_INT15_0 = 98, //!< Combined interrupt indication for GPIO1 signals 0 - 15. + IMX_INT_GPIO1_INT31_16 = 99, //!< Combined interrupt indication for GPIO1 signals 16 - 31. + IMX_INT_GPIO2_INT15_0 = 100, //!< Combined interrupt indication for GPIO2 signals 0 - 15. + IMX_INT_GPIO2_INT31_16 = 101, //!< Combined interrupt indication for GPIO2 signals 16 - 31. + IMX_INT_GPIO3_INT15_0 = 102, //!< Combined interrupt indication for GPIO3 signals 0 - 15. + IMX_INT_GPIO3_INT31_16 = 103, //!< Combined interrupt indication for GPIO3 signals 16 - 31. + IMX_INT_GPIO4_INT15_0 = 104, //!< Combined interrupt indication for GPIO4 signals 0 - 15. + IMX_INT_GPIO4_INT31_16 = 105, //!< Combined interrupt indication for GPIO4 signals 16 - 31. + IMX_INT_GPIO5_INT15_0 = 106, //!< Combined interrupt indication for GPIO5 signals 0 - 15. + IMX_INT_GPIO5_INT31_16 = 107, //!< Combined interrupt indication for GPIO5 signals 16 - 31. + IMX_INT_INTERRUPT_108 = 108, //!< Reserved. + IMX_INT_INTERRUPT_109 = 109, //!< Reserved. + IMX_INT_INTERRUPT_110 = 110, //!< Reserved. + IMX_INT_INTERRUPT_111 = 111, //!< Reserved. + IMX_INT_WDOG1 = 112, //!< WDOG1 timer reset interrupt request. + IMX_INT_WDOG2 = 113, //!< WDOG2 timer reset interrupt request. + IMX_INT_KPP = 114, //!< Key Pad interrupt request. + IMX_INT_PWM1 = 115, //!< Cumulative interrupt line for PWM1. Logical OR of rollover, compare, and FIFO waterlevel crossing interrupts. + IMX_INT_PWM2 = 116, //!< Cumulative interrupt line for PWM2. Logical OR of rollover, compare, and FIFO waterlevel crossing interrupts. + IMX_INT_PWM3 = 117, //!< Cumulative interrupt line for PWM3. Logical OR of rollover, compare, and FIFO waterlevel crossing interrupts. + IMX_INT_PWM4 = 118, //!< Cumulative interrupt line for PWM4. Logical OR of rollover, compare, and FIFO waterlevel crossing interrupts. + IMX_INT_CCM_INT1 = 119, //!< CCM interrupt request 1. + IMX_INT_CCM_INT2 = 120, //!< CCM interrupt request 2. + IMX_INT_GPC_INT1 = 121, //!< GPC interrupt request 1. + IMX_INT_INTERRUPT_122 = 122, //!< Reserved. + IMX_INT_SRC = 123, //!< SRC interrupt request. + IMX_INT_INTERRUPT_124 = 124, //!< Logical OR of all L2 interrupt requests. + IMX_INT_INTERRUPT_125 = 125, //!< Parity Check error interrupt request. + IMX_INT_CHEETAH_PERFORM = 126, //!< Logical OR of Performance Unit interrupts. + IMX_INT_CHEETAH_TRIGGER = 127, //!< Logical OR of CTI trigger outputs. + IMX_INT_SRC_CPU_WDOG = 128, //!< Combined CPU wdog interrupts (4x) out of SRC. + IMX_INT_SAI1 = 129, //!< EPDC interrupt request. + IMX_INT_SAI2 = 130, //!< EPDC interrupt request. + IMX_INT_INTERRUPT_131 = 131, //!< DCP general interrupt request. + IMX_INT_ADC1 = 132, //!< DCP channel 0 interrupt request. + IMX_INT_ADC2 = 133, //!< DCP secure interrupt request. + IMX_INT_INTERRUPT_134 = 134, //!< Reserved. + IMX_INT_INTERRUPT_135 = 135, //!< Reserved. + IMX_INT_SJC = 136, //!< SJC interrupt from General Purpose register. + IMX_INT_CAAM_0 = 137, //!< Reserved. + IMX_INT_CAAM_1 = 138, //!< Reserved. + IMX_INT_QSPI = 139, //!< Reserved. + IMX_INT_TZASC1 = 140, //!< ASC1 interrupt request. + IMX_INT_GPT2 = 141, //!< Reserved. + IMX_INT_CAN1 = 142, //!< Reserved. + IMX_INT_CAN2 = 143, //!< Reserved. + IMX_INT_SIM1 = 144, //!< Reserved. + IMX_INT_SIM2 = 145, //!< Reserved. + IMX_INT_PWM5 = 146, //!< Fast Ethernet Controller interrupt request. + IMX_INT_PWM6 = 147, //!< Reserved. + IMX_INT_PWM7 = 148, //!< Reserved. + IMX_INT_PWM8 = 149, //!< Reserved. + IMX_INT_ENET1 = 150, //!< Reserved. + IMX_INT_ENET1_TIMER = 151, //!< Reserved. + IMX_INT_ENET2 = 152, //!< Reserved. + IMX_INT_ENET2_TIMER = 153, //!< Reserved. + IMX_INT_INTERRUPT_154 = 154, //!< Reserved. + IMX_INT_INTERRUPT_155 = 155, //!< Reserved. + IMX_INT_INTERRUPT_156 = 156, //!< Reserved. + IMX_INT_INTERRUPT_157 = 157, //!< Reserved. + IMX_INT_INTERRUPT_158 = 158, //!< Reserved. + IMX_INT_PMU_DIG_BO = 159, //!< //!< PMU digital regulator brown-out interrupt request. + IMX_INTERRUPT_COUNT = 160 //!< Total number of interrupts. +}; + +/* the maximum number of gic */ +# define ARM_GIC_MAX_NR 1 + +/* the maximum number of interrupts */ +#define ARM_GIC_NR_IRQS IMX_INTERRUPT_COUNT + +/* the maximum entries of the interrupt table */ +#define MAX_HANDLERS IMX_INTERRUPT_COUNT + +/* the basic constants needed by gic */ +rt_inline rt_uint32_t platform_get_gic_dist_base(void) +{ + rt_uint32_t gic_base; + asm volatile ("mrc p15, 4, %0, c15, c0, 0" : "=r"(gic_base)); + return gic_base + kGICDBaseOffset; +} + +rt_inline rt_uint32_t platform_get_gic_cpu_base(void) +{ + rt_uint32_t gic_base; + asm volatile ("mrc p15, 4, %0, c15, c0, 0" : "=r"(gic_base)); + return gic_base + kGICCBaseOffset; +} + +#define GIC_IRQ_START 0 + +#define GIC_ACK_INTID_MASK 0x000003ff + +/* the definition needed by gic.c */ +#define __REG32(x) (*((volatile unsigned int *)(x))) + +/* keep compatible with platform SDK */ +typedef enum { + CPU_0, + CPU_1, + CPU_2, + CPU_3, +} cpuid_e; + +enum _gicd_sgi_filter +{ + //! Forward the interrupt to the CPU interfaces specified in the @a target_list parameter. + kGicSgiFilter_UseTargetList = 0, + + //! Forward the interrupt to all CPU interfaces except that of the processor that requested + //! the interrupt. + kGicSgiFilter_AllOtherCPUs = 1, + + //! Forward the interrupt only to the CPU interface of the processor that requested the + //! interrupt. + kGicSgiFilter_OnlyThisCPU = 2 +}; + +typedef void (*irq_hdlr_t) (void); + +extern void rt_hw_interrupt_mask(int vector); +extern void rt_hw_interrupt_umask(int vector); +extern rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, + void *param, const char *name); + +rt_inline void register_interrupt_routine(uint32_t irq_id, irq_hdlr_t isr) +{ + rt_hw_interrupt_install(irq_id, (rt_isr_handler_t)isr, RT_NULL, "unknown"); +} + +rt_inline void enable_interrupt(uint32_t irq_id, uint32_t cpu_id, uint32_t priority) +{ + rt_hw_interrupt_umask(irq_id); +} + +rt_inline void disable_interrupt(uint32_t irq_id, uint32_t cpu_id) +{ + rt_hw_interrupt_mask(irq_id); +} + +#endif /* __IMX6UL_H__ */ diff --git a/bsp/imx6ull-100ask-smart/drivers/rt_lcd.h b/bsp/imx6ull-100ask-smart/drivers/rt_lcd.h new file mode 100644 index 0000000000000000000000000000000000000000..e496a871da38693db597dcc45ac9a181c8d0c55a --- /dev/null +++ b/bsp/imx6ull-100ask-smart/drivers/rt_lcd.h @@ -0,0 +1,59 @@ +#ifndef RT_LCD_H__ +#define RT_LCD_H__ + + +/* ioctls + 0x46 is 'F' */ +#define FBIOGET_VSCREENINFO 0x4600 +#define FBIOPUT_VSCREENINFO 0x4601 +#define FBIOGET_FSCREENINFO 0x4602 +#define FBIOGETCMAP 0x4604 +#define FBIOPUTCMAP 0x4605 +#define FBIOPAN_DISPLAY 0x4606 +#define FBIO_CURSOR 0x4608 +/* #define FBIOGET_MONITORSPEC 0x460C */ +/* #define FBIOPUT_MONITORSPEC 0x460D */ +/* #define FBIOSWITCH_MONIBIT 0x460E */ +#define FBIOGET_CON2FBMAP 0x460F +#define FBIOPUT_CON2FBMAP 0x4610 +#define FBIOBLANK 0x4611 /* arg: 0 or vesa level + 1 */ +#define FBIOGET_VBLANK 0x4612 +#define FBIO_ALLOC 0x4613 +#define FBIO_FREE 0x4614 +#define FBIOGET_GLYPH 0x4615 +#define FBIOGET_HWCINFO 0x4616 +#define FBIOPUT_MODEINFO 0x4617 +#define FBIOGET_DISPINFO 0x4618 +#define FBIO_WAITFORVSYNC 0x4620 + +struct fb_bitfield +{ + uint32_t offset; /* beginning of bitfield */ + uint32_t length; /* length of bitfield */ + uint32_t msb_right; /* != 0 : Most significant bit is */ + /* right */ +}; + +struct fb_var_screeninfo +{ + uint32_t xres; + uint32_t yres; + + uint32_t bits_per_pixel; + + struct fb_bitfield red; /* bitfield in fb mem if true color, */ + struct fb_bitfield green; /* else only length is significant */ + struct fb_bitfield blue; + struct fb_bitfield transp; /* transparency */ +}; + +struct fb_fix_screeninfo +{ + char id[16]; + unsigned long smem_start; + uint32_t smem_len; + + uint32_t line_length; +}; + +#endif diff --git a/bsp/imx6ull-100ask-smart/drivers/rv.h b/bsp/imx6ull-100ask-smart/drivers/rv.h new file mode 100644 index 0000000000000000000000000000000000000000..13e5b6c520003f2e2ae33d05fb0005584cc85c2a --- /dev/null +++ b/bsp/imx6ull-100ask-smart/drivers/rv.h @@ -0,0 +1,331 @@ +#ifndef __AM33XX_H__ +#define __AM33XX_H__ + +#define __REG32(x) (*((volatile unsigned int *)(x))) +#define __REG16(x) (*((volatile unsigned short *)(x))) + +/* + * Peripheral addresses + */ +#define REALVIEW_UART0_BASE 0x10009000 /* UART 0 */ +#define REALVIEW_UART1_BASE 0x1000A000 /* UART 1 */ +#define REALVIEW_UART2_BASE 0x1000B000 /* UART 2 */ +#define REALVIEW_UART3_BASE 0x1000C000 /* UART 3 */ +#define REALVIEW_SSP_BASE 0x1000D000 /* Synchronous Serial Port */ +#define REALVIEW_WATCHDOG0_BASE 0x1000F000 /* Watchdog 0 */ +#define REALVIEW_WATCHDOG_BASE 0x10010000 /* watchdog interface */ +#define REALVIEW_TIMER0_1_BASE 0x10011000 /* Timer 0 and 1 */ +#define REALVIEW_TIMER2_3_BASE 0x10012000 /* Timer 2 and 3 */ +#define REALVIEW_GPIO0_BASE 0x10013000 /* GPIO port 0 */ +#define REALVIEW_RTC_BASE 0x10017000 /* Real Time Clock */ +#define REALVIEW_TIMER4_5_BASE 0x10018000 /* Timer 4/5 */ +#define REALVIEW_TIMER6_7_BASE 0x10019000 /* Timer 6/7 */ +#define REALVIEW_SCTL_BASE 0x10001000 /* System Controller */ +#define REALVIEW_CLCD_BASE 0x10020000 /* CLCD */ +#define REALVIEW_ONB_SRAM_BASE 0x10060000 /* On-board SRAM */ +#define REALVIEW_DMC_BASE 0x100E0000 /* DMC configuration */ +#define REALVIEW_SMC_BASE 0x100E1000 /* SMC configuration */ +#define REALVIEW_CAN_BASE 0x100E2000 /* CAN bus */ +#define REALVIEW_GIC_CPU_BASE (0x00A00000+0x2000) /* Generic interrupt controller CPU interface */ +#define REALVIEW_FLASH0_BASE 0x40000000 +#define REALVIEW_FLASH0_SIZE SZ_64M +#define REALVIEW_FLASH1_BASE 0x44000000 +#define REALVIEW_FLASH1_SIZE SZ_64M + +#define VEXPRESS_SRAM_BASE 0x48000000 + +#define REALVIEW_ETH_BASE 0x4E000000 /* Ethernet */ +#define VEXPRESS_ETH_BASE 0x4E000000 /* Ethernet */ + +#define REALVIEW_USB_BASE 0x4F000000 /* USB */ +#define REALVIEW_GIC_DIST_BASE (0x00A00000+0x1000) /* Generic interrupt controller distributor */ +#define REALVIEW_LT_BASE 0xC0000000 /* Logic Tile expansion */ +#define REALVIEW_SDRAM6_BASE 0x70000000 /* SDRAM bank 6 256MB */ +#define REALVIEW_SDRAM7_BASE 0x80000000 /* SDRAM bank 7 256MB */ + +#define REALVIEW_SYS_PLD_CTRL1 0x74 + +/* + * PCI regions + */ +#define REALVIEW_PCI_BASE 0x90040000 /* PCI-X Unit base */ +#define REALVIEW_PCI_IO_BASE 0x90050000 /* IO Region on AHB */ +#define REALVIEW_PCI_MEM_BASE 0xA0000000 /* MEM Region on AHB */ + +#define REALVIEW_PCI_BASE_SIZE 0x10000 /* 16 Kb */ +#define REALVIEW_PCI_IO_SIZE 0x1000 /* 4 Kb */ +#define REALVIEW_PCI_MEM_SIZE 0x20000000 /* 512 MB */ + +/* + * Memory definitions + */ +#define REALVIEW_BOOT_ROM_LO 0x30000000 /* DoC Base (64Mb)... */ +#define REALVIEW_BOOT_ROM_HI 0x30000000 +#define REALVIEW_BOOT_ROM_BASE REALVIEW_BOOT_ROM_HI /* Normal position */ +#define REALVIEW_BOOT_ROM_SIZE SZ_64M + +#define REALVIEW_SSRAM_BASE /* REALVIEW_SSMC_BASE ? */ +#define REALVIEW_SSRAM_SIZE SZ_2M + +/* + * SDRAM + */ +#define REALVIEW_SDRAM_BASE 0x00000000 + +/* + * Logic expansion modules + * + */ +#define IRQ_PBA8_GIC_START 32 + +/* + * PB-A8 on-board gic irq sources + */ +#define IRQ_PBA8_WATCHDOG (IRQ_PBA8_GIC_START + 0) /* Watchdog timer */ +#define IRQ_PBA8_SOFT (IRQ_PBA8_GIC_START + 1) /* Software interrupt */ +#define IRQ_PBA8_TIMER0_1 (IRQ_PBA8_GIC_START + 2) /* Timer 0/1 (default timer) */ +#define IRQ_PBA8_TIMER2_3 (IRQ_PBA8_GIC_START + 3) /* Timer 2/3 */ +#define IRQ_PBA8_RTC (IRQ_PBA8_GIC_START + 4) /* Timer 2/3 */ +#define IRQ_VEXPRESS_A9_RTC (IRQ_PBA8_GIC_START + 4) + +#define IRQ_PBA8_UART0 (IRQ_PBA8_GIC_START + 5) /* UART 0 on development chip */ +#define IRQ_PBA8_UART1 (IRQ_PBA8_GIC_START + 6) /* UART 1 on development chip */ +#define IRQ_PBA8_UART2 (IRQ_PBA8_GIC_START + 7) /* UART 2 on development chip */ +#define IRQ_PBA8_UART3 (IRQ_PBA8_GIC_START + 8) /* UART 3 on development chip */ + +#define IRQ_VEXPRESS_A9_KBD (IRQ_PBA8_GIC_START + 12) +#define IRQ_VEXPRESS_A9_MOUSE (IRQ_PBA8_GIC_START + 13) +#define IRQ_VEXPRESS_A9_CLCD (IRQ_PBA8_GIC_START + 14) +#define IRQ_VEXPRESS_A9_ETH (IRQ_PBA8_GIC_START + 15) + +/* 9 reserved */ +#define IRQ_PBA8_SSP (IRQ_PBA8_GIC_START + 11) /* Synchronous Serial Port */ +#define IRQ_PBA8_SCI (IRQ_PBA8_GIC_START + 16) /* Smart Card Interface */ +#define IRQ_PBA8_MMCI0A (IRQ_PBA8_GIC_START + 17) /* Multimedia Card 0A */ +#define IRQ_PBA8_MMCI0B (IRQ_PBA8_GIC_START + 18) /* Multimedia Card 0B */ +#define IRQ_PBA8_AACI (IRQ_PBA8_GIC_START + 19) /* Audio Codec */ +#define IRQ_PBA8_KMI0 (IRQ_PBA8_GIC_START + 20) /* Keyboard/Mouse port 0 */ +#define IRQ_PBA8_KMI1 (IRQ_PBA8_GIC_START + 21) /* Keyboard/Mouse port 1 */ +#define IRQ_PBA8_CHARLCD (IRQ_PBA8_GIC_START + 22) /* Character LCD */ +#define IRQ_PBA8_CLCD (IRQ_PBA8_GIC_START + 23) /* CLCD controller */ +#define IRQ_PBA8_DMAC (IRQ_PBA8_GIC_START + 24) /* DMA controller */ +#define IRQ_PBA8_PWRFAIL (IRQ_PBA8_GIC_START + 25) /* Power failure */ +#define IRQ_PBA8_PISMO (IRQ_PBA8_GIC_START + 26) /* PISMO interface */ +#define IRQ_PBA8_DoC (IRQ_PBA8_GIC_START + 27) /* Disk on Chip memory controller */ +#define IRQ_PBA8_ETH (IRQ_PBA8_GIC_START + 28) /* Ethernet controller */ +#define IRQ_PBA8_USB (IRQ_PBA8_GIC_START + 29) /* USB controller */ +#define IRQ_PBA8_TSPEN (IRQ_PBA8_GIC_START + 30) /* Touchscreen pen */ +#define IRQ_PBA8_TSKPAD (IRQ_PBA8_GIC_START + 31) /* Touchscreen keypad */ + +#define IRQ_PBA8_PMU (IRQ_PBA8_GIC_START + 47) /* Cortex-A8 PMU */ + +/* ... */ +#define IRQ_PBA8_PCI0 (IRQ_PBA8_GIC_START + 50) +#define IRQ_PBA8_PCI1 (IRQ_PBA8_GIC_START + 51) +#define IRQ_PBA8_PCI2 (IRQ_PBA8_GIC_START + 52) +#define IRQ_PBA8_PCI3 (IRQ_PBA8_GIC_START + 53) + +#define IRQ_PBA8_SMC -1 +#define IRQ_PBA8_SCTL -1 + +#define NR_GIC_PBA8 1 + +/* + * Only define NR_IRQS if less than NR_IRQS_PBA8 + */ +#define NR_IRQS_PBA8 (IRQ_PBA8_GIC_START + 64) + +/* ------------------------------------------------------------------------ + * RealView Registers + * ------------------------------------------------------------------------ + * + */ +#define REALVIEW_SYS_ID_OFFSET 0x00 +#define REALVIEW_SYS_SW_OFFSET 0x04 +#define REALVIEW_SYS_LED_OFFSET 0x08 +#define REALVIEW_SYS_OSC0_OFFSET 0x0C + +#define REALVIEW_SYS_OSC1_OFFSET 0x10 +#define REALVIEW_SYS_OSC2_OFFSET 0x14 +#define REALVIEW_SYS_OSC3_OFFSET 0x18 +#define REALVIEW_SYS_OSC4_OFFSET 0x1C /* OSC1 for RealView/AB */ + +#define REALVIEW_SYS_LOCK_OFFSET 0x20 +#define REALVIEW_SYS_100HZ_OFFSET 0x24 +#define REALVIEW_SYS_CFGDATA1_OFFSET 0x28 +#define REALVIEW_SYS_CFGDATA2_OFFSET 0x2C +#define REALVIEW_SYS_FLAGS_OFFSET 0x30 +#define REALVIEW_SYS_FLAGSSET_OFFSET 0x30 +#define REALVIEW_SYS_FLAGSCLR_OFFSET 0x34 +#define REALVIEW_SYS_NVFLAGS_OFFSET 0x38 +#define REALVIEW_SYS_NVFLAGSSET_OFFSET 0x38 +#define REALVIEW_SYS_NVFLAGSCLR_OFFSET 0x3C +#define REALVIEW_SYS_RESETCTL_OFFSET 0x40 +#define REALVIEW_SYS_PCICTL_OFFSET 0x44 +#define REALVIEW_SYS_MCI_OFFSET 0x48 +#define REALVIEW_SYS_FLASH_OFFSET 0x4C +#define REALVIEW_SYS_CLCD_OFFSET 0x50 +#define REALVIEW_SYS_CLCDSER_OFFSET 0x54 +#define REALVIEW_SYS_BOOTCS_OFFSET 0x58 +#define REALVIEW_SYS_24MHz_OFFSET 0x5C +#define REALVIEW_SYS_MISC_OFFSET 0x60 +#define REALVIEW_SYS_IOSEL_OFFSET 0x70 +#define REALVIEW_SYS_PROCID_OFFSET 0x84 +#define REALVIEW_SYS_TEST_OSC0_OFFSET 0xC0 +#define REALVIEW_SYS_TEST_OSC1_OFFSET 0xC4 +#define REALVIEW_SYS_TEST_OSC2_OFFSET 0xC8 +#define REALVIEW_SYS_TEST_OSC3_OFFSET 0xCC +#define REALVIEW_SYS_TEST_OSC4_OFFSET 0xD0 + +#define REALVIEW_SYS_BASE 0x10000000 +#define REALVIEW_SYS_ID (REALVIEW_SYS_BASE + REALVIEW_SYS_ID_OFFSET) +#define REALVIEW_SYS_SW (REALVIEW_SYS_BASE + REALVIEW_SYS_SW_OFFSET) +#define REALVIEW_SYS_LED (REALVIEW_SYS_BASE + REALVIEW_SYS_LED_OFFSET) +#define REALVIEW_SYS_OSC0 (REALVIEW_SYS_BASE + REALVIEW_SYS_OSC0_OFFSET) +#define REALVIEW_SYS_OSC1 (REALVIEW_SYS_BASE + REALVIEW_SYS_OSC1_OFFSET) + +#define REALVIEW_SYS_LOCK (REALVIEW_SYS_BASE + REALVIEW_SYS_LOCK_OFFSET) +#define REALVIEW_SYS_100HZ (REALVIEW_SYS_BASE + REALVIEW_SYS_100HZ_OFFSET) +#define REALVIEW_SYS_CFGDATA1 (REALVIEW_SYS_BASE + REALVIEW_SYS_CFGDATA1_OFFSET) +#define REALVIEW_SYS_CFGDATA2 (REALVIEW_SYS_BASE + REALVIEW_SYS_CFGDATA2_OFFSET) +#define REALVIEW_SYS_FLAGS (REALVIEW_SYS_BASE + REALVIEW_SYS_FLAGS_OFFSET) +#define REALVIEW_SYS_FLAGSSET (REALVIEW_SYS_BASE + REALVIEW_SYS_FLAGSSET_OFFSET) +#define REALVIEW_SYS_FLAGSCLR (REALVIEW_SYS_BASE + REALVIEW_SYS_FLAGSCLR_OFFSET) +#define REALVIEW_SYS_NVFLAGS (REALVIEW_SYS_BASE + REALVIEW_SYS_NVFLAGS_OFFSET) +#define REALVIEW_SYS_NVFLAGSSET (REALVIEW_SYS_BASE + REALVIEW_SYS_NVFLAGSSET_OFFSET) +#define REALVIEW_SYS_NVFLAGSCLR (REALVIEW_SYS_BASE + REALVIEW_SYS_NVFLAGSCLR_OFFSET) +#define REALVIEW_SYS_RESETCTL (REALVIEW_SYS_BASE + REALVIEW_SYS_RESETCTL_OFFSET) +#define REALVIEW_SYS_PCICTL (REALVIEW_SYS_BASE + REALVIEW_SYS_PCICTL_OFFSET) +#define REALVIEW_SYS_MCI (REALVIEW_SYS_BASE + REALVIEW_SYS_MCI_OFFSET) +#define REALVIEW_SYS_FLASH (REALVIEW_SYS_BASE + REALVIEW_SYS_FLASH_OFFSET) +#define REALVIEW_SYS_CLCD (REALVIEW_SYS_BASE + REALVIEW_SYS_CLCD_OFFSET) +#define REALVIEW_SYS_CLCDSER (REALVIEW_SYS_BASE + REALVIEW_SYS_CLCDSER_OFFSET) +#define REALVIEW_SYS_BOOTCS (REALVIEW_SYS_BASE + REALVIEW_SYS_BOOTCS_OFFSET) +#define REALVIEW_SYS_24MHz (REALVIEW_SYS_BASE + REALVIEW_SYS_24MHz_OFFSET) +#define REALVIEW_SYS_MISC (REALVIEW_SYS_BASE + REALVIEW_SYS_MISC_OFFSET) +#define REALVIEW_SYS_IOSEL (REALVIEW_SYS_BASE + REALVIEW_SYS_IOSEL_OFFSET) +#define REALVIEW_SYS_PROCID (REALVIEW_SYS_BASE + REALVIEW_SYS_PROCID_OFFSET) +#define REALVIEW_SYS_TEST_OSC0 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC0_OFFSET) +#define REALVIEW_SYS_TEST_OSC1 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC1_OFFSET) +#define REALVIEW_SYS_TEST_OSC2 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC2_OFFSET) +#define REALVIEW_SYS_TEST_OSC3 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC3_OFFSET) +#define REALVIEW_SYS_TEST_OSC4 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC4_OFFSET) + +#define REALVIEW_SYS_CTRL_LED (1 << 0) + +/* ------------------------------------------------------------------------ + * RealView control registers + * ------------------------------------------------------------------------ + */ + +/* + * REALVIEW_IDFIELD + * + * 31:24 = manufacturer (0x41 = ARM) + * 23:16 = architecture (0x08 = AHB system bus, ASB processor bus) + * 15:12 = FPGA (0x3 = XVC600 or XVC600E) + * 11:4 = build value + * 3:0 = revision number (0x1 = rev B (AHB)) + */ + +/* + * REALVIEW_SYS_LOCK + * control access to SYS_OSCx, SYS_CFGDATAx, SYS_RESETCTL, + * SYS_CLD, SYS_BOOTCS + */ +#define REALVIEW_SYS_LOCK_LOCKED (1 << 16) +#define REALVIEW_SYS_LOCKVAL 0xA05F +#define REALVIEW_SYS_LOCKVAL_MASK 0xFFFF /* write 0xA05F to enable write access */ + +/* + * REALVIEW_SYS_FLASH + */ +#define REALVIEW_FLASHPROG_FLVPPEN (1 << 0) /* Enable writing to flash */ + +/* + * REALVIEW_INTREG + * - used to acknowledge and control MMCI and UART interrupts + */ +#define REALVIEW_INTREG_WPROT 0x00 /* MMC protection status (no interrupt generated) */ +#define REALVIEW_INTREG_RI0 0x01 /* Ring indicator UART0 is asserted, */ +#define REALVIEW_INTREG_CARDIN 0x08 /* MMCI card in detect */ +/* write 1 to acknowledge and clear */ +#define REALVIEW_INTREG_RI1 0x02 /* Ring indicator UART1 is asserted, */ +#define REALVIEW_INTREG_CARDINSERT 0x03 /* Signal insertion of MMC card */ + +/* + * LED settings, bits [7:0] + */ +#define REALVIEW_SYS_LED0 (1 << 0) +#define REALVIEW_SYS_LED1 (1 << 1) +#define REALVIEW_SYS_LED2 (1 << 2) +#define REALVIEW_SYS_LED3 (1 << 3) +#define REALVIEW_SYS_LED4 (1 << 4) +#define REALVIEW_SYS_LED5 (1 << 5) +#define REALVIEW_SYS_LED6 (1 << 6) +#define REALVIEW_SYS_LED7 (1 << 7) + +#define ALL_LEDS 0xFF + +#define LED_BANK REALVIEW_SYS_LED + +/* + * Control registers + */ +#define REALVIEW_IDFIELD_OFFSET 0x0 /* RealView build information */ +#define REALVIEW_FLASHPROG_OFFSET 0x4 /* Flash devices */ +#define REALVIEW_INTREG_OFFSET 0x8 /* Interrupt control */ +#define REALVIEW_DECODE_OFFSET 0xC /* Fitted logic modules */ + +/* + * Clean base - dummy + * + */ +#define CLEAN_BASE REALVIEW_BOOT_ROM_HI + +/* + * System controller bit assignment + */ +#define REALVIEW_REFCLK 0 +#define REALVIEW_TIMCLK 1 + +#define REALVIEW_TIMER1_EnSel 15 +#define REALVIEW_TIMER2_EnSel 17 +#define REALVIEW_TIMER3_EnSel 19 +#define REALVIEW_TIMER4_EnSel 21 + +struct rt_hw_register +{ + unsigned long r0; + unsigned long r1; + unsigned long r2; + unsigned long r3; + unsigned long r4; + unsigned long r5; + unsigned long r6; + unsigned long r7; + unsigned long r8; + unsigned long r9; + unsigned long r10; + unsigned long fp; + unsigned long ip; + unsigned long sp; + unsigned long lr; + unsigned long pc; + unsigned long cpsr; + unsigned long ORIG_r0; +}; + +#include +#include + +/* Interrupt Control Interface */ +#define ARM_GIC_CPU_BASE 0x1E000000 + +/* number of interrupts on board */ +#define ARM_GIC_NR_IRQS 96 +/* only one GIC available */ +#define ARM_GIC_MAX_NR 1 + +#endif + diff --git a/bsp/imx6ull-100ask-smart/drivers/serial.c b/bsp/imx6ull-100ask-smart/drivers/serial.c new file mode 100644 index 0000000000000000000000000000000000000000..38be488c770cdd6ea6341e0702bf5287e4f89e47 --- /dev/null +++ b/bsp/imx6ull-100ask-smart/drivers/serial.c @@ -0,0 +1,271 @@ +/* + * serial.c UART driver + * + * COPYRIGHT (C) 2013, Shanghai Real-Thread Technology Co., Ltd + * + * This file is part of RT-Thread (http://www.rt-thread.org) + * Maintainer: bernard.xiong + * + * All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * Change Logs: + * Date Author Notes + * 2013-03-30 Bernard the first verion + */ + +#include +#include + +#include "serial.h" +#include "board.h" +#include "mmu.h" + +/*根据IMX6ULL芯片手册<<55.15 UART Memory Map/Register Definition>>的3608页，定义UART的结构体,*/ +typedef struct { + volatile unsigned int URXD; /**< UART Receiver Register, offset: 0x0 串口接收寄存器，偏移地址0x0 */ + unsigned char RESERVED_0[60]; + volatile unsigned int UTXD; /**< UART Transmitter Register, offset: 0x40 串口发送寄存器，偏移地址0x40*/ + unsigned char RESERVED_1[60]; + volatile unsigned int UCR1; /**< UART Control Register 1, offset: 0x80 串口控制寄存器1，偏移地址0x80*/ + volatile unsigned int UCR2; /**< UART Control Register 2, offset: 0x84 串口控制寄存器2，偏移地址0x84*/ + volatile unsigned int UCR3; /**< UART Control Register 3, offset: 0x88 串口控制寄存器3，偏移地址0x88*/ + volatile unsigned int UCR4; /**< UART Control Register 4, offset: 0x8C 串口控制寄存器4，偏移地址0x8C*/ + volatile unsigned int UFCR; /**< UART FIFO Control Register, offset: 0x90 串口FIFO控制寄存器，偏移地址0x90*/ + volatile unsigned int USR1; /**< UART Status Register 1, offset: 0x94 串口状态寄存器1，偏移地址0x94*/ +volatile unsigned int USR2; /**< UART Status Register 2, offset: 0x98 串口状态寄存器2，偏移地址0x98*/ + volatile unsigned int UESC; /**< UART Escape Character Register, offset: 0x9C 串口转义字符寄存器，偏移地址0x9C*/ + volatile unsigned int UTIM; /**< UART Escape Timer Register, offset: 0xA0 串口转义定时器寄存器 偏移地址0xA0*/ + volatile unsigned int UBIR; /**< UART BRM Incremental Register, offset: 0xA4 串口二进制倍率增加寄存器 偏移地址0xA4*/ + volatile unsigned int UBMR; /**< UART BRM Modulator Register, offset: 0xA8 串口二进制倍率调节寄存器 偏移地址0xA8*/ + volatile unsigned int UBRC; /**< UART Baud Rate Count Register, offset: 0xAC 串口波特率计数寄存器 偏移地址0xAC*/ + volatile unsigned int ONEMS; /**< UART One Millisecond Register, offset: 0xB0 串口一毫秒寄存器 偏移地址0xB0*/ + volatile unsigned int UTS; /**< UART Test Register, offset: 0xB4 串口测试寄存器 偏移地址0xB4*/ + volatile unsigned int UMCR; /**< UART RS-485 Mode Control Register, offset: 0xB8 串口485模式控制寄存器 偏移地址0xB8*/ +} UART_Type; + + + +struct hw_uart_device +{ + rt_uint32_t hw_base; + rt_uint32_t irqno; +}; + +#define UART_DR(base) __REG32(base + 0x00) +#define UART_FR(base) __REG32(base + 0x18) +#define UART_CR(base) __REG32(base + 0x30) +#define UART_IMSC(base) __REG32(base + 0x38) +#define UART_ICR(base) __REG32(base + 0x44) + +#define UARTFR_RXFE 0x10 +#define UARTFR_TXFF 0x20 +#define UARTIMSC_RXIM 0x10 +#define UARTIMSC_TXIM 0x20 +#define UARTICR_RXIC 0x10 +#define UARTICR_TXIC 0x20 + +static void rt_hw_uart_isr(int irqno, void *param) +{ + struct rt_serial_device *serial = (struct rt_serial_device *)param; + + rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND); +} + +static rt_err_t uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg) +{ + /* 115200,8n1 */ + volatile unsigned int *IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA ; + volatile unsigned int *IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA ; + volatile unsigned int *IOMUXC_UART1_RX_DATA_SELECT_INPUT ; + volatile unsigned int *CCM_CSCDR1; + volatile unsigned int *CCM_CCGR5; + + IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA = (volatile unsigned int *)rt_hw_kernel_phys_to_virt((void *)0x20E0084, 4); + IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA = (volatile unsigned int *)rt_hw_kernel_phys_to_virt((void *)0x20E0088, 4); + IOMUXC_UART1_RX_DATA_SELECT_INPUT = (volatile unsigned int *)rt_hw_kernel_phys_to_virt((void *)0x20E0624, 4); + CCM_CSCDR1 = (volatile unsigned int *)rt_hw_kernel_phys_to_virt((void *)0x020C4024, 4); + CCM_CCGR5 = (volatile unsigned int *)rt_hw_kernel_phys_to_virt((void *)0x020C407C, 4); + + struct hw_uart_device * uart = (struct hw_uart_device *)serial->parent.user_data; + + UART_Type *uart_reg = (UART_Type *)uart->hw_base; + + /* 设置UART的总时钟 + * UART_CLK_ROOT = 80Mhz + */ + *CCM_CSCDR1 &= ~((1<<6) | (0x3f)); + + /* 给UART1模块提供时钟 + * uart1_clk_enable + */ + *CCM_CCGR5 |= (3<<24); + + /* 配置引脚功能 */ + *IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA &= ~0xf; + *IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA &= ~0xf; + + /* IMX6ULL特殊的地方 */ + *IOMUXC_UART1_RX_DATA_SELECT_INPUT |= 3; + + + /* 设置波特率 + * 115200 = 80M/(16*(UBMR+1)/(UBIR+1)) + * UBIR = 15 + * 115200 = 80M/(UBMR+1) + * UBMR = 80,000,000/115200 = 694 - 1 = 693 + * 真正的baudrate = 80,000,000/694 = 115274 + * 先设置UBIR, 后设置UBMR + */ + uart_reg->UFCR |= (5<<7); + uart_reg->UBIR = 15; + uart_reg->UBMR = 693; + + /* 设置数据格式 */ + uart_reg->UCR2 |= (1<<14) | (0<<8) | (0<<6) | (1<<5) | (1<<2) | (1<<1); + + /* IMX6ULL芯片要求必须设置 */ + uart_reg->UCR3 |= (1<<2); + + /* 使能UART */ + uart_reg->UCR1 |= (1<<0); + + return RT_EOK; +} + +static rt_err_t uart_control(struct rt_serial_device *serial, int cmd, void *arg) +{ + struct hw_uart_device *uart; + UART_Type *uart_reg; + + RT_ASSERT(serial != RT_NULL); + uart = (struct hw_uart_device *)serial->parent.user_data; + uart_reg = (UART_Type *)uart->hw_base; + + switch (cmd) + { + case RT_DEVICE_CTRL_CLR_INT: + /* disable rx irq */ + uart_reg->UCR4 &= ~(1<<0); + break; + + case RT_DEVICE_CTRL_SET_INT: + /* enable rx irq */ + uart_reg->UCR4 |= (1<<0); + rt_hw_interrupt_umask(uart->irqno); + break; + } + + return RT_EOK; +} + +static int uart_putc(struct rt_serial_device *serial, char c) +{ + struct hw_uart_device *uart; + UART_Type *uart_reg; + + RT_ASSERT(serial != RT_NULL); + uart = (struct hw_uart_device *)serial->parent.user_data; + uart_reg = (UART_Type *)uart->hw_base; + + while ((uart_reg->USR2 & (1<<3)) == 0); + uart_reg->UTXD = c; + + return 1; +} + +static int uart_getc(struct rt_serial_device *serial) +{ + int ch; + struct hw_uart_device *uart; + UART_Type *uart_reg; + + RT_ASSERT(serial != RT_NULL); + uart = (struct hw_uart_device *)serial->parent.user_data; + uart_reg = (UART_Type *)uart->hw_base; + + if ((uart_reg->USR2 & (1<<0)) == 0) + ch = -1; + else + ch = uart_reg->URXD; + + return ch; +} + +static const struct rt_uart_ops _uart_ops = +{ + uart_configure, + uart_control, + uart_putc, + uart_getc, +}; + +#ifdef RT_USING_UART0 +/* UART device driver structure */ +static struct hw_uart_device _uart0_device = +{ + 0x02020000, /* imx6ull uart1 phy addr */ + 58, /* rx irq */ +}; +static struct rt_serial_device _serial0; +#endif + +#ifdef RT_USING_UART1 +/* UART1 device driver structure */ +static struct hw_uart_device _uart1_device = +{ + REALVIEW_UART1_BASE, + IRQ_PBA8_UART1, +}; +static struct rt_serial_device _serial1; +#endif + +int rt_hw_uart_init(void) +{ + struct hw_uart_device *uart; + struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; + +#ifdef RT_USING_UART0 + _uart0_device.hw_base = (uint32_t)rt_hw_kernel_phys_to_virt((void*)_uart0_device.hw_base, 0x1000); + uart = &_uart0_device; + + _serial0.ops = &_uart_ops; + _serial0.config = config; + + /* register UART1 device */ + rt_hw_serial_register(&_serial0, "uart0", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, + uart); + rt_hw_interrupt_install(uart->irqno, rt_hw_uart_isr, &_serial0, "uart0"); +#endif + +#ifdef RT_USING_UART1 + _uart1_device.hw_base = (uint32_t)rt_hw_kernel_phys_to_virt((void*)_uart1_device.hw_base, 0x1000); + uart = &_uart1_device; + _serial1.ops = &_uart_ops; + _serial1.config = config; + + /* register UART1 device */ + rt_hw_serial_register(&_serial1, "uart1", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, uart); + /* enable Rx and Tx of UART */ + UART_CR(uart->hw_base) = (1 << 0) | (1 << 8) | (1 << 9); + rt_hw_interrupt_install(uart->irqno, rt_hw_uart_isr, &_serial1, "uart1"); +#endif + + return 0; +} +INIT_BOARD_EXPORT(rt_hw_uart_init); diff --git a/bsp/imx6ull-100ask-smart/drivers/serial.h b/bsp/imx6ull-100ask-smart/drivers/serial.h new file mode 100644 index 0000000000000000000000000000000000000000..52e6f07ea399abdcc21a3d21b334db69fe77dddc --- /dev/null +++ b/bsp/imx6ull-100ask-smart/drivers/serial.h @@ -0,0 +1,39 @@ +/* + * UART driver + * + * COPYRIGHT (C) 2013, Shanghai Real-Thread Technology Co., Ltd + * + * This file is part of RT-Thread (http://www.rt-thread.org) + * Maintainer: bernard.xiong + * + * All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * Change Logs: + * Date Author Notes + * 2013-03-30 Bernard the first verion + */ + +#ifndef __UART_H__ +#define __UART_H__ + +#include + +int rt_hw_uart_init(void); + +#endif + + diff --git a/bsp/imx6ull-100ask-smart/drivers/vexpress_a9.h b/bsp/imx6ull-100ask-smart/drivers/vexpress_a9.h new file mode 100644 index 0000000000000000000000000000000000000000..a6467973c5a13c248a088cbb0fad72e640a2b48e --- /dev/null +++ b/bsp/imx6ull-100ask-smart/drivers/vexpress_a9.h @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-03-22 quanzhao first version + */ + +#ifndef __VEXPRESS_A9_H__ +#define __VEXPRESS_A9_H__ + +/* for 'rt_inline' */ +#include +/* SOC-relative definitions */ +#include "realview.h" + +/* the maximum entries of the exception table */ +#define MAX_HANDLERS NR_IRQS_PBA8 + +/* the basic constants and interfaces needed by gic */ +rt_inline rt_uint32_t platform_get_gic_dist_base(void) +{ + return REALVIEW_GIC_DIST_BASE; +} + +rt_inline rt_uint32_t platform_get_gic_cpu_base(void) +{ + return REALVIEW_GIC_CPU_BASE; +} + +#define GIC_IRQ_START 0 + +#define GIC_ACK_INTID_MASK 0x000003ff + +#endif /* __VEXPRESS_A9_H__ */ diff --git a/bsp/imx6ull-100ask-smart/link.lds b/bsp/imx6ull-100ask-smart/link.lds new file mode 100644 index 0000000000000000000000000000000000000000..ab4674d485a4788d467a6b246d2b3e65c2d5559e --- /dev/null +++ b/bsp/imx6ull-100ask-smart/link.lds @@ -0,0 +1,105 @@ +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SECTIONS +{ + /*. = 0x60010000; */ + . = 0xc0010000; + + __text_start = .; + .text : + { + *(.vectors) + *(.text) + *(.text.*) + + /* section information for utest */ + . = ALIGN(4); + __rt_utest_tc_tab_start = .; + KEEP(*(UtestTcTab)) + __rt_utest_tc_tab_end = .; + + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + /* section information for modules */ + . = ALIGN(4); + __rtmsymtab_start = .; + KEEP(*(RTMSymTab)) + __rtmsymtab_end = .; + + /* section information for initialization */ + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + } =0 + __text_end = .; + + .ARM.exidx : + { + __exidx_start = .; + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + __exidx_end = .; + } + + __rodata_start = .; + .rodata : { *(.rodata) *(.rodata.*) } + __rodata_end = .; + + . = ALIGN(4); + .ctors : + { + PROVIDE(__ctors_start__ = .); + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + PROVIDE(__ctors_end__ = .); + } + + .dtors : + { + PROVIDE(__dtors_start__ = .); + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + PROVIDE(__dtors_end__ = .); + } + + . = ALIGN(8); + __data_start = .; + .data : + { + *(.data) + *(.data.*) + } + __data_end = .; + + . = ALIGN(8); + __bss_start = .; + .bss : + { + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(4); + } + . = ALIGN(4); + __bss_end = .; + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + + _end = .; +} diff --git a/bsp/imx6ull-100ask-smart/makefile.targets b/bsp/imx6ull-100ask-smart/makefile.targets new file mode 100644 index 0000000000000000000000000000000000000000..a00129bd90590dcf655a0e6c5ac8f530e7b5c383 --- /dev/null +++ b/bsp/imx6ull-100ask-smart/makefile.targets @@ -0,0 +1,4 @@ +clean2: + -$(RM) $(CC_DEPS)$(C++_DEPS)$(C_UPPER_DEPS)$(CXX_DEPS)$(SECONDARY_FLASH)$(SECONDARY_SIZE)$(ASM_DEPS)$(S_UPPER_DEPS)$(C_DEPS)$(CPP_DEPS) + -$(RM) $(OBJS) *.elf + -@echo ' ' \ No newline at end of file diff --git a/bsp/imx6ull-100ask-smart/mkimage.py b/bsp/imx6ull-100ask-smart/mkimage.py new file mode 100644 index 0000000000000000000000000000000000000000..592f7bb8c0444a9ab77910de2db27e347fc0ce0f --- /dev/null +++ b/bsp/imx6ull-100ask-smart/mkimage.py @@ -0,0 +1,235 @@ +# @Time : 2020/12/31 +# @Author : David Dai +# @File : mkimage.py +#!/usr/bin/python2 + +import os +import argparse +import struct + +parser = argparse.ArgumentParser() + +parser.add_argument('-t', '--type') +parser.add_argument('-b', '--bin') +parser.add_argument('-o', '--out', default = "load.bin") +parser.add_argument('-g', '--img', default = "load.img") +parser.add_argument('-a', '--addr', default = "0x00000000") +parser.add_argument('-e', '--ep', default = "0x00000000") + +args = parser.parse_args() + +args.addr = int(args.addr, 16) +args.ep = int(args.ep, 16) + +def stm32image(): + checksum = 0 + + with open(args.out, 'wb') as f: + #write head 'STM32' + f.write(struct.pack('H', 32)) + f.write(struct.pack('H', (len(dcdConfig) << 3) + 8)) + f.write(struct.pack('H', (len(dcdConfig) << 3) + 4)) + f.write(struct.pack('I', int(d[0], 16))) + f.write(struct.pack('>I', int(d[1], 16))) + + #padding data + for i in range(0x27B): + f.write(struct.pack(' rtt.asm\n' +POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' +\ + 'python mkimage.py ' + MKIMAGE + '\n'