MEMORY { PAGE 0 : /* BEGIN is used for the "boot to SARAM" bootloader mode */ BEGIN : origin = 0x000000, length = 0x000002 RAMM0 : origin = 0x000080, length = 0x000380 RAMD0 : origin = 0x00B000, length = 0x000800 RAMLS0 : origin = 0x008000, length = 0x000800 RAMLS1 : origin = 0x008800, length = 0x000800 RAMLS2 : origin = 0x009000, length = 0x000800 RAMLS3 : origin = 0x009800, length = 0x000800 RAMLS4 : origin = 0x00A000, length = 0x000800 RESET : origin = 0x3FFFC0, length = 0x000002 PAGE 1 : BOOT_RSVD : origin = 0x000002, length = 0x00007E /* Part of M0, BOOT rom will use this for stack */ RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */ RAMD1 : origin = 0x00B800, length = 0x000800 RAMLS5 : origin = 0x00A800, length = 0x000800 CANA_MSG_RAM : origin = 0x049000, length = 0x000800 CANB_MSG_RAM : origin = 0x04B000, length = 0x000800 CPU2TOCPU1RAM : origin = 0x03F800, length = 0x000400 CPU1TOCPU2RAM : origin = 0x03FC00, length = 0x000400 } SECTIONS { codestart : > BEGIN, PAGE = 0 .text : >>RAMD0 | RAMLS0 | RAMLS1 | RAMLS2 | RAMLS3 | RAMLS4, PAGE = 0 .cinit : > RAMM0, PAGE = 0 .pinit : > RAMM0, PAGE = 0 .switch : > RAMM0, PAGE = 0 .reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */ .stack : > RAMM1, PAGE = 1 .ebss : > RAMLS5, PAGE = 1 .econst : > RAMLS5, PAGE = 1 .esysmem : > RAMLS5, PAGE = 1 #ifdef __TI_COMPILER_VERSION__ #if __TI_COMPILER_VERSION__ >= 15009000 .TI.ramfunc : {} > RAMM0, PAGE = 0 #else ramfuncs : > RAMM0 PAGE = 0 #endif #endif /* The following section definitions are required when using the IPC API Drivers */ GROUP : > CPU2TOCPU1RAM, PAGE = 1 { PUTBUFFER PUTWRITEIDX GETREADIDX } GROUP : > CPU1TOCPU2RAM, PAGE = 1 { GETBUFFER : TYPE = DSECT GETWRITEIDX : TYPE = DSECT PUTREADIDX : TYPE = DSECT } } /* //=========================================================================== // End of file. //=========================================================================== */